Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362042
F. Neppl, F. Fischer, U. Schwabe
It is shown, that a thin TaSix layer underneath the Al based metallization considerably improves the contacts from the metallization to shallow diffusion regions in Si. TaSiX with x 2 acts as a barrier against Al and Si diffusion at the contacts and thus impedes Al spiking as well as Si precipitates in the contacts. Furthermore the high current induced Si erosion is reduced by one order of magnitude. The contact resistance to n+-Si is decreased by a factor 3-5. Finally the TaSiX provides a low barrier Schottky diode on lightly doped n-Si and p-Si.
{"title":"TaSix as a Barrier Between Al-Based Metallization and N+- and P+-SI for Reliable VLSI Contacts","authors":"F. Neppl, F. Fischer, U. Schwabe","doi":"10.1109/IRPS.1984.362042","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362042","url":null,"abstract":"It is shown, that a thin TaSix layer underneath the Al based metallization considerably improves the contacts from the metallization to shallow diffusion regions in Si. TaSiX with x 2 acts as a barrier against Al and Si diffusion at the contacts and thus impedes Al spiking as well as Si precipitates in the contacts. Furthermore the high current induced Si erosion is reduced by one order of magnitude. The contact resistance to n+-Si is decreased by a factor 3-5. Finally the TaSiX provides a low barrier Schottky diode on lightly doped n-Si and p-Si.","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122893362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362036
A. Sabnis
With the continuing progress in the Si-VLSI technology from one generation to the next, the number of ion-implantation and dry-etching processes which cause damages to the Si/SiO2 interface region has increased, while at the same time the oxidation and annealing temperatures have decreased, The net impact is manifested as a significant monotonic decrease in the low-field mobility of the inversion layer electrons. Furthermore, the response of the interface to the CO60 source of gamma rays, and the effects of radiation damage on the rate of drift in MOSFETs due to injection of hot-carriers, suggest that the advances in technology have increased the susceptibility of IC's to hot-carrier injection related drifts.
{"title":"Impact Of Advances In Technology On The Properties Of Si/SiO2 Interface","authors":"A. Sabnis","doi":"10.1109/IRPS.1984.362036","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362036","url":null,"abstract":"With the continuing progress in the Si-VLSI technology from one generation to the next, the number of ion-implantation and dry-etching processes which cause damages to the Si/SiO2 interface region has increased, while at the same time the oxidation and annealing temperatures have decreased, The net impact is manifested as a significant monotonic decrease in the low-field mobility of the inversion layer electrons. Furthermore, the response of the interface to the CO60 source of gamma rays, and the effects of radiation damage on the rate of drift in MOSFETs due to injection of hot-carriers, suggest that the advances in technology have increased the susceptibility of IC's to hot-carrier injection related drifts.","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128049894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362049
Kathryn Alexander, J. Hicks, T. Soukup
A unique U. V. transmissive passivation process for One Time Programmable EPROMS has been developed which provides moisture resistance for the plastic encapsulated devices and allows erasure of hermetic devices. This passivation, which consists of a two layer film of plasma enhanced CVD oxynitride and phosphorus doped oxide, requires no change in current interlayer dielectric, metal composition or circuit layout. This approach is novel in that it continues to utilize 9% to 10% phosphorus doped CVD oxide as an interlayer dielectric, while most plastic compatable processes require control of phosphorus concentration to approximately 7%. Observed moisture related failure mechanisms, which include single bit charge loss, metal line corrosion and input/output leakage, were investigated and related to specific processing parameters. Processing limits were then determined to eliminate these failure modes.
{"title":"Moisture Resistive, U. V. Transmissive Passivation for Plastic Encapsulated EPROM Devices","authors":"Kathryn Alexander, J. Hicks, T. Soukup","doi":"10.1109/IRPS.1984.362049","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362049","url":null,"abstract":"A unique U. V. transmissive passivation process for One Time Programmable EPROMS has been developed which provides moisture resistance for the plastic encapsulated devices and allows erasure of hermetic devices. This passivation, which consists of a two layer film of plasma enhanced CVD oxynitride and phosphorus doped oxide, requires no change in current interlayer dielectric, metal composition or circuit layout. This approach is novel in that it continues to utilize 9% to 10% phosphorus doped CVD oxide as an interlayer dielectric, while most plastic compatable processes require control of phosphorus concentration to approximately 7%. Observed moisture related failure mechanisms, which include single bit charge loss, metal line corrosion and input/output leakage, were investigated and related to specific processing parameters. Processing limits were then determined to eliminate these failure modes.","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122151728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362012
J. Klema, R. Pyle, E. Domangue
Aluminum/Silicon (Al/Si) sputtered metal films for MOS integrated circuit metalization deposited under conditions of nitrogen contamination coupled with a subsequent silicon nitride (Si3N4) passivation can seriously impact product relialility. The reliability implications of this sputtered metallization process will be discussed. The discussion will include film characteristics and structure, description f the failure mechanism, life modeling, accelerated testing, and electromigration behavior.
{"title":"Reliability Implications of Nitrogen Contamination During Deposition of Sputtered Aluminum/Silicon Metal Films","authors":"J. Klema, R. Pyle, E. Domangue","doi":"10.1109/IRPS.1984.362012","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362012","url":null,"abstract":"Aluminum/Silicon (Al/Si) sputtered metal films for MOS integrated circuit metalization deposited under conditions of nitrogen contamination coupled with a subsequent silicon nitride (Si3N4) passivation can seriously impact product relialility. The reliability implications of this sputtered metallization process will be discussed. The discussion will include film characteristics and structure, description f the failure mechanism, life modeling, accelerated testing, and electromigration behavior.","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122346136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362013
J. Curry, G. Fitzgibbon, Y. Guan, R. Muollo, G. Nelson, A. Thomas
A new failure mechanism resulting in open metal bit- lines was observed during reliability testing of vendor 64k dynamic random access memory (RAIM) products using sputtered Al-Si metallurgy. Life test data, physical failure analysis, and metal film characterization are presented, The observed phenomenan is not strictly electromigratiotn, but rather a temperature-dependent metal-deformation process, such as creep, resulting in intergranular fracture.
{"title":"New Failure Mechanisms in Sputtered Aluminum-Silicon Films","authors":"J. Curry, G. Fitzgibbon, Y. Guan, R. Muollo, G. Nelson, A. Thomas","doi":"10.1109/IRPS.1984.362013","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362013","url":null,"abstract":"A new failure mechanism resulting in open metal bit- lines was observed during reliability testing of vendor 64k dynamic random access memory (RAIM) products using sputtered Al-Si metallurgy. Life test data, physical failure analysis, and metal film characterization are presented, The observed phenomenan is not strictly electromigratiotn, but rather a temperature-dependent metal-deformation process, such as creep, resulting in intergranular fracture.","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"08 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127184895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362016
D. Dening, D. Lacombe, A. Christou
Silicon based I2 L circuits have survived a life test for over 5000 hours at 340°C without degradation. These chips used aluminum metallization with current densities below 10,000 amp/sq.cm to avoid electromigration failures. The need for a gold based metal system for high temperature applications has lead to the development of Ti-W diffusion barriers which have withstood temperatures of 360°C for longer than 3500 hours without change. MSI integrated circuits with a Ti-W/Au metallization system have withstood stress tests of over 2000 hours at 360°C. Gold hillock formation has been shown to be caused by the compressive strains induced in the gold film by thermal expansion mismatches. The driving force for gold hillock formation may be eliminated by depositing the gold film at elevated temperatures.
{"title":"Reliability of High Temperature I2L Integrated Circuits","authors":"D. Dening, D. Lacombe, A. Christou","doi":"10.1109/IRPS.1984.362016","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362016","url":null,"abstract":"Silicon based I2 L circuits have survived a life test for over 5000 hours at 340°C without degradation. These chips used aluminum metallization with current densities below 10,000 amp/sq.cm to avoid electromigration failures. The need for a gold based metal system for high temperature applications has lead to the development of Ti-W diffusion barriers which have withstood temperatures of 360°C for longer than 3500 hours without change. MSI integrated circuits with a Ti-W/Au metallization system have withstood stress tests of over 2000 hours at 360°C. Gold hillock formation has been shown to be caused by the compressive strains induced in the gold film by thermal expansion mismatches. The driving force for gold hillock formation may be eliminated by depositing the gold film at elevated temperatures.","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127488268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362014
S. O'Donnell, J. Bartling, G. Hill
A significant reliability related problem was detected during the course of a failure analysis performed on a 16K dynamic RAM. The problem was due to the presence of large silicon nodules in the aluminum metalization which, in comparison to the cross-sectional area of the metal stripe, were large enough to severely restrict current flow. Although silicon nodule formation, has been previously analyzed as a processing variable, it has not been regarded as a significant reliability concern at normal die temperatures. With the advent of VLSI technology and the resultant shrinking line widths, nodule formations must be re- evaluated as a potential yield and reliability concern. The nodule problem becomes serious when the nodule size reduces the effective metal line cross- sectional area such that significant current flow restriction occurs. MIL-STD-883C, Method 2018, Scanning Electron Microscope (SEM) examination procedures also do not readily detect these silicon nodules; nor do most other normal industry screening procedures. This paper discusses techniques used to locate the nodules, comparison of several different vendors product, theory of silicon nodule formation, ramifications to the VLSI industry and the reliability risk to the end user.
{"title":"Silicon Inclusions in Aluminum Interconnects","authors":"S. O'Donnell, J. Bartling, G. Hill","doi":"10.1109/IRPS.1984.362014","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362014","url":null,"abstract":"A significant reliability related problem was detected during the course of a failure analysis performed on a 16K dynamic RAM. The problem was due to the presence of large silicon nodules in the aluminum metalization which, in comparison to the cross-sectional area of the metal stripe, were large enough to severely restrict current flow. Although silicon nodule formation, has been previously analyzed as a processing variable, it has not been regarded as a significant reliability concern at normal die temperatures. With the advent of VLSI technology and the resultant shrinking line widths, nodule formations must be re- evaluated as a potential yield and reliability concern. The nodule problem becomes serious when the nodule size reduces the effective metal line cross- sectional area such that significant current flow restriction occurs. MIL-STD-883C, Method 2018, Scanning Electron Microscope (SEM) examination procedures also do not readily detect these silicon nodules; nor do most other normal industry screening procedures. This paper discusses techniques used to locate the nodules, comparison of several different vendors product, theory of silicon nodule formation, ramifications to the VLSI industry and the reliability risk to the end user.","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133787800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362038
S. Shabde, George B. Simmons, A. Baluni, D. Back
A new type of failure mode of the gate dielectric breakdown in an MOS transistor induced by the snapback phenomena is reported. Unlike a typical gate oxide breakdown which is caused by a voltage stress on the gate, this failure mode is caused by a source-drain bipolar current resulting from the snapback action. This failure mode results in a gate-to-drain short, and was found to require a minimum critical current, Idcrit, after the transistor goes in the snapback. The failure node is exhibited in the input protection structures used in an MOS circuit. The incidence of the failure mode increased with increasing grading of the source-drain junction. (i.e., the Idcrit decreased as the junction grading increased). The ESD breakdown of the inputs are also shown to be a direct result of this failure mode
{"title":"Snapback Induced Gate Dielectric Breakdown in Graded Junction MOS Structures","authors":"S. Shabde, George B. Simmons, A. Baluni, D. Back","doi":"10.1109/IRPS.1984.362038","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362038","url":null,"abstract":"A new type of failure mode of the gate dielectric breakdown in an MOS transistor induced by the snapback phenomena is reported. Unlike a typical gate oxide breakdown which is caused by a voltage stress on the gate, this failure mode is caused by a source-drain bipolar current resulting from the snapback action. This failure mode results in a gate-to-drain short, and was found to require a minimum critical current, Idcrit, after the transistor goes in the snapback. The failure node is exhibited in the input protection structures used in an MOS circuit. The incidence of the failure mode increased with increasing grading of the source-drain junction. (i.e., the Idcrit decreased as the junction grading increased). The ESD breakdown of the inputs are also shown to be a direct result of this failure mode","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116609998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362051
D. Bergeron, J. P. Kent, K. Morrett
This paper describes a polyimide interlevel metal insulation process. The use of polyimide near high voltage devices can result in anomalous leakage in certain regions at elevated temperatures. The paper summarizes the reliability investigation on discrete devices fabricated with polyimide, as the interlevel material, as well as characterization data which support design criteria permitting the use of polyimide as an interlevel insulation material.
{"title":"Polyimide Interlevel Insulation Process/Design Limitations","authors":"D. Bergeron, J. P. Kent, K. Morrett","doi":"10.1109/IRPS.1984.362051","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362051","url":null,"abstract":"This paper describes a polyimide interlevel metal insulation process. The use of polyimide near high voltage devices can result in anomalous leakage in certain regions at elevated temperatures. The paper summarizes the reliability investigation on discrete devices fabricated with polyimide, as the interlevel material, as well as characterization data which support design criteria permitting the use of polyimide as an interlevel insulation material.","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115458947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-04-01DOI: 10.1109/IRPS.1984.362033
E. Domangue, R. Rivera, Clark G. Shepard
Large MOS capacitors were used in a study of the dielectric breakdown mechanism to establish the relationship among the results of various test methods. Reliance on models was avoided through the use of a test vehicle which duplicated the structures of a 64K dynamic memory device. A method is proposed to predict device reliability using process monitors at the time of wafer manufacture.
{"title":"Reliability Prediction using Large MOS Capacitors","authors":"E. Domangue, R. Rivera, Clark G. Shepard","doi":"10.1109/IRPS.1984.362033","DOIUrl":"https://doi.org/10.1109/IRPS.1984.362033","url":null,"abstract":"Large MOS capacitors were used in a study of the dielectric breakdown mechanism to establish the relationship among the results of various test methods. Reliance on models was avoided through the use of a test vehicle which duplicated the structures of a 64K dynamic memory device. A method is proposed to predict device reliability using process monitors at the time of wafer manufacture.","PeriodicalId":326004,"journal":{"name":"22nd International Reliability Physics Symposium","volume":"259 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115385014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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