Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406988
Liuyan Chen, Qi Cheng, Jianping Guo, Min Chen
A CMOS low-dropout regulator (LDO) with high power-supply ripple rejection (PSR) across a wide frequency range is presented and designed in 0.18-μm CMOS technology. Targeting for the application of energy-autonomous biomedical implants, it has a very simple structure and features low power consumption. The high PSR in low frequency range is realized by the proposed embedded supply ripple feed-forward technique. Moreover, the PSR bandwidth is improved up to several MHz by adopting an energy-efficient double zero compensation network. With a 4.7-μF ceramic output capacitor, in the maximum loading condition (i.e., 25 mA), the simulated PSR is no less than -86 dB from DC to 10 kHz, and better than -63 dB up to 10 MHz. The quiescent current is just 10 μA. The line and load regulations are 0.5 mV/V @ 25-mA loading and 0.14 mV/mA @ 1.3-V Vin, respectively. The overshoot and undershoot voltages are less than 2 mV when loading current changes between 0 and 25 mA.
{"title":"High-PSR CMOS LDO with embedded ripple feedforward and energy-efficient bandwidth extension","authors":"Liuyan Chen, Qi Cheng, Jianping Guo, Min Chen","doi":"10.1109/SOCC.2015.7406988","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406988","url":null,"abstract":"A CMOS low-dropout regulator (LDO) with high power-supply ripple rejection (PSR) across a wide frequency range is presented and designed in 0.18-μm CMOS technology. Targeting for the application of energy-autonomous biomedical implants, it has a very simple structure and features low power consumption. The high PSR in low frequency range is realized by the proposed embedded supply ripple feed-forward technique. Moreover, the PSR bandwidth is improved up to several MHz by adopting an energy-efficient double zero compensation network. With a 4.7-μF ceramic output capacitor, in the maximum loading condition (i.e., 25 mA), the simulated PSR is no less than -86 dB from DC to 10 kHz, and better than -63 dB up to 10 MHz. The quiescent current is just 10 μA. The line and load regulations are 0.5 mV/V @ 25-mA loading and 0.14 mV/mA @ 1.3-V Vin, respectively. The overshoot and undershoot voltages are less than 2 mV when loading current changes between 0 and 25 mA.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127372715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406906
S. Jung, Janet Roveda
This paper presents a novel adaptive-bandwidth phase-locked loop (PLL) using a closed loop voltage controlled oscillator (VCO). The adaptive-bandwidth PLL uses the gain of closed loop VCO to obtain a constant unity gain bandwidth over an operating frequency range. Furthermore, a charge pump (CP) current is proportional to the current of VCO so that CP current is in proportion to the VCO frequency. Since the adaptive-bandwidth is optimized over the VCO frequency, an integrated RMS jitter is reduced in comparison to a conventional fixed-bandwidth PLL. We simulate the proposed PLL in 130 nm CMOS technology at 1.2 V power supply. The integrated RMS jitter of the proposed adaptive-bandwidth PLL is 2.35 psec which is 70% smaller than the conventional PLL. This adaptive-bandwidth PLL consumes 2.6 mW at 2.56 GHz output frequency.
{"title":"A 320MHz–2.56GHz low jitter phase-locked loop with adaptive-bandwidth technique","authors":"S. Jung, Janet Roveda","doi":"10.1109/SOCC.2015.7406906","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406906","url":null,"abstract":"This paper presents a novel adaptive-bandwidth phase-locked loop (PLL) using a closed loop voltage controlled oscillator (VCO). The adaptive-bandwidth PLL uses the gain of closed loop VCO to obtain a constant unity gain bandwidth over an operating frequency range. Furthermore, a charge pump (CP) current is proportional to the current of VCO so that CP current is in proportion to the VCO frequency. Since the adaptive-bandwidth is optimized over the VCO frequency, an integrated RMS jitter is reduced in comparison to a conventional fixed-bandwidth PLL. We simulate the proposed PLL in 130 nm CMOS technology at 1.2 V power supply. The integrated RMS jitter of the proposed adaptive-bandwidth PLL is 2.35 psec which is 70% smaller than the conventional PLL. This adaptive-bandwidth PLL consumes 2.6 mW at 2.56 GHz output frequency.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127497220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406926
J. N. Tripathi, Hiten Advani, R. Nagpal, V. Sharma, Rakesh Malik
An analysis of power supply induced jitter in a high speed serial link is presented in this paper. An equivalent reduced model for serial link is used for the analysis. Jitter induced by the ripples in power delivery network is analyzed by a small signal equivalent model. The effect is modeled by a transfer function which is not technology specific and can be used generically for System-On-Chip (SoC) level design considerations. The analysis is supported by experimental results by simulation in 130nm BiCMoS RF technology and 28nm FDSOI technology (both technologies are of STMicroelectronics).
{"title":"Analysis of a serial link for power supply induced jitter","authors":"J. N. Tripathi, Hiten Advani, R. Nagpal, V. Sharma, Rakesh Malik","doi":"10.1109/SOCC.2015.7406926","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406926","url":null,"abstract":"An analysis of power supply induced jitter in a high speed serial link is presented in this paper. An equivalent reduced model for serial link is used for the analysis. Jitter induced by the ripples in power delivery network is analyzed by a small signal equivalent model. The effect is modeled by a transfer function which is not technology specific and can be used generically for System-On-Chip (SoC) level design considerations. The analysis is supported by experimental results by simulation in 130nm BiCMoS RF technology and 28nm FDSOI technology (both technologies are of STMicroelectronics).","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"20 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132359034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406888
G. Rincón-Mora
A challenge wireless micro-sensors and other microsystems face is short lifetime, because tiny batteries store little energy. Although miniaturized fuel cells and atomic sources store more energy than lithium ions and super capacitors, they source less power, so they cannot power as many functions. Unfortunately, their power-dense counterparts cannot sustain life for long. Thankfully, the environment also holds vast amounts of energy, and of typical sources, like light, motion, temperature, and radiation, sunlight produces the highest power density, but only when available. The fact is, combining miniaturized fuel or photovoltaic cells with tiny lithium-ion batteries or super capacitors can be more compact, reliable, and longer lasting than any single technology. Managing a hybrid system of this sort to supply a microwatt application, however, requires an intelligent, low-loss dc-dc power converter. This talk discusses the state of the art in miniaturized charger-supply systems that draw power from an energy-dense dc source and supplementary power from a battery to supply a load and recharge the battery with excess power from the energy-dense source.
{"title":"Session T4A: Tutorial: Tiny DC-sourced single inductor charge-supply ICs","authors":"G. Rincón-Mora","doi":"10.1109/SOCC.2015.7406888","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406888","url":null,"abstract":"A challenge wireless micro-sensors and other microsystems face is short lifetime, because tiny batteries store little energy. Although miniaturized fuel cells and atomic sources store more energy than lithium ions and super capacitors, they source less power, so they cannot power as many functions. Unfortunately, their power-dense counterparts cannot sustain life for long. Thankfully, the environment also holds vast amounts of energy, and of typical sources, like light, motion, temperature, and radiation, sunlight produces the highest power density, but only when available. The fact is, combining miniaturized fuel or photovoltaic cells with tiny lithium-ion batteries or super capacitors can be more compact, reliable, and longer lasting than any single technology. Managing a hybrid system of this sort to supply a microwatt application, however, requires an intelligent, low-loss dc-dc power converter. This talk discusses the state of the art in miniaturized charger-supply systems that draw power from an energy-dense dc source and supplementary power from a battery to supply a load and recharge the battery with excess power from the energy-dense source.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128590385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Distributed Video Coding (DVC) is a novel scheme which is different from the state-of-the-art video compression standards. A specific characteristic of DVC is its use of a low complexity encoder. However, there exists an issue on the DVC, which requires redundant decoding time. Therefore, low-complexity motion estimation algorithm and skip mode have been applied to the encoder of a hybrid DVC to reduce half of the decoding time. The computational complexity of the encoder only increases slightly with respect to the hybrid DVC, which is still far less than H.264/AVC no motion. In some cases, the encoding time is even reduced instead of being increased. Besides, the rate-distortion performance is improved in high motion videos. However, the rate-distortion performance does not decrease in the static video, because of the added motion estimation.
{"title":"An improved distributed video coding with low-complexity motion estimation at encoder","authors":"Hsin-Ping Yang, Hsiao-Chi Hsieh, Sheng-Hsiang Chang, Sao-Jie Chen","doi":"10.1109/SOCC.2015.7406923","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406923","url":null,"abstract":"Distributed Video Coding (DVC) is a novel scheme which is different from the state-of-the-art video compression standards. A specific characteristic of DVC is its use of a low complexity encoder. However, there exists an issue on the DVC, which requires redundant decoding time. Therefore, low-complexity motion estimation algorithm and skip mode have been applied to the encoder of a hybrid DVC to reduce half of the decoding time. The computational complexity of the encoder only increases slightly with respect to the hybrid DVC, which is still far less than H.264/AVC no motion. In some cases, the encoding time is even reduced instead of being increased. Besides, the rate-distortion performance is improved in high motion videos. However, the rate-distortion performance does not decrease in the static video, because of the added motion estimation.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117331280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406901
Jun Guo, Peng Liu, Weidong Wang, Jicheng Chen, Yingtao Jiang
Duty-cycle correctors (DCCs) are employed in most high-speed VLSI systems to calibrate the clock duty-cycle at 50% to reduce the deterministic jitter introduced by duty-cycle distortion. An all-analogue feedback DCC circuitry with high working frequency, low jitter, high accuracy, and wide correction range is proposed in this paper. A common mode voltage adjuster and an active feedback amplifier are used to support the DCC to work at a high frequency up to 20 GHz with a wide correction range from 20% to 80%. On the feedback path, a second order duty cycle detector scheme is adopted including a low pass filter and an integrator to significantly reduce the jitter in the output clock and ensure high correction accuracy. Through simulation using 65 nm TSMC CMOS technology, the output duty cycle is corrected to 50±0.3% over the input duty-cycle range of 20-80% for 12.5-20 GHz. The DCC consumes 5.2 mW at 16 GHz using a 1.0 V supply voltage, and has a 572 fs peak-to-peak jitter and a 249 fs RMS jitter.
{"title":"A 20 GHz high speed, low jitter, high accuracy and wide correction range duty cycle corrector","authors":"Jun Guo, Peng Liu, Weidong Wang, Jicheng Chen, Yingtao Jiang","doi":"10.1109/SOCC.2015.7406901","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406901","url":null,"abstract":"Duty-cycle correctors (DCCs) are employed in most high-speed VLSI systems to calibrate the clock duty-cycle at 50% to reduce the deterministic jitter introduced by duty-cycle distortion. An all-analogue feedback DCC circuitry with high working frequency, low jitter, high accuracy, and wide correction range is proposed in this paper. A common mode voltage adjuster and an active feedback amplifier are used to support the DCC to work at a high frequency up to 20 GHz with a wide correction range from 20% to 80%. On the feedback path, a second order duty cycle detector scheme is adopted including a low pass filter and an integrator to significantly reduce the jitter in the output clock and ensure high correction accuracy. Through simulation using 65 nm TSMC CMOS technology, the output duty cycle is corrected to 50±0.3% over the input duty-cycle range of 20-80% for 12.5-20 GHz. The DCC consumes 5.2 mW at 16 GHz using a 1.0 V supply voltage, and has a 572 fs peak-to-peak jitter and a 249 fs RMS jitter.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127594582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406956
Chun-Ying Huang, Po-Tsang Huang, Chih-Chao Yang, C. Chuang, W. Hwang
For energy-limited applications of electronic nose, an application-specific architecture is essential to realize a low-energy gas recognition system. In this paper, a pseudo-zero-leakage gas recognition system is proposed to recognize different gases using event-driven power control. Additionally, this gas recognition system can recognize four different gases with concentration information by drift-insensitive on-line training, achieving 100% recognition accuracy for gas type and 89.4% accuracy for concentration analysis. For further reducing the overall energy consumption, both near-threshold SRAM and low-voltage embedded ReRAM are integrated into the proposed system, respectively. Based on TSMC 65nm LP CMOS process, the total energy of the gas recognition systems with SRAM and ReRAM are only 8.62μJ and 2.04μJ in a sensing period, respectively. Hence, an energy-efficient gas recognition system can be realized by a pseudo-zero-leakage event-driven structure with ReRAM.
{"title":"Energy-efficient gas recognition system with event-driven power control","authors":"Chun-Ying Huang, Po-Tsang Huang, Chih-Chao Yang, C. Chuang, W. Hwang","doi":"10.1109/SOCC.2015.7406956","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406956","url":null,"abstract":"For energy-limited applications of electronic nose, an application-specific architecture is essential to realize a low-energy gas recognition system. In this paper, a pseudo-zero-leakage gas recognition system is proposed to recognize different gases using event-driven power control. Additionally, this gas recognition system can recognize four different gases with concentration information by drift-insensitive on-line training, achieving 100% recognition accuracy for gas type and 89.4% accuracy for concentration analysis. For further reducing the overall energy consumption, both near-threshold SRAM and low-voltage embedded ReRAM are integrated into the proposed system, respectively. Based on TSMC 65nm LP CMOS process, the total energy of the gas recognition systems with SRAM and ReRAM are only 8.62μJ and 2.04μJ in a sensing period, respectively. Hence, an energy-efficient gas recognition system can be realized by a pseudo-zero-leakage event-driven structure with ReRAM.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126076531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406940
Dongliang Chen, Xin Wang, Jinhui Wang, Na Gong
Mobile devices have become the most important way to deliver the videos. Experience and battery life are two major considerations for the mobile users. To be the first time, this paper relates these two together and presents a Viewing Context Aware SRAM (VCAS). The viewing contexts significantly influence the user experience and in the worse context, users have higher tolerance to the video noise. Based on this, we introduce hardware noise in high-tolerance viewing surroundings to achieve more power savings. To meet the low area constraint of mobile devices, we develop an efficient hardware scheme to implement VCAS which induces negligible area overhead. The experimental results based on 45-nm CMOS technology show that, as compared to the conventional SRAM design, VCAS can achieve 32.6% power savings without perceivable quality loss.
{"title":"VCAS: Viewing context aware power-efficient mobile video embedded memory","authors":"Dongliang Chen, Xin Wang, Jinhui Wang, Na Gong","doi":"10.1109/SOCC.2015.7406940","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406940","url":null,"abstract":"Mobile devices have become the most important way to deliver the videos. Experience and battery life are two major considerations for the mobile users. To be the first time, this paper relates these two together and presents a Viewing Context Aware SRAM (VCAS). The viewing contexts significantly influence the user experience and in the worse context, users have higher tolerance to the video noise. Based on this, we introduce hardware noise in high-tolerance viewing surroundings to achieve more power savings. To meet the low area constraint of mobile devices, we develop an efficient hardware scheme to implement VCAS which induces negligible area overhead. The experimental results based on 45-nm CMOS technology show that, as compared to the conventional SRAM design, VCAS can achieve 32.6% power savings without perceivable quality loss.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"35 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121000710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406964
Weng-Chung Tsai, Hsiao-En Lin, Ying-Cherng Lan, Sao-Jie Chen, Y. Hu
An enhanced on-chip network resource allocation method is developed for the Bi-directional Network-on-Chip (BiNoC) platform. Specifically, a novel flow Fluidity Meter (FM) is proposed to provide the real-time estimate of bandwidth utilization of the Virtual Channel (VC) buffer in a BiNoC router. The degree of fluidity of a packet transfer in each router is a reliable, yet low-cost method for measuring bandwidth utilization in the VC. We show that the overhead implementing this FM is very affordable. Finally, extensive simulation results verify that this proposed FM approach achieves superior performance compared to existing BiNoC resource allocation methods.
{"title":"A novel flow fluidity meter for BiNoC bandwidth resource allocation","authors":"Weng-Chung Tsai, Hsiao-En Lin, Ying-Cherng Lan, Sao-Jie Chen, Y. Hu","doi":"10.1109/SOCC.2015.7406964","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406964","url":null,"abstract":"An enhanced on-chip network resource allocation method is developed for the Bi-directional Network-on-Chip (BiNoC) platform. Specifically, a novel flow Fluidity Meter (FM) is proposed to provide the real-time estimate of bandwidth utilization of the Virtual Channel (VC) buffer in a BiNoC router. The degree of fluidity of a packet transfer in each router is a reliable, yet low-cost method for measuring bandwidth utilization in the VC. We show that the overhead implementing this FM is very affordable. Finally, extensive simulation results verify that this proposed FM approach achieves superior performance compared to existing BiNoC resource allocation methods.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126550231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406951
Yujin Park, Han Yang, Hyunjong Kim, Jun Soo Cho, Suhwan Kim
This paper presents a low noise output stage of oversampling audio digital-to-analog converter (DAC). The proposed glitchless switched capacitor DAC (GSC-DAC) eliminates the penalty of a constrained signal range and a signal distortion caused by return-to-zero signals in SC-DAC that is an essential part in order to convert the digital signal into the analog signal. By using a track and hold circuit and deglitching method in GSC-DAC, the low noise is efficiently achieved. The results of post layout simulation show the noise performance improvements of 21dB on average of SNR, SNDR, SFDR and THD in comparison with the absence of the proposed techniques.
{"title":"Low noise output stage for oversampling audio DAC","authors":"Yujin Park, Han Yang, Hyunjong Kim, Jun Soo Cho, Suhwan Kim","doi":"10.1109/SOCC.2015.7406951","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406951","url":null,"abstract":"This paper presents a low noise output stage of oversampling audio digital-to-analog converter (DAC). The proposed glitchless switched capacitor DAC (GSC-DAC) eliminates the penalty of a constrained signal range and a signal distortion caused by return-to-zero signals in SC-DAC that is an essential part in order to convert the digital signal into the analog signal. By using a track and hold circuit and deglitching method in GSC-DAC, the low noise is efficiently achieved. The results of post layout simulation show the noise performance improvements of 21dB on average of SNR, SNDR, SFDR and THD in comparison with the absence of the proposed techniques.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131835374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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