Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406991
Ting Kang, Zhaowen Yan, Wei Zhang, Jianwei Wang
This paper focused on the crosstalk analysis of through silicon via (TSV) for 3D integration. It started with the TSV electrical character. A GS TSV pair was established in HFSS and its electrical model was created in ADS. The S-parameter showed a good match between the two methods which validated the electrical model. Crosstalk analysis was an important part in this paper. First, the S-parameter of GSSG-BUMP-RDL model was simulated from 0.1GHz to 20GHz in HFSS, and the NEXT and FEXT crosstalk at 1GHz and 10GHz were given respectively in time domain. Then we added more ground TSV to the model to suppress the crosstalk. And it showed a better capacity to suppress the FEXT crosstalk. Finally, another improved model which used a ground plane to replace the ground RDL was carried out, and it resulted in a better performance to decrease the NEXT crosstalk.
{"title":"Research on crosstalk issue of through silicon via for 3D integration","authors":"Ting Kang, Zhaowen Yan, Wei Zhang, Jianwei Wang","doi":"10.1109/SOCC.2015.7406991","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406991","url":null,"abstract":"This paper focused on the crosstalk analysis of through silicon via (TSV) for 3D integration. It started with the TSV electrical character. A GS TSV pair was established in HFSS and its electrical model was created in ADS. The S-parameter showed a good match between the two methods which validated the electrical model. Crosstalk analysis was an important part in this paper. First, the S-parameter of GSSG-BUMP-RDL model was simulated from 0.1GHz to 20GHz in HFSS, and the NEXT and FEXT crosstalk at 1GHz and 10GHz were given respectively in time domain. Then we added more ground TSV to the model to suppress the crosstalk. And it showed a better capacity to suppress the FEXT crosstalk. Finally, another improved model which used a ground plane to replace the ground RDL was carried out, and it resulted in a better performance to decrease the NEXT crosstalk.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128143422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406902
Yung-Hui Chung, Cheng-Hsun Tsai, Hsuan-Chin Yeh
A power-efficiency and speed-enhancing technique for binary-search ADCs is presented. Asynchronous timing and reduced-count binary-search architecture is implemented to achieve a high-speed operation. The distributed track-and-hold circuit is applied to relax the ENOB degradation caused by the comparator kickback noise and dynamic offset. A prototype 5-b 1-GS/s ADC was simulated in a 90nm CMOS technology. It consumes 2.7 mW from a 1.2 V supply. The ADC core occupies an active area of 0.012 mm2. With the post-layout simulation results, the SNDR and SFDR are 30 dB and 40 dB respectively. The equivalent ENOB is 4.55 b at the Nyquist-rate input. Its FoM is 115 fJ/conversion-step.
{"title":"A 5-b 1-GS/s 2.7-mW binary-search ADC in 90nm digital CMOS","authors":"Yung-Hui Chung, Cheng-Hsun Tsai, Hsuan-Chin Yeh","doi":"10.1109/SOCC.2015.7406902","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406902","url":null,"abstract":"A power-efficiency and speed-enhancing technique for binary-search ADCs is presented. Asynchronous timing and reduced-count binary-search architecture is implemented to achieve a high-speed operation. The distributed track-and-hold circuit is applied to relax the ENOB degradation caused by the comparator kickback noise and dynamic offset. A prototype 5-b 1-GS/s ADC was simulated in a 90nm CMOS technology. It consumes 2.7 mW from a 1.2 V supply. The ADC core occupies an active area of 0.012 mm2. With the post-layout simulation results, the SNDR and SFDR are 30 dB and 40 dB respectively. The equivalent ENOB is 4.55 b at the Nyquist-rate input. Its FoM is 115 fJ/conversion-step.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114563025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406882
W. Rhee
A phase-locked loop is a key building block in wireline and wireless systems. In the wireline systems, low-jitter clock generation and versatile clock-and-data recovery circuits are critical in high data rate I/O links. In the wireless systems, the DS PLL based synthesizer plays a critical role in modern transceivers not only as a local oscillator but also as a phase modulator with direct digital modulation. However, the traditional PLL in advanced CMOS technology suffers from poor scalability, loop parameter variability and leakage current problems. Accordingly, diversified PLL architectures and circuit techniques have been recently proposed in consideration of performance, power and cost, thus making it more difficult for circuit designers to choose the right design solution than ever. This tutorial gives some insight into PLL basics tailored for circuit designers. Then, system perspectives and practical circuit design aspects will be presented. Furthermore, various PLL architectures and design challenges will be discussed.
{"title":"Session T1A: Tutorial: Phase-locked clock generation for SoC: Circuit and system design aspects","authors":"W. Rhee","doi":"10.1109/SOCC.2015.7406882","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406882","url":null,"abstract":"A phase-locked loop is a key building block in wireline and wireless systems. In the wireline systems, low-jitter clock generation and versatile clock-and-data recovery circuits are critical in high data rate I/O links. In the wireless systems, the DS PLL based synthesizer plays a critical role in modern transceivers not only as a local oscillator but also as a phase modulator with direct digital modulation. However, the traditional PLL in advanced CMOS technology suffers from poor scalability, loop parameter variability and leakage current problems. Accordingly, diversified PLL architectures and circuit techniques have been recently proposed in consideration of performance, power and cost, thus making it more difficult for circuit designers to choose the right design solution than ever. This tutorial gives some insight into PLL basics tailored for circuit designers. Then, system perspectives and practical circuit design aspects will be presented. Furthermore, various PLL architectures and design challenges will be discussed.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121344456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406938
Alexander Fell, S. Nandy, R. Narayan
The topology and channel width in Network-on-Chips (NoC) impacts the throughput and latency and therefore the area of deployment. In this paper an NoC based on a three dimensional, toroidal rectangular honeycomb topology using a two tupled (x, y) address, is discussed. It employs a minimal and deterministic routing algorithm utilizing Virtual Channels (VC) to be deadlock free. The performance of this topology is analyzed by integrating the NoC into a multi-core Coarse Grained Reconfigurable Architecture (CGRA) called REDEFINE [1], [2] executing real-life applications such as CRC, AES and ECP. Further the area and power consumptions of NoC routers integrated in honeycomb, mesh and hexagonal/triangular topologies are compared. The results show that a honeycomb topology with its lowest degree, does not always perform worst when compared to the other topologies as suggested by synthetic traffic generators. This can lead to an efficient System-on-Chip (SoC) design in which area and power is reduced by approximately 11% and 7% respectively when compared to an NoC with a mesh topology.
{"title":"A deterministic, minimal routing algorithm for a toroidal, rectangular honeycomb topology using a 2-tupled relative address","authors":"Alexander Fell, S. Nandy, R. Narayan","doi":"10.1109/SOCC.2015.7406938","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406938","url":null,"abstract":"The topology and channel width in Network-on-Chips (NoC) impacts the throughput and latency and therefore the area of deployment. In this paper an NoC based on a three dimensional, toroidal rectangular honeycomb topology using a two tupled (x, y) address, is discussed. It employs a minimal and deterministic routing algorithm utilizing Virtual Channels (VC) to be deadlock free. The performance of this topology is analyzed by integrating the NoC into a multi-core Coarse Grained Reconfigurable Architecture (CGRA) called REDEFINE [1], [2] executing real-life applications such as CRC, AES and ECP. Further the area and power consumptions of NoC routers integrated in honeycomb, mesh and hexagonal/triangular topologies are compared. The results show that a honeycomb topology with its lowest degree, does not always perform worst when compared to the other topologies as suggested by synthetic traffic generators. This can lead to an efficient System-on-Chip (SoC) design in which area and power is reduced by approximately 11% and 7% respectively when compared to an NoC with a mesh topology.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126330044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406934
Taehoon Kim, Sunkwon Kim, J. Woo, Hyongmin Lee, Suhwan Kim
A 9-bit 110-MS/s pipelined-SAR ADC is proposed. To alleviate the design tradeoff between conversion rate and power consumption, the design adopts a voltage-mode open-loop amplifier and a time-interleaved SAR architecture with comparator sharing. The ADC simulated in a 65-nm CMOS technology achieves an ENOB of 8.63 bits near the Nyquist input frequency at the sampling rate of 110MS/s. The power consumption is 7.9mW, resulting in 181.3fJ/conversion-step of Figure of Merit (FoM).
{"title":"A 9-bit, 110-MS/s pipelined-SAR ADC using time-interleaved technique with shared comparator","authors":"Taehoon Kim, Sunkwon Kim, J. Woo, Hyongmin Lee, Suhwan Kim","doi":"10.1109/SOCC.2015.7406934","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406934","url":null,"abstract":"A 9-bit 110-MS/s pipelined-SAR ADC is proposed. To alleviate the design tradeoff between conversion rate and power consumption, the design adopts a voltage-mode open-loop amplifier and a time-interleaved SAR architecture with comparator sharing. The ADC simulated in a 65-nm CMOS technology achieves an ENOB of 8.63 bits near the Nyquist input frequency at the sampling rate of 110MS/s. The power consumption is 7.9mW, resulting in 181.3fJ/conversion-step of Figure of Merit (FoM).","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125780035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406917
To-Po Wang, Shih-Hua Chiang
An integrated differential CMOS low-noise amplifier (LNA) with high gain, low dc power consumption, and low noise figure is presented in this paper. By introducing a current-reused negative-conductance accommodation structure to a differential LNA, the transconductance of the LNA can be effectively increased, leading to a performance enhanced differential LNA. To characterize the performance improvement of the differential LNA, two differential LNAs with and without the 33.3% current-reused negative-conductance accommodation structure were designed and fabricated for comparison. At supply voltages of 0.65-V VDD1 and 1.2-V VDD2, the measured gain of the differential LNA can be significantly improved from 13.1 dB to 15.8 dB, leading to a remarkable 2.7-dB gain increment. The measured dc power dissipation of the presented differential LNA with negative-conductance accommodation structure is 11.48 mW. In addition, the measured noise figure of the differential LNA with a current-reused negative-conductance accommodation structure is 3.3 dB. Compared to previously published 0.18-μm CMOS LNAs at the same frequency of interest, the proposed differential LNA with the current-reused negative-conductance accommodation structure achieves the high gain, low dc power dissipation, and low noise figure.
提出了一种具有高增益、低直流功耗和低噪声因数的集成差分CMOS低噪声放大器。通过在差分LNA中引入电流重复使用的负电导调节结构，可以有效地增加LNA的跨电导，从而提高差分LNA的性能。为了表征差分LNA的性能改进，设计并制造了两种具有和不具有33.3%电流重复使用负电导调节结构的差分LNA进行比较。在电源电压为0.65 v VDD1和1.2 v VDD2时，差分LNA的测量增益可以从13.1 dB显著提高到15.8 dB，增益增加2.7 dB。采用负电导调节结构的差分LNA的直流功耗为11.48 mW。此外，具有电流重复使用负电导调节结构的差分LNA的实测噪声系数为3.3 dB。与先前发表的相同频率的0.18 μm CMOS LNA相比，该差分LNA采用电流复用负电导调节结构，实现了高增益、低直流功耗和低噪声。
{"title":"A high-gain low-power low-noise-figure differential CMOS LNA with 33% current-reused negative-conductance accommodation structure","authors":"To-Po Wang, Shih-Hua Chiang","doi":"10.1109/SOCC.2015.7406917","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406917","url":null,"abstract":"An integrated differential CMOS low-noise amplifier (LNA) with high gain, low dc power consumption, and low noise figure is presented in this paper. By introducing a current-reused negative-conductance accommodation structure to a differential LNA, the transconductance of the LNA can be effectively increased, leading to a performance enhanced differential LNA. To characterize the performance improvement of the differential LNA, two differential LNAs with and without the 33.3% current-reused negative-conductance accommodation structure were designed and fabricated for comparison. At supply voltages of 0.65-V VDD1 and 1.2-V VDD2, the measured gain of the differential LNA can be significantly improved from 13.1 dB to 15.8 dB, leading to a remarkable 2.7-dB gain increment. The measured dc power dissipation of the presented differential LNA with negative-conductance accommodation structure is 11.48 mW. In addition, the measured noise figure of the differential LNA with a current-reused negative-conductance accommodation structure is 3.3 dB. Compared to previously published 0.18-μm CMOS LNAs at the same frequency of interest, the proposed differential LNA with the current-reused negative-conductance accommodation structure achieves the high gain, low dc power dissipation, and low noise figure.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126007867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Carbon nanotube field effect transistors (CNFETs), which use carbon nanotubes (CNTs) as the transistor channel, are promising substitution of conventional CMOS technology. However, due to the stochastic assembly process of CNTs, the number of CNTs in each CNFET has a large variation, resulting in a vast circuit delay variation and timing yield degradation. To overcome it, we propose a timing-driven placement method for CNFET circuits. It exploits a unique feature of CNFET circuits, namely, asymmetric spatial correlation: CNFETs that lie along the CNT growth direction are highly correlated in terms of their electrical properties. Our method distributes CNFETs of the same critical paths to different rows perpendicular to the CNT growth direction during both global and detailed placement phases, while optimizing the timing of these critical paths. Experimental results demonstrated that our approach reduces both the mean and the variance of circuit delay, leading to an improvement in timing yield.
{"title":"Timing-driven placement for carbon nanotube circuits","authors":"Chen Wang, Li Jiang, Shiyan Hu, Tianjian Li, Xiaoyao Liang, Naifeng Jing, Weikang Qian","doi":"10.1109/SOCC.2015.7406983","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406983","url":null,"abstract":"Carbon nanotube field effect transistors (CNFETs), which use carbon nanotubes (CNTs) as the transistor channel, are promising substitution of conventional CMOS technology. However, due to the stochastic assembly process of CNTs, the number of CNTs in each CNFET has a large variation, resulting in a vast circuit delay variation and timing yield degradation. To overcome it, we propose a timing-driven placement method for CNFET circuits. It exploits a unique feature of CNFET circuits, namely, asymmetric spatial correlation: CNFETs that lie along the CNT growth direction are highly correlated in terms of their electrical properties. Our method distributes CNFETs of the same critical paths to different rows perpendicular to the CNT growth direction during both global and detailed placement phases, while optimizing the timing of these critical paths. Experimental results demonstrated that our approach reduces both the mean and the variance of circuit delay, leading to an improvement in timing yield.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127373695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406978
Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, V. Hu, P. Su, C. Chuang
In this paper, we investigate the hybrid TFET-FinFET latch circuits and compare the clock-to-Q delay, dynamic energy, leakage power and energy-delay product (EDP) with all FinFET and all TFET implementations in near-threshold region. We use atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. Four types of latch circuits are evaluated, including standard clocked CMOS latch (SCCL), low-voltage C2MOS latch (LVCL), master-slave transmission-gate latch pair (MTLP) and pulse-triggered latch (PTL). In the hybrid design, TFETs are used for critical path to reduce the clock-to-Q delay, and FinFETs are used for the rest of the circuits to reduce the power consumption. The hybrid latch circuits are shown to offer comparable or better clock-to-Q delays while exhibiting superior EDP compared with all TFET implementations. Among the four types of latch circuits, the hybrid TFET-FinFET LVCL exhibits the most significant clock-to-Q delay and EDP improvements at low operating voltage (<; 0.30V). With work function variation (WFV) and fin line-edge roughness (LER), the hybrid LVCL exhibits superior and comparable EDP variability compared with all FinFET and all TFET implementations at 0.25V.
{"title":"Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications","authors":"Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, V. Hu, P. Su, C. Chuang","doi":"10.1109/SOCC.2015.7406978","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406978","url":null,"abstract":"In this paper, we investigate the hybrid TFET-FinFET latch circuits and compare the clock-to-Q delay, dynamic energy, leakage power and energy-delay product (EDP) with all FinFET and all TFET implementations in near-threshold region. We use atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. Four types of latch circuits are evaluated, including standard clocked CMOS latch (SCCL), low-voltage C2MOS latch (LVCL), master-slave transmission-gate latch pair (MTLP) and pulse-triggered latch (PTL). In the hybrid design, TFETs are used for critical path to reduce the clock-to-Q delay, and FinFETs are used for the rest of the circuits to reduce the power consumption. The hybrid latch circuits are shown to offer comparable or better clock-to-Q delays while exhibiting superior EDP compared with all TFET implementations. Among the four types of latch circuits, the hybrid TFET-FinFET LVCL exhibits the most significant clock-to-Q delay and EDP improvements at low operating voltage (<; 0.30V). With work function variation (WFV) and fin line-edge roughness (LER), the hybrid LVCL exhibits superior and comparable EDP variability compared with all FinFET and all TFET implementations at 0.25V.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130890143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406899
X. Iturbe, D. Keymeulen, Emre Ozer, P. Yiu, D. Berisford, K. Hand, R. Carlson
SoC technology permits to integrate all the computational power required by next-generation space exploration flight science instruments on a single chip. This paper describes the Xilinx Zynq-based Advanced Processor for space EXploration SoC (APEX-SoC) that has been developed at the Jet Propulsion Laboratory (JPL) in collaboration with ARM. The paper discusses the APEX-SoC architecture and demonstrates its main capabilities when used to control JPL's Compositional InfraRed Imaging Spectrometer (CIRIS). As the CIRIS instrument is intended to explore harsh space environments, the paper also deals with the Radiation Hardened By Design (RHBD) features that have been implemented in the APEX-SoC.
{"title":"Designing a SoC to control the next-generation space exploration flight science instruments","authors":"X. Iturbe, D. Keymeulen, Emre Ozer, P. Yiu, D. Berisford, K. Hand, R. Carlson","doi":"10.1109/SOCC.2015.7406899","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406899","url":null,"abstract":"SoC technology permits to integrate all the computational power required by next-generation space exploration flight science instruments on a single chip. This paper describes the Xilinx Zynq-based Advanced Processor for space EXploration SoC (APEX-SoC) that has been developed at the Jet Propulsion Laboratory (JPL) in collaboration with ARM. The paper discusses the APEX-SoC architecture and demonstrates its main capabilities when used to control JPL's Compositional InfraRed Imaging Spectrometer (CIRIS). As the CIRIS instrument is intended to explore harsh space environments, the paper also deals with the Radiation Hardened By Design (RHBD) features that have been implemented in the APEX-SoC.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131898623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406986
A. Ammar, R. Guindi, Ethan Shih, Carlos Tokunaga, J. Tschanz, M. Khellah
Power supply noise has become a major challenge for proper operation of circuits with continuous scaling of CMOS technology along with supply voltage scaling. Conventional passive decoupling capacitors exhibit significant die area penalty resulting in a limited regulation effect. This paper presents a fully integrated charge-sharing-based active decap scheme for power supply noise suppression. The proposed idea is based on allocating a portion of the available passive decap to be used as an active decap that is charged up to a higher voltage and shares its boosted charge with the noisy rail upon droop detection. The proposed scheme uses a charge pump for providing the higher voltage node, as well as a detector circuit for droop detection. The system is implemented in 32 nm CMOS process, and achieves up to ~47% worst-case droop reduction with reduced ringing and settling time, at minimal area and power penalties.
{"title":"A fully integrated charge sharing active decap scheme for power supply noise suppression","authors":"A. Ammar, R. Guindi, Ethan Shih, Carlos Tokunaga, J. Tschanz, M. Khellah","doi":"10.1109/SOCC.2015.7406986","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406986","url":null,"abstract":"Power supply noise has become a major challenge for proper operation of circuits with continuous scaling of CMOS technology along with supply voltage scaling. Conventional passive decoupling capacitors exhibit significant die area penalty resulting in a limited regulation effect. This paper presents a fully integrated charge-sharing-based active decap scheme for power supply noise suppression. The proposed idea is based on allocating a portion of the available passive decap to be used as an active decap that is charged up to a higher voltage and shares its boosted charge with the noisy rail upon droop detection. The proposed scheme uses a charge pump for providing the higher voltage node, as well as a detector circuit for droop detection. The system is implemented in 32 nm CMOS process, and achieves up to ~47% worst-case droop reduction with reduced ringing and settling time, at minimal area and power penalties.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133497576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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