Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406947
S. Rethinagiri, Oscar Palomar, J. Moreno, A. Cristal, O. Unsal
This paper proposes a novel fast and accurate architectural-level tool to estimate power and energy (FAcET) for heterogeneous (CPU-GPU) system architecture based platforms. FAcET consists of two components. The first is a set of generic parametrizable power models generated by characterizing the functional-level activities for different blocks of the chosen platforms. The second is a simulation-based architectural-level prototype that uses SystemC (JIT) simulators to accurately evaluate the parameters of the corresponding power models of the first component. The combination of the two components leads to a novel power and energy estimation methodology at the architectural level that provides a better balance between speed and accuracy. The efficacy of the FAcET tool is verified against measurements taken on real board platforms, which consist of low-power ARM quad-core processors (Cortex-A7, -A9 and -A15), NVIDIA GPUs (Quadro 1000M, Quadro FX5600, Tegra K1, and GTX480) and heterogeneous platforms (NVIDIA Tegra3 and NVIDIA Jetson TK1). Power and energy estimation results obtained with FAcET deviate in less than 3.6% for quad-core processors, 6.5% for GPU, 10% for heterogeneous multiprocessor based systems from the measurements and estimation is 15x faster than state-of-the-art tools.
{"title":"FAcET: Fast and accurate power/energy estimation tool for CPU-GPU platforms at architectural-level","authors":"S. Rethinagiri, Oscar Palomar, J. Moreno, A. Cristal, O. Unsal","doi":"10.1109/SOCC.2015.7406947","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406947","url":null,"abstract":"This paper proposes a novel fast and accurate architectural-level tool to estimate power and energy (FAcET) for heterogeneous (CPU-GPU) system architecture based platforms. FAcET consists of two components. The first is a set of generic parametrizable power models generated by characterizing the functional-level activities for different blocks of the chosen platforms. The second is a simulation-based architectural-level prototype that uses SystemC (JIT) simulators to accurately evaluate the parameters of the corresponding power models of the first component. The combination of the two components leads to a novel power and energy estimation methodology at the architectural level that provides a better balance between speed and accuracy. The efficacy of the FAcET tool is verified against measurements taken on real board platforms, which consist of low-power ARM quad-core processors (Cortex-A7, -A9 and -A15), NVIDIA GPUs (Quadro 1000M, Quadro FX5600, Tegra K1, and GTX480) and heterogeneous platforms (NVIDIA Tegra3 and NVIDIA Jetson TK1). Power and energy estimation results obtained with FAcET deviate in less than 3.6% for quad-core processors, 6.5% for GPU, 10% for heterogeneous multiprocessor based systems from the measurements and estimation is 15x faster than state-of-the-art tools.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128379507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406946
U. Gupta, Sankalp Jain, Ümit Y. Ogras
Mechanically flexible and conformal shaped electronics is gaining momentum in today's electronics ecosystem. Rapid progress at device and circuit levels are already underway, but researchers are yet to envision the system design in a flexible form. This paper introduces hybrid flexible systems, and coins the term System-on-Polymer (SoP) to combine the advantages of flexible electronics and traditional silicon technology. First, we formally define flexibility as a new design metric in addition to existing power, performance, and area metrics. Then, we present a novel optimization approach to place rigid components on to a flexible substrate while minimizing the loss in flexibility. We show that intuitive placement leads to as much as 5.7x loss in flexibility compared to the optimal placement. Finally, we discuss major challenges in the architecture and design of SoPs.
{"title":"Can systems extend to polymer? SoP architecture design and challenges","authors":"U. Gupta, Sankalp Jain, Ümit Y. Ogras","doi":"10.1109/SOCC.2015.7406946","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406946","url":null,"abstract":"Mechanically flexible and conformal shaped electronics is gaining momentum in today's electronics ecosystem. Rapid progress at device and circuit levels are already underway, but researchers are yet to envision the system design in a flexible form. This paper introduces hybrid flexible systems, and coins the term System-on-Polymer (SoP) to combine the advantages of flexible electronics and traditional silicon technology. First, we formally define flexibility as a new design metric in addition to existing power, performance, and area metrics. Then, we present a novel optimization approach to place rigid components on to a flexible substrate while minimizing the loss in flexibility. We show that intuitive placement leads to as much as 5.7x loss in flexibility compared to the optimal placement. Finally, we discuss major challenges in the architecture and design of SoPs.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130496360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406912
Kratika Garg, Y. Aung, S. Lam, T. Srikanthan
FPGAs with integrated hard processors delivering a combination of performance, power savings and flexibility are becoming leading products in the market. Use of this platform calls for efficient hardware-software partitioning, which is crucial to the overall performance and reliability of these platforms. In this paper, we present a run-time efficient hardware-software partitioning technique for FPGAs called `KnapSim'. It employs two well-known heuristics - 0-1 Knapsack and Simulated Annealing algorithms, and provides near-optimal solutions. Experimental results show that performance of the proposed method is significantly better than Simulated Annealing in terms of quality of results and run-time.
{"title":"KnapSim - Run-time efficient hardware-software partitioning technique for FPGAs","authors":"Kratika Garg, Y. Aung, S. Lam, T. Srikanthan","doi":"10.1109/SOCC.2015.7406912","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406912","url":null,"abstract":"FPGAs with integrated hard processors delivering a combination of performance, power savings and flexibility are becoming leading products in the market. Use of this platform calls for efficient hardware-software partitioning, which is crucial to the overall performance and reliability of these platforms. In this paper, we present a run-time efficient hardware-software partitioning technique for FPGAs called `KnapSim'. It employs two well-known heuristics - 0-1 Knapsack and Simulated Annealing algorithms, and provides near-optimal solutions. Experimental results show that performance of the proposed method is significantly better than Simulated Annealing in terms of quality of results and run-time.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"292 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116306974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406905
László Szilágyi, R. Henker, F. Ellinger
This paper presents the design, electrical and optical measurements of a receiver for optical communications in 28 nm CMOS. Electrical measurements show an error-free transmission with a bit error rate (BER) of 10-12 up to 20 Gbps. Inductor-less peaking methods are used, thus the circuit is very compact. With only 0.0025 mm2, 13.6 mW power consumption, yielding 0.68 pJ/bit it is one of the smallest and most energy efficient receiver to this date for 20 Gbps data rate (DR). The receiver was bonded to a printed circuit board (PCB) and to a 14 Gbps, 850 nm photo diode. An error-free transmission over the optical link was obtained up to 17 Gbps with an input optical sensitivity of -4.3 dBm. The measured sensitivity at 15 Gbps is just -7.5 dBm and -8.4 dBm for 10 Gbps.
{"title":"A 0.68 pJ/bit inductor-less optical receiver for 20 Gbps with 0.0025 mm2 area in 28 nm CMOS","authors":"László Szilágyi, R. Henker, F. Ellinger","doi":"10.1109/SOCC.2015.7406905","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406905","url":null,"abstract":"This paper presents the design, electrical and optical measurements of a receiver for optical communications in 28 nm CMOS. Electrical measurements show an error-free transmission with a bit error rate (BER) of 10-12 up to 20 Gbps. Inductor-less peaking methods are used, thus the circuit is very compact. With only 0.0025 mm2, 13.6 mW power consumption, yielding 0.68 pJ/bit it is one of the smallest and most energy efficient receiver to this date for 20 Gbps data rate (DR). The receiver was bonded to a printed circuit board (PCB) and to a 14 Gbps, 850 nm photo diode. An error-free transmission over the optical link was obtained up to 17 Gbps with an input optical sensitivity of -4.3 dBm. The measured sensitivity at 15 Gbps is just -7.5 dBm and -8.4 dBm for 10 Gbps.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128094146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406931
Jie Jin, Lingling Sun, Fengyu Guo, Xiaojun Wang
Recently, network energy consumption and carbon emission statistics show an alarming and growing trend. Such high power requirement can be mainly due to networking hardwares (primarily router processors) designed to operate at maximum capacity with constant and highest energy consumption, independent of the network traffic load. However, recent developments of green network on-chip systems using power proportional technologies suggest the chance to adapt their performance and energy consumption to meet actual workload and operational requirements. In such a scenario, this paper aims at implementing a low power networking processing system by on-chip Dynamic Frequency Scaling (DFS) and Physical Port Switch (PPS), and proposing a control scheme to minimise the number of clock frequency switches that maximises energy saving with negligible Quality of Service(QoS) loss overhead.
{"title":"Low power design for on-chip networking processing system","authors":"Jie Jin, Lingling Sun, Fengyu Guo, Xiaojun Wang","doi":"10.1109/SOCC.2015.7406931","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406931","url":null,"abstract":"Recently, network energy consumption and carbon emission statistics show an alarming and growing trend. Such high power requirement can be mainly due to networking hardwares (primarily router processors) designed to operate at maximum capacity with constant and highest energy consumption, independent of the network traffic load. However, recent developments of green network on-chip systems using power proportional technologies suggest the chance to adapt their performance and energy consumption to meet actual workload and operational requirements. In such a scenario, this paper aims at implementing a low power networking processing system by on-chip Dynamic Frequency Scaling (DFS) and Physical Port Switch (PPS), and proposing a control scheme to minimise the number of clock frequency switches that maximises energy saving with negligible Quality of Service(QoS) loss overhead.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129610775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406883
Yu Huang, J. Rajski
This tutorial covers fundamental concepts, recent developments and industry practices on SoC hierarchical and modular test flow. It has two sections: 1. Core-level test technologies: In this section, we will cover three important topics in core-level DFT and ATPG. a. Test quality. We will introduce cell-aware ATPG. Industrial case studies will be used to illustrate this new fault model's contributions to test quality. b. Test compressions. We will first review the basics of the test compression technologies, which include test stimuli compression and test responses compaction. In the test stimuli compression, we will focus on continuous-flowbased technology, such as Embedded Deterministic Test (EDT). For the test responses compaction, we will briefly introduce space compaction, time compaction and hybrid compaction. Low power compression technologies will also be reviewed. c. Test point insertion. In the good old days, test point was used to improve the test coverage. However, the new trend in test industry is to use the new test point insertion technologies to reduce the pattern count. 2. SoC-level test technologies: In this section, we will cover the following important topics in SoClevel Testing a. This section starts with a review on published core-based SoC hierarchical DFT methodologies and techniques such as TAM, wrapper, test scheduling, and diagnosis etc. b. Illustrate SoC modular test flow and technologies such as broadcasting compressed test stimuli to multiple identical and non-identical cores, channel scaling, and flexible test accessible channels to optimize SoC pin utilization and reduce total SoC test time. c. Pattern retargeting based hierarchical SoC test and diagnosis flow. Dynamic bandwidth management will be explained. It can take advantage of pattern retargeting flow and achieve higher SoC test time reduction. IEEE 1687 (IJTAG) applications in the SoC test flow. This new IEEE standard makes cores to be tested at SoC in a plug-and-play manner.
{"title":"Session T1B: Tutorial: SoC testing","authors":"Yu Huang, J. Rajski","doi":"10.1109/SOCC.2015.7406883","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406883","url":null,"abstract":"This tutorial covers fundamental concepts, recent developments and industry practices on SoC hierarchical and modular test flow. It has two sections: 1. Core-level test technologies: In this section, we will cover three important topics in core-level DFT and ATPG. a. Test quality. We will introduce cell-aware ATPG. Industrial case studies will be used to illustrate this new fault model's contributions to test quality. b. Test compressions. We will first review the basics of the test compression technologies, which include test stimuli compression and test responses compaction. In the test stimuli compression, we will focus on continuous-flowbased technology, such as Embedded Deterministic Test (EDT). For the test responses compaction, we will briefly introduce space compaction, time compaction and hybrid compaction. Low power compression technologies will also be reviewed. c. Test point insertion. In the good old days, test point was used to improve the test coverage. However, the new trend in test industry is to use the new test point insertion technologies to reduce the pattern count. 2. SoC-level test technologies: In this section, we will cover the following important topics in SoClevel Testing a. This section starts with a review on published core-based SoC hierarchical DFT methodologies and techniques such as TAM, wrapper, test scheduling, and diagnosis etc. b. Illustrate SoC modular test flow and technologies such as broadcasting compressed test stimuli to multiple identical and non-identical cores, channel scaling, and flexible test accessible channels to optimize SoC pin utilization and reduce total SoC test time. c. Pattern retargeting based hierarchical SoC test and diagnosis flow. Dynamic bandwidth management will be explained. It can take advantage of pattern retargeting flow and achieve higher SoC test time reduction. IEEE 1687 (IJTAG) applications in the SoC test flow. This new IEEE standard makes cores to be tested at SoC in a plug-and-play manner.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127604913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406977
N. Vamsi, P. Kaddi, A. Dutta, S. Singh
A high Q matching network is being proposed for an RF energy scavenging system that is highly efficient and ultra low power sensitive. The applications of the presented technique are passive next generation wearable devices for remote health care monitoring systems and wireless sensor nodes with usual input power ranging from 1μm to 100μW from 4W EIRP source. The rectifier can rectify an equivalent input voltages as low as 10mV from antenna and is ultra low power sensitive with 1μW(-30 dBm) rectifying capability. The proposed RF energy harvesting scheme achieves better rectifier efficiency of 70.1% at -22 dBm input power (30m distance from 4W EIRP source) compared to existing schemes in literature at 953-MHz to drive load resistance 226KΩ,. The proposed high Q matching technique achieves a better drive strength as it is capable to drive higher load. The RF energy harvesting system is implemented in a standard UMC 0.18μm CMOS technology and generates 1 V regulated output voltage. The results are verified using schematic and post layout simulations.
{"title":"A −30 dBm sensitive ultra low power RF energy harvesting front end with an efficiency of 70.1% at −22 dBm","authors":"N. Vamsi, P. Kaddi, A. Dutta, S. Singh","doi":"10.1109/SOCC.2015.7406977","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406977","url":null,"abstract":"A high Q matching network is being proposed for an RF energy scavenging system that is highly efficient and ultra low power sensitive. The applications of the presented technique are passive next generation wearable devices for remote health care monitoring systems and wireless sensor nodes with usual input power ranging from 1μm to 100μW from 4W EIRP source. The rectifier can rectify an equivalent input voltages as low as 10mV from antenna and is ultra low power sensitive with 1μW(-30 dBm) rectifying capability. The proposed RF energy harvesting scheme achieves better rectifier efficiency of 70.1% at -22 dBm input power (30m distance from 4W EIRP source) compared to existing schemes in literature at 953-MHz to drive load resistance 226KΩ,. The proposed high Q matching technique achieves a better drive strength as it is capable to drive higher load. The RF energy harvesting system is implemented in a standard UMC 0.18μm CMOS technology and generates 1 V regulated output voltage. The results are verified using schematic and post layout simulations.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121032213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406979
Shixiong Jiang, P. Yan, R. Sridhar
This paper presents a novel technique to design high performance Content-addressable memories(CAMs), with lower power and latency as compared to other similar structures. The first technique is to pipeline the search operation by distributing single matching operation into several segments for different search-line registers. Speed is improved significantly since four search-line registers are comparing in parallel. Meanwhile, by disabling the subsequent segments, the power consumption is also reduced. The second technique is to improve the speed further by using multi-bank search data registers structure. The experimental results show that up to 37.32% power savings can be obtained and 90.79% time can be shrieked as compared to conventional NOR-type CAM design.
{"title":"A high speed and low power content-addressable memory(CAM) using pipelined scheme","authors":"Shixiong Jiang, P. Yan, R. Sridhar","doi":"10.1109/SOCC.2015.7406979","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406979","url":null,"abstract":"This paper presents a novel technique to design high performance Content-addressable memories(CAMs), with lower power and latency as compared to other similar structures. The first technique is to pipeline the search operation by distributing single matching operation into several segments for different search-line registers. Speed is improved significantly since four search-line registers are comparing in parallel. Meanwhile, by disabling the subsequent segments, the power consumption is also reduced. The second technique is to improve the speed further by using multi-bank search data registers structure. The experimental results show that up to 37.32% power savings can be obtained and 90.79% time can be shrieked as compared to conventional NOR-type CAM design.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115359039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406885
R. Sridhar
Internet of Things (IoT) is considered to be a technological trend that is likely to have a far reaching impact on every one's lives in many distinct ways. IoTs changs the internet from internet for people to internet of things. Enabling of IoT is accomplished through efforts by hardware and network industry and the enormous amount of data generated through IoTs impacts Big Data and data mining fields. With its wide ranging applications in Healthcare, Home automation, Industrial Control and environmental and social domains, IoTs can have wide ranging expectations. Major roadblocks to the deployment and prevalent use of IoTs are power and privacy-security vulnerabilities. IoTs have conflicting requirements and choosing appropriate tradeoffs based on the situation will lead to its increased use. Though varying projections have large investment in IoTs, there is also increased skepticism due to privacy and security concerns. This tutorial will introduce IoTs, specifications, opportunities for SoC designers and their integration into diverse applications. Possible solutions will be discussed in dealing with power and security aspects as well.
{"title":"Session T2B: Tutorial: Internet of Things (IoT) - Opportunities for SoC designers","authors":"R. Sridhar","doi":"10.1109/SOCC.2015.7406885","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406885","url":null,"abstract":"Internet of Things (IoT) is considered to be a technological trend that is likely to have a far reaching impact on every one's lives in many distinct ways. IoTs changs the internet from internet for people to internet of things. Enabling of IoT is accomplished through efforts by hardware and network industry and the enormous amount of data generated through IoTs impacts Big Data and data mining fields. With its wide ranging applications in Healthcare, Home automation, Industrial Control and environmental and social domains, IoTs can have wide ranging expectations. Major roadblocks to the deployment and prevalent use of IoTs are power and privacy-security vulnerabilities. IoTs have conflicting requirements and choosing appropriate tradeoffs based on the situation will lead to its increased use. Though varying projections have large investment in IoTs, there is also increased skepticism due to privacy and security concerns. This tutorial will introduce IoTs, specifications, opportunities for SoC designers and their integration into diverse applications. Possible solutions will be discussed in dealing with power and security aspects as well.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132461606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
PAM-4 signaling is an effective solution for high-speed CMOS serial-link transceivers, but it suffers from the difficulty of signal regeneration in analog front-end owning to its multi-level characteristics. An adaptive analog equalizer with decoupling control loops is proposed to address the nonlinearity of amplifiers. A low-frequency gain invariant equalizer and a golden signal generator are designed to serve boost and swing control loops, respectively. An integrating charge pump is employed to improve the convergence performance of receiver. Transistor-level simulation results show that the proposed adaptive analog equalizer in 40-nm CMOS technology can recover 25 Gb/s random data transmitted over a 29.8 inches Megtron6 printed circuit board (PCB) copper channel.
{"title":"A PAM-4 adaptive analog equalizer with decoupling control loops for 25-Gb/s CMOS serial-link receiver","authors":"Shunbin Li, Peng Liu, Weidong Wang, X. Fang, Dong Wu, Xiang-hui Xie","doi":"10.1109/SOCC.2015.7406950","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406950","url":null,"abstract":"PAM-4 signaling is an effective solution for high-speed CMOS serial-link transceivers, but it suffers from the difficulty of signal regeneration in analog front-end owning to its multi-level characteristics. An adaptive analog equalizer with decoupling control loops is proposed to address the nonlinearity of amplifiers. A low-frequency gain invariant equalizer and a golden signal generator are designed to serve boost and swing control loops, respectively. An integrating charge pump is employed to improve the convergence performance of receiver. Transistor-level simulation results show that the proposed adaptive analog equalizer in 40-nm CMOS technology can recover 25 Gb/s random data transmitted over a 29.8 inches Megtron6 printed circuit board (PCB) copper channel.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126834759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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