Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406996
Liping Li, Wenyi Zhang
Systematic polar codes are proposed by Arikan and are shown to have better BER performance than non-systematic polar codes. From a recursive decomposition of the generator matrix of polar codes, Arikan showed that the encoding complexity of systematic polar codes is also O(N log N) where N is the code block length. But the recursive process involves some additional calculations in transforming the problem instances back and forth. In this paper, by using the sparsity property of the generator matrix, we propose an encoding process which has the same complexity as non-systematic polar codes in the presence of an additional memory array. Without the additional memory elements, the number of additions of the proposed encoding process increases compared with non-systematic polar codes. We also provide an analysis to quantify this additional increase of the complexity.
{"title":"On the encoding complexity of systematic polar codes","authors":"Liping Li, Wenyi Zhang","doi":"10.1109/SOCC.2015.7406996","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406996","url":null,"abstract":"Systematic polar codes are proposed by Arikan and are shown to have better BER performance than non-systematic polar codes. From a recursive decomposition of the generator matrix of polar codes, Arikan showed that the encoding complexity of systematic polar codes is also O(N log N) where N is the code block length. But the recursive process involves some additional calculations in transforming the problem instances back and forth. In this paper, by using the sparsity property of the generator matrix, we propose an encoding process which has the same complexity as non-systematic polar codes in the presence of an additional memory array. Without the additional memory elements, the number of additions of the proposed encoding process increases compared with non-systematic polar codes. We also provide an analysis to quantify this additional increase of the complexity.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134006276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406918
Evan K. Jorgensen, P. R. Mukund
Four multi-GHz LCVCOs were designed in the GlobalFoundries 28 nm HPP CMOS technology: 15 GHz varactor-tuned NMOS-only, 9 GHz varactor-tuned self-biased CMOS, 14.2 GHz digitally-tuned NMOS-only, and 8.2 GHz digitally-tuned self-biased CMOS. As a design method, analytical expressions describing tuning range, tank amplitude constraint, and startup condition were used in MATLAB to output a graphical view of the design space for both NMOS-only and CMOS LCVCOs, with maximum varactor capacitance on the y-axis and NMOS transistor width on the x-axis. Phase noise was predicted as well. In addition to the standard varactor control voltage tuning method, digitally-tuned implementations of both NMOS and CMOS LCVCOs are presented. The performance aspects of all designed LCVCOs are compared. Both varactor-tuned and digitally-tuned NMOS LCVCOs have lower phase noise, lower power consumption, and higher tuning range than both CMOS topologies. The varactor-tuned NMOS LCVCO has the lowest phase noise of -97 dBc/Hz at 1 MHz offset from 15 GHz center frequency, FOM of -172.20 dBc/Hz, and FOMT of -167.76 dBc/Hz. The digitally-tuned CMOS LCVCO has the greatest tuning range at 10%. Phase noise is improved by 3 dBc/Hz with the digitally-tuned CMOS topology over varactor-tuned CMOS.
{"title":"A comparative study of multi-GHz LCVCOs designed in 28nm CMOS technology","authors":"Evan K. Jorgensen, P. R. Mukund","doi":"10.1109/SOCC.2015.7406918","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406918","url":null,"abstract":"Four multi-GHz LCVCOs were designed in the GlobalFoundries 28 nm HPP CMOS technology: 15 GHz varactor-tuned NMOS-only, 9 GHz varactor-tuned self-biased CMOS, 14.2 GHz digitally-tuned NMOS-only, and 8.2 GHz digitally-tuned self-biased CMOS. As a design method, analytical expressions describing tuning range, tank amplitude constraint, and startup condition were used in MATLAB to output a graphical view of the design space for both NMOS-only and CMOS LCVCOs, with maximum varactor capacitance on the y-axis and NMOS transistor width on the x-axis. Phase noise was predicted as well. In addition to the standard varactor control voltage tuning method, digitally-tuned implementations of both NMOS and CMOS LCVCOs are presented. The performance aspects of all designed LCVCOs are compared. Both varactor-tuned and digitally-tuned NMOS LCVCOs have lower phase noise, lower power consumption, and higher tuning range than both CMOS topologies. The varactor-tuned NMOS LCVCO has the lowest phase noise of -97 dBc/Hz at 1 MHz offset from 15 GHz center frequency, FOM of -172.20 dBc/Hz, and FOMT of -167.76 dBc/Hz. The digitally-tuned CMOS LCVCO has the greatest tuning range at 10%. Phase noise is improved by 3 dBc/Hz with the digitally-tuned CMOS topology over varactor-tuned CMOS.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"434 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134349783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406937
Xiang Wang, Lin Li, Longbing Zhang, Weike Wang, Rong Zhang, Yi Zhang, Quanneng Shen
This essay provides a multi-level collaboration low-power design based on embedded processor, builds SoC (System-on-Chip) and designs a low-power SoC by register level, system level and gate level. The designed clock gating module, power management module and system program coordination can be used to realize the sleep and wake up functions on SoC. In order to realize a multi-level collaboration low-power designing, gating clock circuit can be used in circuit designing.
{"title":"A multi-level collaboration low-power design based on embedded system","authors":"Xiang Wang, Lin Li, Longbing Zhang, Weike Wang, Rong Zhang, Yi Zhang, Quanneng Shen","doi":"10.1109/SOCC.2015.7406937","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406937","url":null,"abstract":"This essay provides a multi-level collaboration low-power design based on embedded processor, builds SoC (System-on-Chip) and designs a low-power SoC by register level, system level and gate level. The designed clock gating module, power management module and system program coordination can be used to realize the sleep and wake up functions on SoC. In order to realize a multi-level collaboration low-power designing, gating clock circuit can be used in circuit designing.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115106080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406975
K. G. Perez, Sandra Scott-Hayward, Xin Yang, S. Sezer
Multiple Table Lookup architectures in Software Defined Networking (SDN) open the door for exciting new network applications. The development of the OpenFlow protocol supported the SDN paradigm. However, the first version of the OpenFlow protocol specified a single table lookup model with the associated constraints in flow entry numbers and search capabilities. With the introduction of multiple table lookup in OpenFlow v1.1, flexible and efficient search to support SDN application innovation became possible. However, implementation of multiple table lookup in hardware to meet high performance requirements is non-trivial. One possible approach involves the use of multi-dimensional lookup algorithms. A high lookup performance can be achieved by using embedded memory for flow entry storage. A detailed study of OpenFlow flow filters for multi-dimensional lookup is presented in this paper. Based on a proposed multiple table lookup architecture, the memory consumption and update performance using parallel single field searches are evaluated. The results demonstrate an efficient multi-table lookup implementation with minimum memory usage.
{"title":"Memory cost analysis for OpenFlow multiple table lookup","authors":"K. G. Perez, Sandra Scott-Hayward, Xin Yang, S. Sezer","doi":"10.1109/SOCC.2015.7406975","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406975","url":null,"abstract":"Multiple Table Lookup architectures in Software Defined Networking (SDN) open the door for exciting new network applications. The development of the OpenFlow protocol supported the SDN paradigm. However, the first version of the OpenFlow protocol specified a single table lookup model with the associated constraints in flow entry numbers and search capabilities. With the introduction of multiple table lookup in OpenFlow v1.1, flexible and efficient search to support SDN application innovation became possible. However, implementation of multiple table lookup in hardware to meet high performance requirements is non-trivial. One possible approach involves the use of multi-dimensional lookup algorithms. A high lookup performance can be achieved by using embedded memory for flow entry storage. A detailed study of OpenFlow flow filters for multi-dimensional lookup is presented in this paper. Based on a proposed multiple table lookup architecture, the memory consumption and update performance using parallel single field searches are evaluated. The results demonstrate an efficient multi-table lookup implementation with minimum memory usage.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123783116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406920
Yanqi Zheng, M. Ho, K. Leung, Jianping Guo, Biao Chen
A digital-control sensorless current-mode boost DC-DC converter is presented in this paper. By using the proposed sensorless current-mode control, the requirement for implementation of current sensor for conventional current-mode dc-dc converter is relaxed. Moreover, the converter can seamlessly switch between CCM and DCM operation as in conventional current-mode control. With this method, the non-limited-cycle for digital-control current-mode converter is realized. Lower resolution of DPWM can be used to avoid the appearance of limited cycle, regardless of loading condition.
{"title":"A digital-control sensorless current-mode boost converter with non-zero error bin compensation and seamless mode transition","authors":"Yanqi Zheng, M. Ho, K. Leung, Jianping Guo, Biao Chen","doi":"10.1109/SOCC.2015.7406920","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406920","url":null,"abstract":"A digital-control sensorless current-mode boost DC-DC converter is presented in this paper. By using the proposed sensorless current-mode control, the requirement for implementation of current sensor for conventional current-mode dc-dc converter is relaxed. Moreover, the converter can seamlessly switch between CCM and DCM operation as in conventional current-mode control. With this method, the non-limited-cycle for digital-control current-mode converter is realized. Lower resolution of DPWM can be used to avoid the appearance of limited cycle, regardless of loading condition.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128444815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406933
Xiaofan Zhang, M. Ebrahimi, Letian Huang, Guangjun Li
With aggressive technology scaling in deep submicron era, burgeoning transistors make chips more susceptible to failures. It is inevitable that process variation is gradually becoming a crucial challenge in the IC design. In addition, aging leads to faults, shortening the lifetime of the circuits. Networks-on-chip also come to the problems caused by variations and aging, leading to degraded performance and erroneous behaviors. Faults may occur in numerous locations of the on-chip networks and once they occur in the control path, more severe effects such as deadlock and livelock are expected. In this paper, we present a fine-grained mechanism to tolerate faults in the routing computation units without disabling the faulty routers. By applying this mechanism, routing and packet-receiving services are separated. The faulty routing computation unit is replaced by a light-weight redundant circuit, providing static but reliable routing services. The other components in this router are still functional retaining the on-chip performance. Experimental results indicate that the on-chip network with the proposed mechanism is fault-tolerant when 14% of all routing computation modules are suffering from faults. The area overhead and power consumption of the proposed method is around 7.29% and 6.20% over the baseline approach.
{"title":"Fault-resilient routing unit in NoCs","authors":"Xiaofan Zhang, M. Ebrahimi, Letian Huang, Guangjun Li","doi":"10.1109/SOCC.2015.7406933","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406933","url":null,"abstract":"With aggressive technology scaling in deep submicron era, burgeoning transistors make chips more susceptible to failures. It is inevitable that process variation is gradually becoming a crucial challenge in the IC design. In addition, aging leads to faults, shortening the lifetime of the circuits. Networks-on-chip also come to the problems caused by variations and aging, leading to degraded performance and erroneous behaviors. Faults may occur in numerous locations of the on-chip networks and once they occur in the control path, more severe effects such as deadlock and livelock are expected. In this paper, we present a fine-grained mechanism to tolerate faults in the routing computation units without disabling the faulty routers. By applying this mechanism, routing and packet-receiving services are separated. The faulty routing computation unit is replaced by a light-weight redundant circuit, providing static but reliable routing services. The other components in this router are still functional retaining the on-chip performance. Experimental results indicate that the on-chip network with the proposed mechanism is fault-tolerant when 14% of all routing computation modules are suffering from faults. The area overhead and power consumption of the proposed method is around 7.29% and 6.20% over the baseline approach.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125940965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406925
H. Yamauchi, Worawit Somha, Yuan-Qiang Song
A filter design to improve convergence characteristics in the Lucy-Richardson-deconvolution (LRDec) iterations is proposed, which is required for inversely analyzing log-mixtures 7-segmented Random Telegraph Noise (RTN) distribution effects on VLSI reliability margin. The proposed filter alleviates unwanted phase misalignment between the two distribution curves of feedback gain and deconvoluted RTN. This contributes to reduce its relative deconvolution errors by 1.5-orders of magnitude compared with the conventional LRDec. The accuracy of the fail-bit-count (FBC) prediction is increased by 10-folds while accelerating its convergence speed by 7 times of the conventional one. This contributes not to give up on a benefit of smaller iteration cycles from LRDec.
{"title":"A filter design to increase accuracy of Lucy-Richardson deconvolution for analyzing RTN mixtures effects on VLSI reliability margin","authors":"H. Yamauchi, Worawit Somha, Yuan-Qiang Song","doi":"10.1109/SOCC.2015.7406925","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406925","url":null,"abstract":"A filter design to improve convergence characteristics in the Lucy-Richardson-deconvolution (LRDec) iterations is proposed, which is required for inversely analyzing log-mixtures 7-segmented Random Telegraph Noise (RTN) distribution effects on VLSI reliability margin. The proposed filter alleviates unwanted phase misalignment between the two distribution curves of feedback gain and deconvoluted RTN. This contributes to reduce its relative deconvolution errors by 1.5-orders of magnitude compared with the conventional LRDec. The accuracy of the fail-bit-count (FBC) prediction is increased by 10-folds while accelerating its convergence speed by 7 times of the conventional one. This contributes not to give up on a benefit of smaller iteration cycles from LRDec.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128929957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406973
Ramandeep Kaur, Alexander Fell, Harsh Rawat
Multi-port Static Random Access Memories (SRAM) are essential for shared data structures, especially in distributed, multi-core and multi-processing computing systems. This paper introduces an elementary multi-port memory design which can perform either dual-read or a single-write operation (2R/1W) by efficiently combining the 6 Transistor (6T) single-port SRAM (SP-SRAM). This new architecture offers a solution to the existing 8T dual-port (DP) cell problems including read-write stability issues. The design has been evaluated by comparing with the conventional solutions, in 28nm Ultra Thin Body and Box Fully Depleted Silicon on Insulator (UTBB-FDSOI) technology. A 2048 words, 64 bit memory shows 31% improvement in performance, 31% reduced area and 19% lesser power consumption than the conventional 8T dual-port SRAM (DP-SRAM). In addition, the proposed design is scalable to large memory capacities which cannot be generated directly using the available dual-port memory compilers.
{"title":"A 6T SRAM cell based pipelined 2R/1W memory design using 28nm UTBB-FDSOI","authors":"Ramandeep Kaur, Alexander Fell, Harsh Rawat","doi":"10.1109/SOCC.2015.7406973","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406973","url":null,"abstract":"Multi-port Static Random Access Memories (SRAM) are essential for shared data structures, especially in distributed, multi-core and multi-processing computing systems. This paper introduces an elementary multi-port memory design which can perform either dual-read or a single-write operation (2R/1W) by efficiently combining the 6 Transistor (6T) single-port SRAM (SP-SRAM). This new architecture offers a solution to the existing 8T dual-port (DP) cell problems including read-write stability issues. The design has been evaluated by comparing with the conventional solutions, in 28nm Ultra Thin Body and Box Fully Depleted Silicon on Insulator (UTBB-FDSOI) technology. A 2048 words, 64 bit memory shows 31% improvement in performance, 31% reduced area and 19% lesser power consumption than the conventional 8T dual-port SRAM (DP-SRAM). In addition, the proposed design is scalable to large memory capacities which cannot be generated directly using the available dual-port memory compilers.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125482695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406997
X. Liang, Chuan Zhang, Menghui Xu, Shunqing Zhang, X. You
Representing continuous values by streams of random binary bits, stochastic decoding has shown advantages in both hardware efficiency and fault tolerance, therefore has been widely adopted by iterative decoding of error correction codes such as low-density parity-check (LDPC) codes and so on. Recently, polar codes, the first codes that can provably achieve the capacity of symmetric binary-input discrete memoryless channels (B-DMCs), have drawn a lot of attentions from both academia and industry. Although, polar codes with list successive cancellation (SC) decoding can outperform several best-known LDPC codes even within high error-rate regions, the linearly increasing hardware complexity makes its efficient implementation difficult. To this end, the stochastic list SC polar decoding algorithm is proposed in this paper to provide a good tradeoff between performance and complexity. In order to increase the decoding performance of stochastic list SC polar decoder, doubling probability approach is presented. The corresponding hardware architecture is also given. The approximate doubling approach is employed to facilitate the efficient implementation. Implementation results have shown that the proposed stochastic list SC polar decoder can achieve a good trade-off between performance and complexity.
{"title":"Efficient stochastic list successive cancellation decoder for polar codes","authors":"X. Liang, Chuan Zhang, Menghui Xu, Shunqing Zhang, X. You","doi":"10.1109/SOCC.2015.7406997","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406997","url":null,"abstract":"Representing continuous values by streams of random binary bits, stochastic decoding has shown advantages in both hardware efficiency and fault tolerance, therefore has been widely adopted by iterative decoding of error correction codes such as low-density parity-check (LDPC) codes and so on. Recently, polar codes, the first codes that can provably achieve the capacity of symmetric binary-input discrete memoryless channels (B-DMCs), have drawn a lot of attentions from both academia and industry. Although, polar codes with list successive cancellation (SC) decoding can outperform several best-known LDPC codes even within high error-rate regions, the linearly increasing hardware complexity makes its efficient implementation difficult. To this end, the stochastic list SC polar decoding algorithm is proposed in this paper to provide a good tradeoff between performance and complexity. In order to increase the decoding performance of stochastic list SC polar decoder, doubling probability approach is presented. The corresponding hardware architecture is also given. The approximate doubling approach is employed to facilitate the efficient implementation. Implementation results have shown that the proposed stochastic list SC polar decoder can achieve a good trade-off between performance and complexity.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132878047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406974
Anil Kumar Gundu, M. Hashmi, Ramkesh Sharma, Naushad Ansari
In advanced CMOS technologies large-scale integration has enabled larger embedded memory capacity in SoCs and it has also necessitated the Static Random Access Memory (SRAM) bitcell qualification requirement of the order of 0.1ppb. This paper presents a qualitative statistical analysis of a 6T standard SRAM cell in read cycle with respect to Static Noise Margin (SNM) due to process parameter fluctuation. The Yield (Y) of SRAM is predicted for different capacities of SRAM array by modeling success/failure boundary through mathematical modeling for one cell. With this frame work, it is demonstrated that the yield can be accurately predicted by increasing the order of the polynomial. The obtained results show that for the first order approximation, the failure probability of a single cell is 2.36×10-6 whereas the failure probability of an SRAM can be decreased to 8.38×10-13 if the success/failure boundary is modeled with a polynomial of order 4.
{"title":"Statistical analysis and parametric yield estimation of standard 6T SRAM cell for different capacities","authors":"Anil Kumar Gundu, M. Hashmi, Ramkesh Sharma, Naushad Ansari","doi":"10.1109/SOCC.2015.7406974","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406974","url":null,"abstract":"In advanced CMOS technologies large-scale integration has enabled larger embedded memory capacity in SoCs and it has also necessitated the Static Random Access Memory (SRAM) bitcell qualification requirement of the order of 0.1ppb. This paper presents a qualitative statistical analysis of a 6T standard SRAM cell in read cycle with respect to Static Noise Margin (SNM) due to process parameter fluctuation. The Yield (Y) of SRAM is predicted for different capacities of SRAM array by modeling success/failure boundary through mathematical modeling for one cell. With this frame work, it is demonstrated that the yield can be accurately predicted by increasing the order of the polynomial. The obtained results show that for the first order approximation, the failure probability of a single cell is 2.36×10-6 whereas the failure probability of an SRAM can be decreased to 8.38×10-13 if the success/failure boundary is modeled with a polynomial of order 4.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125059648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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