Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406930
Abdullah M. Zyarah, D. Kudithipudi
Self-learning hardware systems, with high-degree of plasticity, are critical in performing spatio-temporal tasks in next-generation computing systems. To this end, hierarchical temporal memory (HTM) offers time-based online-learning algorithms that store and recall temporal and spatial patterns. One of the key building blocks in HTM is the spatial pooler. In this paper, we propose a reconfigurable and scalable spatial pooler architecture that is ported onto a Xilinx Virtex-IV FPGA fabric. The concept of synthetic synapses is proposed for dynamic interconnections. The spatial pooler architecture is verified for two different datasets, MNIST and EU numberplate font, with ≈ 91% and ≈ 90% accuracy respectively. Moreover, the proposed hardware model offers speed up of 4817X over the software realization. These results indicate that the proposed architecture can serve as a core to build the HTM in hardware and eventually as a standalone self-learning hardware system.
{"title":"Reconfigurable hardware architecture of the spatial pooler for hierarchical temporal memory","authors":"Abdullah M. Zyarah, D. Kudithipudi","doi":"10.1109/SOCC.2015.7406930","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406930","url":null,"abstract":"Self-learning hardware systems, with high-degree of plasticity, are critical in performing spatio-temporal tasks in next-generation computing systems. To this end, hierarchical temporal memory (HTM) offers time-based online-learning algorithms that store and recall temporal and spatial patterns. One of the key building blocks in HTM is the spatial pooler. In this paper, we propose a reconfigurable and scalable spatial pooler architecture that is ported onto a Xilinx Virtex-IV FPGA fabric. The concept of synthetic synapses is proposed for dynamic interconnections. The spatial pooler architecture is verified for two different datasets, MNIST and EU numberplate font, with ≈ 91% and ≈ 90% accuracy respectively. Moreover, the proposed hardware model offers speed up of 4817X over the software realization. These results indicate that the proposed architecture can serve as a core to build the HTM in hardware and eventually as a standalone self-learning hardware system.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122110379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406898
Koki Igawa, Youhua Shi, M. Yanagisawa, N. Togawa
In order to tackle a process-variation problem, we can define several scenarios, each of which corresponds to a particular LSI behavior, such as a typical-case scenario and a worst-case scenario. By designing a single LSI chip which realizes multiple scenarios simultaneously, we can have a process-variation-tolerant LSI chip. In this paper, we propose a process-variation-aware low-latency and multi-scenario high-level synthesis algorithm targeting new distributed-register architectures, called HDR architectures. We assume two scenarios, a typical-case scenario and a worst-case scenario, and realize them onto a single chip. We first schedule/bind each of the scenarios independently. After that, we commonize the scheduling/binding results for the typical-case and worst-case scenarios and thus generate a commonized area-minimized floorplan result. Experimental results show that our algorithm reduces the latency of the typical-case scenario by up to 50% without increasing the latency of the worst-case scenario, compared with several existing methods.
{"title":"A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures","authors":"Koki Igawa, Youhua Shi, M. Yanagisawa, N. Togawa","doi":"10.1109/SOCC.2015.7406898","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406898","url":null,"abstract":"In order to tackle a process-variation problem, we can define several scenarios, each of which corresponds to a particular LSI behavior, such as a typical-case scenario and a worst-case scenario. By designing a single LSI chip which realizes multiple scenarios simultaneously, we can have a process-variation-tolerant LSI chip. In this paper, we propose a process-variation-aware low-latency and multi-scenario high-level synthesis algorithm targeting new distributed-register architectures, called HDR architectures. We assume two scenarios, a typical-case scenario and a worst-case scenario, and realize them onto a single chip. We first schedule/bind each of the scenarios independently. After that, we commonize the scheduling/binding results for the typical-case and worst-case scenarios and thus generate a commonized area-minimized floorplan result. Experimental results show that our algorithm reduces the latency of the typical-case scenario by up to 50% without increasing the latency of the worst-case scenario, compared with several existing methods.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130649097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406884
M. Ker
To reduce the weight of electronic products, to integrate more functions into the electronic products, as well as to reduce the power consumption of electronic products, the CMOS technology has been developed into nanometer scale to realize VLSI/SoC for electronic systems. With the transistors in the nano-scale dimension, the gate-oxide thickness of MOSFET is only 10~15Å for operating with sub-1V power supply. Such thinner gate oxide is very easily ruptured by electrostatic discharge (ESD) events, which frequently happen in our environments with the voltage level of hundreds or even thousands volts. The integrated circuits (ICs) are weaker to sustain such ESD stresses during the assembly, testing, package, and the applications. To verify the ESD reliability of IC products for safe applications, there are already some industry ESD test standards developed, such as Human Body Model (HBM) and Charged Device Model (CDM), to verify the ESD robustness of IC products. Besides, in the IEC 61000-4-2 standard, the electronic products are zapped by the ESD gun with ESD voltage of even up to 15kV in the air-discharge mode. How to design the on-chip ESD protection circuits to effectively protect the integrated circuits realized by the nano-scale CMOS devices is a quite difficult challenge to IC industry. The on-chip ESD protection circuit must be included in the beginning phase of chip design. In this Tutorial, a brief introduction on ESD issue and test standards to IC products is presented with some failure analysis pictures from real IC products to demonstrate the impact of ESD on IC products. The basic design concept for on-chip ESD protection circuit will be presented. Some useful ESD protection designs for high-speed I/O and RF circuits will be mentioned. To achieve the whole-chip ESD protection by using the active power-rail ESD clamp circuit will be emphasized. Additional consideration on the active power-rail ESD clamp circuit realized in the nanoscale CMOS processes will be especially addressed. After the component-level ESD protection, the system-level ESD protection design will be brief discussed. ESD protection for CMOS ICs is not only the process issue but also highly dependent to the design issue, which has been an important topic that the IC designers need to know.
{"title":"SESSION T2A: Tutorial: Advanced ESD protection design for CMOS circuits and systems","authors":"M. Ker","doi":"10.1109/SOCC.2015.7406884","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406884","url":null,"abstract":"To reduce the weight of electronic products, to integrate more functions into the electronic products, as well as to reduce the power consumption of electronic products, the CMOS technology has been developed into nanometer scale to realize VLSI/SoC for electronic systems. With the transistors in the nano-scale dimension, the gate-oxide thickness of MOSFET is only 10~15Å for operating with sub-1V power supply. Such thinner gate oxide is very easily ruptured by electrostatic discharge (ESD) events, which frequently happen in our environments with the voltage level of hundreds or even thousands volts. The integrated circuits (ICs) are weaker to sustain such ESD stresses during the assembly, testing, package, and the applications. To verify the ESD reliability of IC products for safe applications, there are already some industry ESD test standards developed, such as Human Body Model (HBM) and Charged Device Model (CDM), to verify the ESD robustness of IC products. Besides, in the IEC 61000-4-2 standard, the electronic products are zapped by the ESD gun with ESD voltage of even up to 15kV in the air-discharge mode. How to design the on-chip ESD protection circuits to effectively protect the integrated circuits realized by the nano-scale CMOS devices is a quite difficult challenge to IC industry. The on-chip ESD protection circuit must be included in the beginning phase of chip design. In this Tutorial, a brief introduction on ESD issue and test standards to IC products is presented with some failure analysis pictures from real IC products to demonstrate the impact of ESD on IC products. The basic design concept for on-chip ESD protection circuit will be presented. Some useful ESD protection designs for high-speed I/O and RF circuits will be mentioned. To achieve the whole-chip ESD protection by using the active power-rail ESD clamp circuit will be emphasized. Additional consideration on the active power-rail ESD clamp circuit realized in the nanoscale CMOS processes will be especially addressed. After the component-level ESD protection, the system-level ESD protection design will be brief discussed. ESD protection for CMOS ICs is not only the process issue but also highly dependent to the design issue, which has been an important topic that the IC designers need to know.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126264275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406897
Bill Ma, Qinjin Huang, Fengqi Yu
This paper presents a novel segmented hybrid digital-to-analog converter (DAC). It uses a resistor-string as the LSB part for low-power consumption, and uses a current-steering array as the MSB part for high-speed and small size. The LSB and MSB parts are combined by a slew-rate-enhanced class AB output amplifier for high speed. Compared to resistor string DACs, current steering DACs, or resistor-capacitor hybrid DACs, the proposed DAC shows a better tradeoff between power and speed at low power application demanding a sampling clock between 1 MHz and 100 MHz. The prototype is a 12-bit DAC implemented in 0.18-μm CMOS technology with the worst measured DNL/INL of 6.38 LSB / 7.55 LSB. The analogue part power consumption is 1.24 mW and the digital part 0.5mW at 1.35-V power supply at 20-MS/s sampling rate. Its output is single-end buffered voltage with a range of 500 mV. The core area is 0.16 mm2.
{"title":"A 12-bit 1.74-mW 20-MS/s DAC with resistor-string and current-steering hybrid architecture","authors":"Bill Ma, Qinjin Huang, Fengqi Yu","doi":"10.1109/SOCC.2015.7406897","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406897","url":null,"abstract":"This paper presents a novel segmented hybrid digital-to-analog converter (DAC). It uses a resistor-string as the LSB part for low-power consumption, and uses a current-steering array as the MSB part for high-speed and small size. The LSB and MSB parts are combined by a slew-rate-enhanced class AB output amplifier for high speed. Compared to resistor string DACs, current steering DACs, or resistor-capacitor hybrid DACs, the proposed DAC shows a better tradeoff between power and speed at low power application demanding a sampling clock between 1 MHz and 100 MHz. The prototype is a 12-bit DAC implemented in 0.18-μm CMOS technology with the worst measured DNL/INL of 6.38 LSB / 7.55 LSB. The analogue part power consumption is 1.24 mW and the digital part 0.5mW at 1.35-V power supply at 20-MS/s sampling rate. Its output is single-end buffered voltage with a range of 500 mV. The core area is 0.16 mm2.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126506207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406921
Jiang Xiao-bo, Tang Xue-qing, Huang Wei-pei
The evaluation of error correction code (ECC) for NAND flash memory is increasingly complicated by the increasing bit error rate in memory. The concept of error-free information capacity is proposed to evaluate the performance ECC of NAND flash memory. The new method simultaneously considers the capacity and reliability of NAND flash memory. Low-density parity-check (LDPC) codes with a medium code rate can improve the integrated performance of NAND flash memory in order of magnitudes. Observations provide guides for the development of ECC schemes in NAND flash memory in future. An ECC structure based on adaptive LDPC codes is also presented in this paper. The new structure achieves integrated performance of both capacity and reliability in NAND flash memory.
{"title":"Novel ECC structure and evaluation method for NAND flash memory","authors":"Jiang Xiao-bo, Tang Xue-qing, Huang Wei-pei","doi":"10.1109/SOCC.2015.7406921","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406921","url":null,"abstract":"The evaluation of error correction code (ECC) for NAND flash memory is increasingly complicated by the increasing bit error rate in memory. The concept of error-free information capacity is proposed to evaluate the performance ECC of NAND flash memory. The new method simultaneously considers the capacity and reliability of NAND flash memory. Low-density parity-check (LDPC) codes with a medium code rate can improve the integrated performance of NAND flash memory in order of magnitudes. Observations provide guides for the development of ECC schemes in NAND flash memory in future. An ECC structure based on adaptive LDPC codes is also presented in this paper. The new structure achieves integrated performance of both capacity and reliability in NAND flash memory.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126256404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406966
P. Yan, Shixiong Jiang, R. Sridhar
In Network-on-Chip (NoC) architectures, a faulty router can isolate a functional processing element (PE) from other nodes, severely restricting the performance of the system. This paper presents a fault-tolerant router architecture that can avoid PE isolation even if the router fails. In this design, we connect the local port of the router with one of the other four ports through a fault tolerant control unit that works with the fault detection signal. If the router fails, the control unit will turn on and connect the PE with the neighboring router directly, thus protecting the system functioning. A revised XY-Routing algorithm is also presented to achieve the NoC reconfiguration when router fails. Theoretical analysis show that for a 10*10 mesh NoC, the reliability at year 10 is 20 times better than NoC implemented with traditional router. Also our design has greatly improved value for mean time to failure (MTTF). In video and DSP applications, simulation results show better power control with faulty PEs. The new architecture also has other advantages over annealing re-mapping algorithm. Our design has only 12% area overhead, which is significantly better than other approaches to deal with faults.
{"title":"A novel fault-tolerant router architecture for network-on-chip reconfiguration","authors":"P. Yan, Shixiong Jiang, R. Sridhar","doi":"10.1109/SOCC.2015.7406966","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406966","url":null,"abstract":"In Network-on-Chip (NoC) architectures, a faulty router can isolate a functional processing element (PE) from other nodes, severely restricting the performance of the system. This paper presents a fault-tolerant router architecture that can avoid PE isolation even if the router fails. In this design, we connect the local port of the router with one of the other four ports through a fault tolerant control unit that works with the fault detection signal. If the router fails, the control unit will turn on and connect the PE with the neighboring router directly, thus protecting the system functioning. A revised XY-Routing algorithm is also presented to achieve the NoC reconfiguration when router fails. Theoretical analysis show that for a 10*10 mesh NoC, the reliability at year 10 is 20 times better than NoC implemented with traditional router. Also our design has greatly improved value for mean time to failure (MTTF). In video and DSP applications, simulation results show better power control with faulty PEs. The new architecture also has other advantages over annealing re-mapping algorithm. Our design has only 12% area overhead, which is significantly better than other approaches to deal with faults.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123836858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406981
Hai Helen Li, Xiuyuan Bi, Zhenyu Sun
This paper gives a comprehensive summary of our study in using the spintronic technologies for the on-chip cache density improvement of high performance computing systems. We will start with the spin-transfer torque random access memory (STT-RAM) at the early of stage of commercialization and then extend it to the emerging racetrack memory that has been successfully demonstrated at device and small array level. In multi-level cell (MLC) STT-RAM cache, the cell design constrains, e.g., the switching current requirement and asymmetry in write operations, severely limit the density benefit. Moreover, the two-step read/write accesses and inflexible data mapping strategy may even result in system performance degradation. This paper will discuss our circuit and architecture combined solution. Advanced spintronic technology, i.e., racetrack memory, enables an extremely high storage density and offers a faster-than-Moores law scaling path. Unorthodox new memory hierarchies are necessary to minimize the impact of pseudo-sequential accesses of racetrack memory.
{"title":"The evolutionary spintronic technologies and their usage in high performance computing","authors":"Hai Helen Li, Xiuyuan Bi, Zhenyu Sun","doi":"10.1109/SOCC.2015.7406981","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406981","url":null,"abstract":"This paper gives a comprehensive summary of our study in using the spintronic technologies for the on-chip cache density improvement of high performance computing systems. We will start with the spin-transfer torque random access memory (STT-RAM) at the early of stage of commercialization and then extend it to the emerging racetrack memory that has been successfully demonstrated at device and small array level. In multi-level cell (MLC) STT-RAM cache, the cell design constrains, e.g., the switching current requirement and asymmetry in write operations, severely limit the density benefit. Moreover, the two-step read/write accesses and inflexible data mapping strategy may even result in system performance degradation. This paper will discuss our circuit and architecture combined solution. Advanced spintronic technology, i.e., racetrack memory, enables an extremely high storage density and offers a faster-than-Moores law scaling path. Unorthodox new memory hierarchies are necessary to minimize the impact of pseudo-sequential accesses of racetrack memory.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134414134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406965
N. Nasirian, M. Bayoumi
Network-on-chip (NOC) technology has offered an efficient solution for scalability problem. Following the advent of the NOC technology, decreasing the static power consumption has been at the focus of research and development. Since the routers are the most important and main power-consuming modules of NOC, most of the contributions are related to improvement in router micro-architecture design [1], [2]. Power-gating is currently an effective solution in this area but it causes overhead in terms of delays and in some cases it deteriorates the performance. In this paper, a power efficient design for the network-on-chip (NOC) routers using adaptive routing has been proposed. The Proposed scheme is directing the traffic in a power-gated network with respect to the routers status. In this way, we avoid to turn on the routers, that are in sleep state by alternating the paths. Our simulation has shown that we can achieve near 80% reduction in static power consumption compared to non-power-gated design and we improved the average delay by 35% in comparison with conventional power-gated design.
{"title":"Low-latency power-efficient adaptive router design for network-on-chip","authors":"N. Nasirian, M. Bayoumi","doi":"10.1109/SOCC.2015.7406965","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406965","url":null,"abstract":"Network-on-chip (NOC) technology has offered an efficient solution for scalability problem. Following the advent of the NOC technology, decreasing the static power consumption has been at the focus of research and development. Since the routers are the most important and main power-consuming modules of NOC, most of the contributions are related to improvement in router micro-architecture design [1], [2]. Power-gating is currently an effective solution in this area but it causes overhead in terms of delays and in some cases it deteriorates the performance. In this paper, a power efficient design for the network-on-chip (NOC) routers using adaptive routing has been proposed. The Proposed scheme is directing the traffic in a power-gated network with respect to the routers status. In this way, we avoid to turn on the routers, that are in sleep state by alternating the paths. Our simulation has shown that we can achieve near 80% reduction in static power consumption compared to non-power-gated design and we improved the average delay by 35% in comparison with conventional power-gated design.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"96 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114653182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406985
Guangxiang Li, Jianping Guo, Yanqi Zheng, Mo Huang, Dihu Chen
A novel cascoded flipped voltage follower (CAFVF) based output-capacitorless low-dropout (LDO) regulator is proposed and implemented in 0.18-μm CMOS technology. With a cascode current source (CCS) embedded into the CAFVF structure, the proposed LDO regulator achieves 58.6-dB DC gain in heavy loading condition (100 mA), which is 44-dB for the conventional CAFVF counterpart under identical conditions. The cascode compensation technique is introduced to widen the loop bandwidth and reduce the minimal loading requirement. With a 5-pF compensation capacitor, the minimum load current to keep the proposed LDO regulator stable is reduced to 50 μA. In addition, the unity-gain frequency (UGF) is extended from 1.51 MHz to 2.36 MHz in 100-mA loading condition. Moreover, an accurate stability analysis without ignoring any channel resistance has been presented in this work. Simulation results show that the LDO regulator consumes an ultra-low quiescent current (Iq) of 14 μA for input voltage ranging from 1.2 V to 1.8 V, with a dropout voltage (Vdrop) of 200 mV.
提出了一种新型的基于级联编码翻转电压从动器(CAFVF)的无输出电容低差(LDO)稳压器，并在0.18 μm CMOS工艺上实现。通过将级联码电流源(CCS)嵌入到CAFVF结构中，所提出的LDO稳压器在重负载条件下(100 mA)可实现58.6 db DC增益，而在相同条件下，传统CAFVF对应器件的增益为44 db。引入级联补偿技术，拓宽环路带宽，降低最小负载要求。采用5-pF补偿电容，保持LDO稳压器稳定的最小负载电流降至50 μA。此外，在100 ma负载条件下，单位增益频率(UGF)从1.51 MHz扩展到2.36 MHz。此外，在不忽略任何通道阻力的情况下，本文给出了精确的稳定性分析。仿真结果表明，LDO稳压器在1.2 V ~ 1.8 V的输入电压范围内消耗14 μA的超低静态电流(Iq)，电压降为200 mV。
{"title":"Cascoded flipped voltage follower based output-capacitorless low-dropout regulator for SoCs","authors":"Guangxiang Li, Jianping Guo, Yanqi Zheng, Mo Huang, Dihu Chen","doi":"10.1109/SOCC.2015.7406985","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406985","url":null,"abstract":"A novel cascoded flipped voltage follower (CAFVF) based output-capacitorless low-dropout (LDO) regulator is proposed and implemented in 0.18-μm CMOS technology. With a cascode current source (CCS) embedded into the CAFVF structure, the proposed LDO regulator achieves 58.6-dB DC gain in heavy loading condition (100 mA), which is 44-dB for the conventional CAFVF counterpart under identical conditions. The cascode compensation technique is introduced to widen the loop bandwidth and reduce the minimal loading requirement. With a 5-pF compensation capacitor, the minimum load current to keep the proposed LDO regulator stable is reduced to 50 μA. In addition, the unity-gain frequency (UGF) is extended from 1.51 MHz to 2.36 MHz in 100-mA loading condition. Moreover, an accurate stability analysis without ignoring any channel resistance has been presented in this work. Simulation results show that the LDO regulator consumes an ultra-low quiescent current (Iq) of 14 μA for input voltage ranging from 1.2 V to 1.8 V, with a dropout voltage (Vdrop) of 200 mV.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121080722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406987
Chia-Tsen Dai, M. Ker
For high-voltage (HV) application, an on-chip ESD protection solution has been proposed in a 0.25-μm HV BCD process by using low-voltage (LV) p-type devices with the stacked configuration. Experimental results in silicon chip have verified that the proposed design can successfully protect the 60-V pins of a battery-monitoring IC against over 8-kV human-body-mode (HBM) ESD stress.
{"title":"ESD protection design with stacked low-voltage devices for high-voltage pins of battery-monitoring IC","authors":"Chia-Tsen Dai, M. Ker","doi":"10.1109/SOCC.2015.7406987","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406987","url":null,"abstract":"For high-voltage (HV) application, an on-chip ESD protection solution has been proposed in a 0.25-μm HV BCD process by using low-voltage (LV) p-type devices with the stacked configuration. Experimental results in silicon chip have verified that the proposed design can successfully protect the 60-V pins of a battery-monitoring IC against over 8-kV human-body-mode (HBM) ESD stress.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124546233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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