The objective of this paper is to provide an effective technique far accurate modeling of the external input sequences that affect the behavior of Finite State Machines (FSMs). Based on the block entropy concept, we present a technique for identifying the order of variable-order Markov sources of information. Furthermore, using dynamic Markov modeling, we propose an effective approach to compact an initial sequence into a much shorter equivalent one. The compacted sequence, can be subsequently used with any available simulator to derive the steady-state and transition probabilities, and the total power consumption in the target circuit. As the results demonstrate, large compaction ratios of orders of magnitude can be obtained without significant loss (less than 5% on average) in the accuracy of estimated values.
{"title":"Composite sequence compaction for finite-state machines using block entropy and high-order Markov models","authors":"R. Marculescu, Diana Marculescu, Massoud Pedram","doi":"10.1145/263272.263325","DOIUrl":"https://doi.org/10.1145/263272.263325","url":null,"abstract":"The objective of this paper is to provide an effective technique far accurate modeling of the external input sequences that affect the behavior of Finite State Machines (FSMs). Based on the block entropy concept, we present a technique for identifying the order of variable-order Markov sources of information. Furthermore, using dynamic Markov modeling, we propose an effective approach to compact an initial sequence into a much shorter equivalent one. The compacted sequence, can be subsequently used with any available simulator to derive the steady-state and transition probabilities, and the total power consumption in the target circuit. As the results demonstrate, large compaction ratios of orders of magnitude can be obtained without significant loss (less than 5% on average) in the accuracy of estimated values.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116824827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Uno, K. Kumatani, H. Okuhata, I. Shirakawa, T. Chiba
A high performance and low power architecture is devised for a 4 Mbps infrared wireless communication system dedicated to mobile computing. In this architecture 4PPM (4-Pulse Position Modulation) infrared signals detected by an infrared receiver are digitized into TTL interface level pulses, and the digitized pulses are demodulated by a 1-bit digital demodulator. To extend the range of the link length, a 4PPM demodulator is synthesized to implement a demodulation algorithm which is constructed so as to accommodate the output tolerance of the infrared receiver. A experimental results show that the proposed 4 Mbps infrared communication system can achieve an error free link in the range of 0-140 cm at power consumption of 245 mW and 65 mW for transmitting and receiving, respectively. The communication controller is integrated in a 0.6 /spl mu/m CMOS standard-cell chip, which contains 10,015 transistors on a 12 mm/sup 2/ die.
{"title":"Low power architecture for high speed infrared wireless communication system","authors":"H. Uno, K. Kumatani, H. Okuhata, I. Shirakawa, T. Chiba","doi":"10.1145/263272.263347","DOIUrl":"https://doi.org/10.1145/263272.263347","url":null,"abstract":"A high performance and low power architecture is devised for a 4 Mbps infrared wireless communication system dedicated to mobile computing. In this architecture 4PPM (4-Pulse Position Modulation) infrared signals detected by an infrared receiver are digitized into TTL interface level pulses, and the digitized pulses are demodulated by a 1-bit digital demodulator. To extend the range of the link length, a 4PPM demodulator is synthesized to implement a demodulation algorithm which is constructed so as to accommodate the output tolerance of the infrared receiver. A experimental results show that the proposed 4 Mbps infrared communication system can achieve an error free link in the range of 0-140 cm at power consumption of 245 mW and 65 mW for transmitting and receiving, respectively. The communication controller is integrated in a 0.6 /spl mu/m CMOS standard-cell chip, which contains 10,015 transistors on a 12 mm/sup 2/ die.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129531684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The invention of the bipolar transistor in 1948 and the integrated circuit in 1958 as well as the announcement of CMOS logic circuits in 1963 demonstrated the critical basis for modern low power electronics. Future opportunities for low power gigascale integration will be governed by a hierarchy of physical limits whose five levels can be codified as: (1) fundamental, (2) material, (3) device, (4) circuit and (5) system. Through analysis of the attributes of a hypothetical quasi-asymptotic 10 nm single electron MOSFET and its local interconnection network, it is apparent that such a device would have an unaffordably large switching error rate. However, it is feasible that low power electronics may well achieve a capability within several hundred times the switching energy of the 10 nm single electron MOSFET.
{"title":"A history of low power electronics: how it began and where it's headed","authors":"J. Meindl","doi":"10.1145/263272.263311","DOIUrl":"https://doi.org/10.1145/263272.263311","url":null,"abstract":"The invention of the bipolar transistor in 1948 and the integrated circuit in 1958 as well as the announcement of CMOS logic circuits in 1963 demonstrated the critical basis for modern low power electronics. Future opportunities for low power gigascale integration will be governed by a hierarchy of physical limits whose five levels can be codified as: (1) fundamental, (2) material, (3) device, (4) circuit and (5) system. Through analysis of the attributes of a hypothetical quasi-asymptotic 10 nm single electron MOSFET and its local interconnection network, it is apparent that such a device would have an unaffordably large switching error rate. However, it is feasible that low power electronics may well achieve a capability within several hundred times the switching energy of the 10 nm single electron MOSFET.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128526205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This report, based on the most recent analytical and experimental studies of CMOS scaling and gate delay models, reexamines the fundamental design quantities such as driving current, I/sub dsat/, propagation delay, t/sub pd/, and switching energy, E, and investigates device optimization issues in deep sub-micron regime. Empirical I/sub dsat/ equations and device optimization guidelines with gate oxide, channel length and power supply scaling as well as interconnect loading are extracted.
{"title":"Device and technology optimizations for low power design in deep sub-micron regime","authors":"Kai Chen, C. Hu","doi":"10.1145/263272.263363","DOIUrl":"https://doi.org/10.1145/263272.263363","url":null,"abstract":"This report, based on the most recent analytical and experimental studies of CMOS scaling and gate delay models, reexamines the fundamental design quantities such as driving current, I/sub dsat/, propagation delay, t/sub pd/, and switching energy, E, and investigates device optimization issues in deep sub-micron regime. Empirical I/sub dsat/ equations and device optimization guidelines with gate oxide, channel length and power supply scaling as well as interconnect loading are extracted.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124683129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a survey of low power techniques for Read Only Memories (ROMs). Significant savings in power dissipation are achieved through the use of techniques at the circuit and architecture level. The ROM circuits have been designed in O.35 /spl mu/m CMOS technology and simulated using PowerMill.
本文介绍了只读存储器(rom)的低功耗技术。通过在电路和架构级别使用技术，可以显著节省功耗。采用0.35 /spl μ m CMOS工艺设计了ROM电路，并用PowerMill进行了仿真。
{"title":"Survey of low power techniques for ROMs","authors":"Edwin de Angel, E. Swartzlander","doi":"10.1145/263272.263274","DOIUrl":"https://doi.org/10.1145/263272.263274","url":null,"abstract":"This paper presents a survey of low power techniques for Read Only Memories (ROMs). Significant savings in power dissipation are achieved through the use of techniques at the circuit and architecture level. The ROM circuits have been designed in O.35 /spl mu/m CMOS technology and simulated using PowerMill.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123723608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A low voltage current source is described that has a minimum input voltage of less than 0.1 V and a minimum output voltage swing of 0.2 V. Although this current source has an output voltage range equivalent to a simple current mirror, the output resistance is amplified by a feedback amplifier to produce an output resistance on the order of a cascode current source. The low voltage current source was fabricated in a 2 micron n-well CMOS process. The measured minimum output voltage is 0.2 V and the measured output resistance is 11 M/spl Omega/. Using this current source, a 1.8 V folded-cascode op amp was designed. The simulated open loop gain was 50 dB with a nearly rail-to-rail output linear range.
{"title":"A low voltage CMOS current source","authors":"Detlev Schmitt, T. Fiez","doi":"10.1145/263272.263301","DOIUrl":"https://doi.org/10.1145/263272.263301","url":null,"abstract":"A low voltage current source is described that has a minimum input voltage of less than 0.1 V and a minimum output voltage swing of 0.2 V. Although this current source has an output voltage range equivalent to a simple current mirror, the output resistance is amplified by a feedback amplifier to produce an output resistance on the order of a cascode current source. The low voltage current source was fabricated in a 2 micron n-well CMOS process. The measured minimum output voltage is 0.2 V and the measured output resistance is 11 M/spl Omega/. Using this current source, a 1.8 V folded-cascode op amp was designed. The simulated open loop gain was 50 dB with a nearly rail-to-rail output linear range.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132437122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Banna, Philip C. H. Chan, M. Chan, S. Fung, P. Ko
In this paper we report the fully depleted CMOS/SOI device design guidelines for low power application. Optimal technology, device and circuit parameters are discussed and compared with bulk CMOS based design. The differences and similarities are summarized. We believe this is the first such study to be reported.
{"title":"Fully depleted CMOS/SOI device design guidelines for low power applications","authors":"S. Banna, Philip C. H. Chan, M. Chan, S. Fung, P. Ko","doi":"10.1145/263272.263361","DOIUrl":"https://doi.org/10.1145/263272.263361","url":null,"abstract":"In this paper we report the fully depleted CMOS/SOI device design guidelines for low power application. Optimal technology, device and circuit parameters are discussed and compared with bulk CMOS based design. The differences and similarities are summarized. We believe this is the first such study to be reported.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115869892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We introduce a new method for the synthesis of power-optimal asynchronous control-circuits. The method includes two steps: (i) an exact algorithm for 2-level synthesis, and (ii) heuristic algorithms for multi-level synthesis. Unlike most existing synchronous algorithms, we incorporate both temporal dependence and glitch activity in our model to guide synthesis. Results, using only our 2-level minimization, show power reduction up to 33%.
{"title":"Synthesis of low-power asynchronous circuits in a specified environment","authors":"S. Nowick, Michael Theobald","doi":"10.1145/263272.263291","DOIUrl":"https://doi.org/10.1145/263272.263291","url":null,"abstract":"We introduce a new method for the synthesis of power-optimal asynchronous control-circuits. The method includes two steps: (i) an exact algorithm for 2-level synthesis, and (ii) heuristic algorithms for multi-level synthesis. Unlike most existing synchronous algorithms, we incorporate both temporal dependence and glitch activity in our model to guide synthesis. Results, using only our 2-level minimization, show power reduction up to 33%.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117013103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A differential oscillator topology with an integrated resonator is presented that allows for low supply voltages and RF/microwave frequencies. On-chip, pad-to-pad bond wire inductors and noise matching techniques are used to minimize phase noise. Operation in the 1.8 GHz range with a phase noise spectral density of -94 dBc/Hz at a 100 kHz offset is achieved with 5 mA drawn from a 1 V supply, and oscillation is supported down to power supply levels of 3.3 mW.
{"title":"A 1 V, 5 mW, 1.8 GHz, balanced voltage-controlled oscillator with an integrated resonator","authors":"D. Hitko, T. Tewksbury, C. Sodini","doi":"10.1109/LPE.1997.621232","DOIUrl":"https://doi.org/10.1109/LPE.1997.621232","url":null,"abstract":"A differential oscillator topology with an integrated resonator is presented that allows for low supply voltages and RF/microwave frequencies. On-chip, pad-to-pad bond wire inductors and noise matching techniques are used to minimize phase noise. Operation in the 1.8 GHz range with a phase noise spectral density of -94 dBc/Hz at a 100 kHz offset is achieved with 5 mA drawn from a 1 V supply, and oscillation is supported down to power supply levels of 3.3 mW.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121134010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a new model for the stability analysis of low-pass Sigma-Delta modulators (/spl Sigma//spl Delta/Ms) using the describing function method. The transfer of a single-bit quantizer is represented by a global signal gain and a phase uncertainty. This phase uncertainty arises from the limited accuracy in time with which the quantizer can detect the quantization-level crossings. This new model allows for a better prediction of possible idle patterns (important for the in-band signal-to-quantization error ratio), and calculation of zero-input stability boundaries for loop-filter parameters in higher order low-pass /spl Sigma//spl Delta/Ms.
{"title":"New stability criteria for the design of low-pass sigma-delta modulators","authors":"J. V. van Engelen, J. van de Plassche","doi":"10.1145/263272.263302","DOIUrl":"https://doi.org/10.1145/263272.263302","url":null,"abstract":"This paper describes a new model for the stability analysis of low-pass Sigma-Delta modulators (/spl Sigma//spl Delta/Ms) using the describing function method. The transfer of a single-bit quantizer is represented by a global signal gain and a phase uncertainty. This phase uncertainty arises from the limited accuracy in time with which the quantizer can detect the quantization-level crossings. This new model allows for a better prediction of possible idle patterns (important for the in-band signal-to-quantization error ratio), and calculation of zero-input stability boundaries for loop-filter parameters in higher order low-pass /spl Sigma//spl Delta/Ms.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115151372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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