Translation look-aside buffers (TLBs) are small caches to speed-up address translation in processors with virtual memory. This paper considers two issues: (1) a comparison of the power consumption of fully-associative, set-associative, and direct mapped TLBs for the same miss rate and (2) the proposal of modifications of the basic cells and of the structure of set-associative TLBs to reduce the power. The power evaluation is done using a model and the miss rates are obtained from simulations of the SPEC92 benchmark. With respect to (1) we conclude that for small TLBs (high miss rates) fully-associative TLBs consume less power but for larger TLBs (low miss rates) set-associative TLBs are better. Moreover, the proposed modifications produce significant reductions in power consumption. Our evaluations show a reduction of 40 to 60% compared to the best traditional TLB. The proposed TLB implementation produces an increase in delay and in area. However, these increases are tolerable because the cycle time is determined by the slower cache and because the TLB area corresponds to only a small portion of the chip area.
{"title":"Reducing TLB power requirements","authors":"Toni Juan, T. Lang, J. Navarro","doi":"10.1145/263272.263332","DOIUrl":"https://doi.org/10.1145/263272.263332","url":null,"abstract":"Translation look-aside buffers (TLBs) are small caches to speed-up address translation in processors with virtual memory. This paper considers two issues: (1) a comparison of the power consumption of fully-associative, set-associative, and direct mapped TLBs for the same miss rate and (2) the proposal of modifications of the basic cells and of the structure of set-associative TLBs to reduce the power. The power evaluation is done using a model and the miss rates are obtained from simulations of the SPEC92 benchmark. With respect to (1) we conclude that for small TLBs (high miss rates) fully-associative TLBs consume less power but for larger TLBs (low miss rates) set-associative TLBs are better. Moreover, the proposed modifications produce significant reductions in power consumption. Our evaluations show a reduction of 40 to 60% compared to the best traditional TLB. The proposed TLB implementation produces an increase in delay and in area. However, these increases are tolerable because the cycle time is determined by the slower cache and because the TLB area corresponds to only a small portion of the chip area.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"11 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132906855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The energy consumption at the I/O pins is a significant part of the overall chip consumption. This paper presents a method for encoding an external address bus which lowers its activity and, thus, decreases the energy. This method relies on the locality of memory references. Since applications favor a few working zones of their address space at each instant, for an address to one of these zones only the offset of this reference with respect to the previous reference to that zone needs to be sent over the bus, along with an identifier of the current working zone. This is combined with a modified one-shot encoding for the offset. An estimate of the area and energy overhead of the encoder/decoder are given; their effect is small. The approach has been applied to two memory-intensive examples, obtaining a bus-activity reduction of about 2/3 in both of them. Comparisons are given with previous methods for bus encoding, showing significant improvement.
{"title":"Exploiting the locality of memory references to reduce the address bus energy","authors":"E. Musoll, T. Lang, J. Cortadella","doi":"10.1145/263272.263334","DOIUrl":"https://doi.org/10.1145/263272.263334","url":null,"abstract":"The energy consumption at the I/O pins is a significant part of the overall chip consumption. This paper presents a method for encoding an external address bus which lowers its activity and, thus, decreases the energy. This method relies on the locality of memory references. Since applications favor a few working zones of their address space at each instant, for an address to one of these zones only the offset of this reference with respect to the previous reference to that zone needs to be sent over the bus, along with an identifier of the current working zone. This is combined with a modified one-shot encoding for the offset. An estimate of the area and energy overhead of the encoder/decoder are given; their effect is small. The approach has been applied to two memory-intensive examples, obtaining a bus-activity reduction of about 2/3 in both of them. Comparisons are given with previous methods for bus encoding, showing significant improvement.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124704112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Yoshida, Bao-Yu Song, H. Okuhata, T. Onoye, I. Shirakawa
A low-power processor architecture is described dedicatedly for embedded application programs by means of an object code compression approach. This approach unifies duplicated instructions existing in the embedded program and assigns a compressed object code to such an instruction. An instruction decompressor is constructed so as to generate an object code from each compressed object code (pseudo code) input. A single-chip implementation of this decompressor together with a processor core can effectively reduce the bandwidth required for the I/O interface. To demonstrate the practicability of the proposed approach, experiments are applied to an embedded processor ARM610 which attains 62.5% code compression, and hence 42.3% of the power consumption of instruction memory can be reduced.
{"title":"An object code compression approach to embedded processors","authors":"Y. Yoshida, Bao-Yu Song, H. Okuhata, T. Onoye, I. Shirakawa","doi":"10.1145/263272.263349","DOIUrl":"https://doi.org/10.1145/263272.263349","url":null,"abstract":"A low-power processor architecture is described dedicatedly for embedded application programs by means of an object code compression approach. This approach unifies duplicated instructions existing in the embedded program and assigns a compressed object code to such an instruction. An instruction decompressor is constructed so as to generate an object code from each compressed object code (pseudo code) input. A single-chip implementation of this decompressor together with a processor core can effectively reduce the bandwidth required for the I/O interface. To demonstrate the practicability of the proposed approach, experiments are applied to an embedded processor ARM610 which attains 62.5% code compression, and hence 42.3% of the power consumption of instruction memory can be reduced.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"140 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129652791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A technology dependent power optimization technique is proposed which formulates the problem of hot spot reduction as a variant of the engineering change (EC) problem. A technique is presented for determining the sensitivity of circuit power dissipation to functional changes considering both local and global effects. This sensitivity is combined with a measure of synthesis flexibility to identify hot regions in the circuit which have a lot of flexibility in making functional changes and for whom a small functional change can greatly affect the overall power dissipation. An incompletely specified target function is constructed for the hot region such that any implementation satisfying it is expected to reduce power. A rewiring algorithm is used to solve the resulting EC problem without affecting circuit area, gate capacitance or delay under the unit delay model. Experimental results on a set of MCNC benchmark circuits show that the proposed approach can give up to 13% reduction in power dissipation with an average reduction of 4%.
{"title":"Engineering change for power optimization using global sensitivity and synthesis flexibility","authors":"Premal Buch, C. Lennard, A. Newton","doi":"10.1145/263272.263290","DOIUrl":"https://doi.org/10.1145/263272.263290","url":null,"abstract":"A technology dependent power optimization technique is proposed which formulates the problem of hot spot reduction as a variant of the engineering change (EC) problem. A technique is presented for determining the sensitivity of circuit power dissipation to functional changes considering both local and global effects. This sensitivity is combined with a measure of synthesis flexibility to identify hot regions in the circuit which have a lot of flexibility in making functional changes and for whom a small functional change can greatly affect the overall power dissipation. An incompletely specified target function is constructed for the hot region such that any implementation satisfying it is expected to reduce power. A rewiring algorithm is used to solve the resulting EC problem without affecting circuit area, gate capacitance or delay under the unit delay model. Experimental results on a set of MCNC benchmark circuits show that the proposed approach can give up to 13% reduction in power dissipation with an average reduction of 4%.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121363259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper investigates delay, power and area of several critical library components for high-performance, low-power microprocessor designs. To improve performance of a 0.18-/spl mu/m technology at a supply voltage of 1.8 V, the proposed hybrid dual-V/sub t/ (HDVT) circuit architectures enhance speed of low-V/sub t/ by 21% while reducing leakage power dissipation of low-V/sub t/ by an order of magnitude for combinatorial logic. For sequential elements, a HDVT split-slave dual-path (HSSDP) and Push-Pull Isolation (HPPI) registers are proposed to improve 29-92% performance over an HDVT-conventional registers with 20-89% less energy consumption. For the datapath, a HDVT hierarchical, reduced-swing, dual-V/sub t/ logic (HHRSL) comparator is proposed to improve the delay of prior arts by up to 50%.
{"title":"Hybrid dual-threshold design techniques for high-performance processors with low-power features","authors":"U. Ko, Andrew Pua, A. Hill, Pranjal Srivastava","doi":"10.1145/263272.263362","DOIUrl":"https://doi.org/10.1145/263272.263362","url":null,"abstract":"This paper investigates delay, power and area of several critical library components for high-performance, low-power microprocessor designs. To improve performance of a 0.18-/spl mu/m technology at a supply voltage of 1.8 V, the proposed hybrid dual-V/sub t/ (HDVT) circuit architectures enhance speed of low-V/sub t/ by 21% while reducing leakage power dissipation of low-V/sub t/ by an order of magnitude for combinatorial logic. For sequential elements, a HDVT split-slave dual-path (HSSDP) and Push-Pull Isolation (HPPI) registers are proposed to improve 29-92% performance over an HDVT-conventional registers with 20-89% less energy consumption. For the datapath, a HDVT hierarchical, reduced-swing, dual-V/sub t/ logic (HHRSL) comparator is proposed to improve the delay of prior arts by up to 50%.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124105447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jianjun J. Zhou, R. M. Ziazadeh, H. Ng, Hiok-Tiaq Ng, D. Allstot
Low-voltage/low-power requirements have become essential considerations in modern mixed-signal designs. In this paper, we present a 1.8 V multi-stage opamp designed using a standard 0.6 /spl mu/m n-well CMOS process. The op amp designs include a new high efficiency DC-DC converter used in a low-voltage frequency compensation configuration that tracks process, temperature, and supply voltage variations and enables accurate pole-zero cancellation. Low-power operation is compared in passive and active g/sub m/ feedforward compensation techniques. An automatic threshold calibration scheme is also described.
{"title":"Charge-pump assisted low-power/low-voltage CMOS op amp design","authors":"Jianjun J. Zhou, R. M. Ziazadeh, H. Ng, Hiok-Tiaq Ng, D. Allstot","doi":"10.1145/263272.263299","DOIUrl":"https://doi.org/10.1145/263272.263299","url":null,"abstract":"Low-voltage/low-power requirements have become essential considerations in modern mixed-signal designs. In this paper, we present a 1.8 V multi-stage opamp designed using a standard 0.6 /spl mu/m n-well CMOS process. The op amp designs include a new high efficiency DC-DC converter used in a low-voltage frequency compensation configuration that tracks process, temperature, and supply voltage variations and enables accurate pole-zero cancellation. Low-power operation is compared in passive and active g/sub m/ feedforward compensation techniques. An automatic threshold calibration scheme is also described.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126355310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the design of a low power spread spectrum correlator. We look at two major approaches and evaluate the best alternative for power reduction. We first consider a shift register FIFO implementation and look at reducing the switching activity for the arithmetic operations with a change in the addition algorithm. The correlation calculation can be modified to include storage of the previous result so that arithmetic circuits need only compute the difference between the present and next value. A binary adder tree with bypass can then reduce power by shutting off unnecessary computations. We then look at minimizing the power for sample storage by limiting the amount of data moved per cycle. This can be achieved by using a register file FIFO implementation. Interestingly the two power minimization techniques, bypass adder tree and register file FIFO implementation, were found to be strongly non-orthogonal, with the final effect that the register file changes the data statistics in such a way that it cancels the savings for the adder tree with bypass. The final solution of a register file with standard adder tree was found to have the lowest power dissipation. Using Bus-Invert for encoding the data as it enters the FIFO further reduces the power consumption due to the global bus of the register file.
{"title":"Power reduction techniques for a spread spectrum based correlator","authors":"David Garrett, M. Stan","doi":"10.1145/263272.263339","DOIUrl":"https://doi.org/10.1145/263272.263339","url":null,"abstract":"This paper presents the design of a low power spread spectrum correlator. We look at two major approaches and evaluate the best alternative for power reduction. We first consider a shift register FIFO implementation and look at reducing the switching activity for the arithmetic operations with a change in the addition algorithm. The correlation calculation can be modified to include storage of the previous result so that arithmetic circuits need only compute the difference between the present and next value. A binary adder tree with bypass can then reduce power by shutting off unnecessary computations. We then look at minimizing the power for sample storage by limiting the amount of data moved per cycle. This can be achieved by using a register file FIFO implementation. Interestingly the two power minimization techniques, bypass adder tree and register file FIFO implementation, were found to be strongly non-orthogonal, with the final effect that the register file changes the data statistics in such a way that it cancels the savings for the adder tree with bypass. The final solution of a register file with standard adder tree was found to have the lowest power dissipation. Using Bus-Invert for encoding the data as it enters the FIFO further reduces the power consumption due to the global bus of the register file.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126494765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Maksimović, V. Oklobdzija, B. Nikolić, K. Current
In this paper we describe the design and experimental evaluation of a clocked CMOS adiabatic logic (CAL). CAL is a dual-rail logic that operates from a single-phase AC power-clock supply in the 'adiabatic' mode, or from a DC power supply in the 'non-adiabatic' mode. In the adiabatic mode, the power-clock supply waveform is generated using an on-chip switching transistor and a small external inductor between the chip and a low-voltage DC supply. Circuit operation and performance are evaluated using a chain of inverters realized in 1.2 /spl mu/m technology. Experimental results show energy savings in the adiabatic mode versus the non-adiabatic mode at clock frequencies up to about 40 MHz.
{"title":"Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results","authors":"D. Maksimović, V. Oklobdzija, B. Nikolić, K. Current","doi":"10.1145/263272.263365","DOIUrl":"https://doi.org/10.1145/263272.263365","url":null,"abstract":"In this paper we describe the design and experimental evaluation of a clocked CMOS adiabatic logic (CAL). CAL is a dual-rail logic that operates from a single-phase AC power-clock supply in the 'adiabatic' mode, or from a DC power supply in the 'non-adiabatic' mode. In the adiabatic mode, the power-clock supply waveform is generated using an on-chip switching transistor and a small external inductor between the chip and a low-voltage DC supply. Circuit operation and performance are evaluated using a chain of inverters realized in 1.2 /spl mu/m technology. Experimental results show energy savings in the adiabatic mode versus the non-adiabatic mode at clock frequencies up to about 40 MHz.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127438656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To optimize performance and power of a processor with both precharged and static circuit styles, a self-timed modified cascode latch (MCL) is proposed for dual-rail domino to static logic interface. Compared to conventional self-timed cascode and cross-coupled NAND latches, the innovative MCL achieves the highest performance and lowest power dissipation with reasonable noise immunity. Ease of embedding logic functions in these self-timed latches is also studied. For interfacing single-rail domino to static logic, the pseudo-inverter latch (PIL) is the most power efficient latch when compared with the conventional transparent and cross-coupled NAND latches. Based on a 0.18 /spl mu/m CMOS nominal process with a 1.6 V supply voltage, effects on these latches' power dissipation and delay from scaling supply voltage and output load are presented respectively.
{"title":"High-performance, low-power design techniques for dynamic to static logic interface","authors":"June Jiang, Kan Lu, U. Ko","doi":"10.1145/263272.263275","DOIUrl":"https://doi.org/10.1145/263272.263275","url":null,"abstract":"To optimize performance and power of a processor with both precharged and static circuit styles, a self-timed modified cascode latch (MCL) is proposed for dual-rail domino to static logic interface. Compared to conventional self-timed cascode and cross-coupled NAND latches, the innovative MCL achieves the highest performance and lowest power dissipation with reasonable noise immunity. Ease of embedding logic functions in these self-timed latches is also studied. For interfacing single-rail domino to static logic, the pseudo-inverter latch (PIL) is the most power efficient latch when compared with the conventional transparent and cross-coupled NAND latches. Based on a 0.18 /spl mu/m CMOS nominal process with a 1.6 V supply voltage, effects on these latches' power dissipation and delay from scaling supply voltage and output load are presented respectively.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133924394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Igarashi, K. Usami, K. Nogami, F. Minami, Y. Kawasaki, T. Aoki, M. Takano, C. Mizuno, T. Ishikawa, M. Kanazawa, Shinji Sonoda, M. Ichida, N. Hatanaka
We present a low-power design method that utilizes the multiple supply voltages. The proposed method reduces the power consumption of random logic circuits by 47% on the average, with up to 15% area overhead, by the combination of "Clustered Voltage Scaling (CVS) scheme" and "Row by Row optimized Power Supply (RRPS) scheme". By the CVS scheme, the optimal netlist, that uses the minimized number of the level converters and the maximized number of the low Vdd gates under the timing constraints, is generated. To avoid the wiring resource consumption and the increase of the interconnect delay caused by the layout constraints of the multiple-supply-voltage design, a new power bus wiring scheme called "RRPS scheme" is proposed. The proposed method is applied to a media processor chip Mpact/sup TM/ and achieved the above mentioned results. In this paper, the emphasis is put on the interrelation between the generation of the two-supply-voltage netlist with the CVS scheme and the layout technology, such as the power supply scheme and the placement of the multiple-supply-voltage gates. The clocking scheme for the multiple supply voltages is also discussed.
{"title":"A low-power design method using multiple supply voltages","authors":"M. Igarashi, K. Usami, K. Nogami, F. Minami, Y. Kawasaki, T. Aoki, M. Takano, C. Mizuno, T. Ishikawa, M. Kanazawa, Shinji Sonoda, M. Ichida, N. Hatanaka","doi":"10.1145/263272.263279","DOIUrl":"https://doi.org/10.1145/263272.263279","url":null,"abstract":"We present a low-power design method that utilizes the multiple supply voltages. The proposed method reduces the power consumption of random logic circuits by 47% on the average, with up to 15% area overhead, by the combination of \"Clustered Voltage Scaling (CVS) scheme\" and \"Row by Row optimized Power Supply (RRPS) scheme\". By the CVS scheme, the optimal netlist, that uses the minimized number of the level converters and the maximized number of the low Vdd gates under the timing constraints, is generated. To avoid the wiring resource consumption and the increase of the interconnect delay caused by the layout constraints of the multiple-supply-voltage design, a new power bus wiring scheme called \"RRPS scheme\" is proposed. The proposed method is applied to a media processor chip Mpact/sup TM/ and achieved the above mentioned results. In this paper, the emphasis is put on the interrelation between the generation of the two-supply-voltage netlist with the CVS scheme and the layout technology, such as the power supply scheme and the placement of the multiple-supply-voltage gates. The clocking scheme for the multiple supply voltages is also discussed.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127762060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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