This paper presents a new two-gate-delay implementation of the Booth encoder and partial product generator, which eliminates the unnecessary glitches associated with the Booth multiplier. In addition, a modified signed/unsigned (MSU) and modified sign-generate (MSG) algorithms, suitable especially for signed/unsigned multipliers, were developed in order to reduce the compression level needed in the Wallace tree, and hence reduce the multiplier hardware. Using these features reduces the multiplier array energy dissipation by about 30% and increases speed by about 10%.
{"title":"Minimizing energy dissipation in high-speed multipliers","authors":"R. Fried","doi":"10.1145/263272.263337","DOIUrl":"https://doi.org/10.1145/263272.263337","url":null,"abstract":"This paper presents a new two-gate-delay implementation of the Booth encoder and partial product generator, which eliminates the unnecessary glitches associated with the Booth multiplier. In addition, a modified signed/unsigned (MSU) and modified sign-generate (MSG) algorithms, suitable especially for signed/unsigned multipliers, were developed in order to reduce the compression level needed in the Wallace tree, and hence reduce the multiplier hardware. Using these features reduces the multiplier array energy dissipation by about 30% and increases speed by about 10%.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130831312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Designing for low power has become increasingly important in a wide variety of applications, ranging from wireless communications where battery life is the critical factor to high performance computing where reliability and cooling issues have become first order concerns. Numerous tools have emerged in recent years to help designers address these issues, yet some aspects of the power problem are still inadequately addressed. This paper will survey existing commercial tools used to estimate and optimize power, analyze their strengths and weaknesses, and describe a variety of open issues.
{"title":"Issues and directions in low power design tools: an industrial perspective","authors":"J. Frenkil","doi":"10.1109/LPE.1997.621269","DOIUrl":"https://doi.org/10.1109/LPE.1997.621269","url":null,"abstract":"Designing for low power has become increasingly important in a wide variety of applications, ranging from wireless communications where battery life is the critical factor to high performance computing where reliability and cooling issues have become first order concerns. Numerous tools have emerged in recent years to help designers address these issues, yet some aspects of the power problem are still inadequately addressed. This paper will survey existing commercial tools used to estimate and optimize power, analyze their strengths and weaknesses, and describe a variety of open issues.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115054053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Encouraged by the promising results of SOI device-based studies, CMOS on SOI has recently been suggested for the low power digital applications. In this paper, the crucial effects of SOI device characteristics on switching circuits is investigated, and the relative merits of SOI and bulk devices for circuit applications are compared. As a result, the impact of the floating body on SOI circuit performance and the related device solutions are discussed.
{"title":"The impact of SOI MOSFETs on low power digital circuits","authors":"Y. Tseng, S. Chin, J. Woo","doi":"10.1109/LPE.1997.621291","DOIUrl":"https://doi.org/10.1109/LPE.1997.621291","url":null,"abstract":"Encouraged by the promising results of SOI device-based studies, CMOS on SOI has recently been suggested for the low power digital applications. In this paper, the crucial effects of SOI device characteristics on switching circuits is investigated, and the relative merits of SOI and bulk devices for circuit applications are compared. As a result, the impact of the floating body on SOI circuit performance and the related device solutions are discussed.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"228 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132493694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper provides an overview of SOI MOSFET theory and practice with emphasis on circuit applications issues. Fully and partially depleted channel devices are considered and particular attention is given to describing the so-called floating-body effects that are unique to SOI. Two advanced SOI MOSFET configurations, dual-gate SOI and active body SOI, specifically developed for low voltage circuit applications are also discussed.
{"title":"SOI CMOS as a mainstream low-power technology: a critical assessment","authors":"D. Antoniadis","doi":"10.1145/263272.263357","DOIUrl":"https://doi.org/10.1145/263272.263357","url":null,"abstract":"This paper provides an overview of SOI MOSFET theory and practice with emphasis on circuit applications issues. Fully and partially depleted channel devices are considered and particular attention is given to describing the so-called floating-body effects that are unique to SOI. Two advanced SOI MOSFET configurations, dual-gate SOI and active body SOI, specifically developed for low voltage circuit applications are also discussed.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130264233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new statistical technique for average power estimation in sequential circuits is presented. Due to the feedback mechanism, conventional statistical procedures cannot be applied to infer the average power of sequential circuits. As a remedy, we propose a sequential procedure to determine an independence interval which is used to generate an independent and identically distributed (iid) power sample. A distribution-independent stopping criterion is applied to choose an appropriate convergent sample size. The proposed technique is applied to a set of sequential benchmark circuits and demonstrates high accuracy and efficiency.
{"title":"A sequential procedure for average power analysis of sequential circuits","authors":"L. Yuan, S. Kang","doi":"10.1145/263272.263340","DOIUrl":"https://doi.org/10.1145/263272.263340","url":null,"abstract":"A new statistical technique for average power estimation in sequential circuits is presented. Due to the feedback mechanism, conventional statistical procedures cannot be applied to infer the average power of sequential circuits. As a remedy, we propose a sequential procedure to determine an independence interval which is used to generate an independent and identically distributed (iid) power sample. A distribution-independent stopping criterion is applied to choose an appropriate convergent sample size. The proposed technique is applied to a set of sequential benchmark circuits and demonstrates high accuracy and efficiency.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115175146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a novel method to estimate and to reduce redundant power of synchronous circuits at RT level design. Because much redundant power is caused by redundant clockings which activate registers unnecessarily, we detect these clockings. They are detected from the difference of the numbers of incoming and outgoing data of a register. Then we introduce a gated-clock scheme to reduce the power consumption of the circuits using our estimation results. Experimental results demonstrate the accuracy of our method and the effect on power reduction.
{"title":"A method of redundant clocking detection and power reduction at RT level design","authors":"M. Ohnishi, A. Yamada, H. Noda, T. Kambe","doi":"10.1145/263272.263307","DOIUrl":"https://doi.org/10.1145/263272.263307","url":null,"abstract":"This paper proposes a novel method to estimate and to reduce redundant power of synchronous circuits at RT level design. Because much redundant power is caused by redundant clockings which activate registers unnecessarily, we detect these clockings. They are detected from the difference of the numbers of incoming and outgoing data of a register. Then we introduce a gated-clock scheme to reduce the power consumption of the circuits using our estimation results. Experimental results demonstrate the accuracy of our method and the effect on power reduction.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128526530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper demonstrates the feasibility of a register-memory addressing mode in microprocessors targeted for low power applications. Using a high level power profiling tool that performs software energy evaluation, the major sources of power dissipation in a typical RISC processor are identified. It is shown that the addition of a register-memory addressing mode can target these "hot-spots" and provide power savings. Two different implementation options are considered and the power-performance trade-offs are evaluated. The reduction in performance is cushioned by the reduced instruction count and it is anticipated that the overall impact on the total execution time of programs will be acceptable in low power application domains.
{"title":"An extended addressing mode for low power","authors":"Atul Kalambur, M. J. Irwin","doi":"10.1145/263272.263336","DOIUrl":"https://doi.org/10.1145/263272.263336","url":null,"abstract":"This paper demonstrates the feasibility of a register-memory addressing mode in microprocessors targeted for low power applications. Using a high level power profiling tool that performs software energy evaluation, the major sources of power dissipation in a typical RISC processor are identified. It is shown that the addition of a register-memory addressing mode can target these \"hot-spots\" and provide power savings. Two different implementation options are considered and the power-performance trade-offs are evaluated. The reduction in performance is cushioned by the reduced instruction count and it is anticipated that the overall impact on the total execution time of programs will be acceptable in low power application domains.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"332 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115974569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
New measures of peak power in the context of sequential circuits are proposed. This paper presents an automatic procedure to obtain very good lower bounds on these measures as well as the actual input vectors that attain such bounds. The initial state of the circuit is an important factor in determining the amount of switching activity in sequential circuits and is taken into account. A peak power estimator tool K2 was developed using genetic techniques. Experiments show that vector sequences generated by K2 give much more accurate estimates for peak power dissipation than the estimates made from randomly generated sequences.
{"title":"K2: an estimator for peak sustainable power of VLSI circuits","authors":"M. Hsiao, E. Rudnick, J. Patel","doi":"10.1145/263272.263321","DOIUrl":"https://doi.org/10.1145/263272.263321","url":null,"abstract":"New measures of peak power in the context of sequential circuits are proposed. This paper presents an automatic procedure to obtain very good lower bounds on these measures as well as the actual input vectors that attain such bounds. The initial state of the circuit is an important factor in determining the amount of switching activity in sequential circuits and is taken into account. A peak power estimator tool K2 was developed using genetic techniques. Experiments show that vector sequences generated by K2 give much more accurate estimates for peak power dissipation than the estimates made from randomly generated sequences.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131403620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present an algorithm that restructures the state transition graph (STG) of a sequential circuit so as to reduce power dissipation. The STG is modified without changing the behavior of the circuit, by exploiting state equivalence. Rather than aiming primarily at reducing the number of states, our algorithm redirects transitions so that the new destination states are equivalent to the original ones, while the average activity of the circuit is decreased. The impact on area is also estimated to increase the accuracy of the power analysis. The STG and all other major data structures are stored as decision diagrams, and the algorithm does not enumerate explicitly the states or the transitions (i.e., it is symbolic.) Therefore, it can deal with circuits that have millions of states. Once the STG has been restructured we apply symbolic factoring algorithms, based on zero-suppressed BDDs, to convert the optimized graph into a multilevel circuit. We derive an efficient circuit from the BDDs of the STG by incorporating power constraints in the symbolic factoring algorithms.
{"title":"A symbolic algorithm for low power sequential synthesis","authors":"B. Kumthekar, In-Ho Moon, F. Somenzi","doi":"10.1145/263272.263283","DOIUrl":"https://doi.org/10.1145/263272.263283","url":null,"abstract":"We present an algorithm that restructures the state transition graph (STG) of a sequential circuit so as to reduce power dissipation. The STG is modified without changing the behavior of the circuit, by exploiting state equivalence. Rather than aiming primarily at reducing the number of states, our algorithm redirects transitions so that the new destination states are equivalent to the original ones, while the average activity of the circuit is decreased. The impact on area is also estimated to increase the accuracy of the power analysis. The STG and all other major data structures are stored as decision diagrams, and the algorithm does not enumerate explicitly the states or the transitions (i.e., it is symbolic.) Therefore, it can deal with circuits that have millions of states. Once the STG has been restructured we apply symbolic factoring algorithms, based on zero-suppressed BDDs, to convert the optimized graph into a multilevel circuit. We derive an efficient circuit from the BDDs of the STG by incorporating power constraints in the symbolic factoring algorithms.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124969021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Mehta, R. Owens, M. J. Irwin, Rita Yu Chen, Debashree Ghosh
The energy consumption of a system depends upon the hardware and software component of a system. Since it is the software which drives the hardware in most systems, decisions taken during software design has significant impact on the energy consumption of the processor. The paper focuses on decreasing energy consumption of a processor using software techniques. A novel compiler technique is proposed which reduces energy consumption by proper register labeling during the compilation phase. The idea behind this technique is to reduce the energy of the processor by reducing the energy of the instruction register (also the instruction data bus) and the register file decoder by encoding the register labels such that the sum of the switching costs between all the register labels in the transition graph is minimized. There is no hardware penalty since this is purely a compiler optimization. Results on benchmarks show that the energy consumption of the DLX processor can be reduced by 9.82% (maximum) and 4.25% (average) (as measured by DLX energy simulator). In addition several compiler techniques such as loop unrolling, software pipelining, recursion elimination and of effects of different algorithms on power and energy consumption are studied. This evaluation methodology is useful for computer architects to evaluate energy improvements of their hardware, compiler writers to evaluate energy of the compiled code and program writers to evaluate energy of data structures and algorithms.
{"title":"Techniques for low energy software","authors":"H. Mehta, R. Owens, M. J. Irwin, Rita Yu Chen, Debashree Ghosh","doi":"10.1145/263272.263286","DOIUrl":"https://doi.org/10.1145/263272.263286","url":null,"abstract":"The energy consumption of a system depends upon the hardware and software component of a system. Since it is the software which drives the hardware in most systems, decisions taken during software design has significant impact on the energy consumption of the processor. The paper focuses on decreasing energy consumption of a processor using software techniques. A novel compiler technique is proposed which reduces energy consumption by proper register labeling during the compilation phase. The idea behind this technique is to reduce the energy of the processor by reducing the energy of the instruction register (also the instruction data bus) and the register file decoder by encoding the register labels such that the sum of the switching costs between all the register labels in the transition graph is minimized. There is no hardware penalty since this is purely a compiler optimization. Results on benchmarks show that the energy consumption of the DLX processor can be reduced by 9.82% (maximum) and 4.25% (average) (as measured by DLX energy simulator). In addition several compiler techniques such as loop unrolling, software pipelining, recursion elimination and of effects of different algorithms on power and energy consumption are studied. This evaluation methodology is useful for computer architects to evaluate energy improvements of their hardware, compiler writers to evaluate energy of the compiled code and program writers to evaluate energy of data structures and algorithms.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"34 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120819376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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