The leakage current due to the parasitic PN junction diodes in SOI DTMOS (Dynamic threshold voltage MOSFET) inverter is reported. The additional power dissipation in DTMOS inverter due to the diodes is quantified through an analytical model and verified by MEDICI simulation. Power dissipation between conventional SOI CMOS and SOI DTMOS inverters is compared.
报道了SOI动态阈值电压MOSFET (Dynamic threshold voltage MOSFET)逆变器中寄生PN结二极管的漏电流。通过分析模型量化了二极管在DTMOS逆变器中的附加功耗，并通过MEDICI仿真进行了验证。比较了传统SOI CMOS和SOI DTMOS逆变器的功耗。
{"title":"On the power dissipation in dynamic threshold silicon-on-insulator CMOS inverter","authors":"W. Jin, Philip C. H. Chan, M. Chan","doi":"10.1109/LPE.1997.621292","DOIUrl":"https://doi.org/10.1109/LPE.1997.621292","url":null,"abstract":"The leakage current due to the parasitic PN junction diodes in SOI DTMOS (Dynamic threshold voltage MOSFET) inverter is reported. The additional power dissipation in DTMOS inverter due to the diodes is quantified through an analytical model and verified by MEDICI simulation. Power dissipation between conventional SOI CMOS and SOI DTMOS inverters is compared.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128706571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A low-power H.263 video codec core dedicated to low bitrate visual communication is described. A number of sophisticated architectures have been devised by attempting not only to minimize the total chip area but also to reduce the power consumption to such an extent that the operation frequency can be slowed down to 15 MHz. As a result, the whole encoding and decoding facilities of an H.263 video codec core have been integrated in the die area of 6.54 mm/sup 2/ by means of a 0.35 /spl mu/m CMOS technology, with the dissipation of 146.60 mW from a single 3.3 V supply.
{"title":"Low-power H.263 video codec dedicated to mobile computing","authors":"M. H. Miki, G. Fujita, T. Onoye, I. Shirakawa","doi":"10.1145/263272.263288","DOIUrl":"https://doi.org/10.1145/263272.263288","url":null,"abstract":"A low-power H.263 video codec core dedicated to low bitrate visual communication is described. A number of sophisticated architectures have been devised by attempting not only to minimize the total chip area but also to reduce the power consumption to such an extent that the operation frequency can be slowed down to 15 MHz. As a result, the whole encoding and decoding facilities of an H.263 video codec core have been integrated in the die area of 6.54 mm/sup 2/ by means of a 0.35 /spl mu/m CMOS technology, with the dissipation of 146.60 mW from a single 3.3 V supply.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117328799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We describe a method of polynomial simulation to calculate switching activities in a general-delay combinational logic circuit. This method is a generalization of the exact signal probability evaluation method due to Parker and McCluskey, which as been extended to handle temporal correlation and arbitrary transport delays. Our method is parameterized by a single parameter l, which determines the speed-accuracy tradeoff. l indicates the depth in terms of logic levels over which spatial signal correlation is taken into account. This is done by only taking into account reconvergent paths whose length is at most l. The rationale is that ignoring spatial correlation for signals that reconverge after many levels of logic introduces negligible error. We present results that show that the error in the switching activity and power estimates is very small even for small values of l. In fact, for most of the examples we tried, power estimates with l=1 are within 5% of the exact. However, this error can be higher than 20% for some examples, More robust estimates are obtained with l=2, providing a good compromise between speed and accuracy.
{"title":"Switching activity estimation using limited depth reconvergent path analysis","authors":"José C. Costa, J. Monteiro, S. Devadas","doi":"10.1145/263272.263323","DOIUrl":"https://doi.org/10.1145/263272.263323","url":null,"abstract":"We describe a method of polynomial simulation to calculate switching activities in a general-delay combinational logic circuit. This method is a generalization of the exact signal probability evaluation method due to Parker and McCluskey, which as been extended to handle temporal correlation and arbitrary transport delays. Our method is parameterized by a single parameter l, which determines the speed-accuracy tradeoff. l indicates the depth in terms of logic levels over which spatial signal correlation is taken into account. This is done by only taking into account reconvergent paths whose length is at most l. The rationale is that ignoring spatial correlation for signals that reconverge after many levels of logic introduces negligible error. We present results that show that the error in the switching activity and power estimates is very small even for small values of l. In fact, for most of the examples we tried, power estimates with l=1 are within 5% of the exact. However, this error can be higher than 20% for some examples, More robust estimates are obtained with l=2, providing a good compromise between speed and accuracy.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115692697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power consumption is very critical for portable video applications such as portable video-phone. Motion estimation in the video encoder requires huge amount of computation and hence consumes the largest portion of power. In this paper we propose a novel method of reducing power consumption of the motion estimation by adaptively changing the pixel resolution during the computation of the motion vector. The pixel resolution is changed by masking or truncating the LSBs of the pixel data which is governed by an adaptive mechanism. Experimental results show that on average more than 4 bits can be truncated without affecting the picture quality. This results in an average 70% reduction in power consumption.
{"title":"Low power motion estimation design using adaptive pixel truncation","authors":"Zhongli He, Kai-Keung Chan, C. Tsui, M. Liou","doi":"10.1109/LPE.1997.621273","DOIUrl":"https://doi.org/10.1109/LPE.1997.621273","url":null,"abstract":"Power consumption is very critical for portable video applications such as portable video-phone. Motion estimation in the video encoder requires huge amount of computation and hence consumes the largest portion of power. In this paper we propose a novel method of reducing power consumption of the motion estimation by adaptively changing the pixel resolution during the computation of the motion vector. The pixel resolution is changed by masking or truncating the LSBs of the pixel data which is governed by an adaptive mechanism. Experimental results show that on average more than 4 bits can be truncated without affecting the picture quality. This results in an average 70% reduction in power consumption.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"2011 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131872219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power dissipation can be addressed at three different levels: system, architecture, and circuit. The system has to be designed to allow for efficient paging to allow the phone to sleep for long periods, and the access scheme and modulation method have a large impact on circuit performance. A proper architecture and circuit partitioning has to be chosen: off-chip devices offer lower current consumption, but signal routing may require high power levels. At the circuit level, optimized supply voltages and power-down modes are important for digital circuits. Dynamic-bias analog circuits may adapt to the signal and interference situation.
{"title":"Minimizing power dissipation of cellular phones","authors":"S. Mattisson","doi":"10.1145/263272.263280","DOIUrl":"https://doi.org/10.1145/263272.263280","url":null,"abstract":"Power dissipation can be addressed at three different levels: system, architecture, and circuit. The system has to be designed to allow for efficient paging to allow the phone to sleep for long periods, and the access scheme and modulation method have a large impact on circuit performance. A proper architecture and circuit partitioning has to be chosen: off-chip devices offer lower current consumption, but signal routing may require high power levels. At the circuit level, optimized supply voltages and power-down modes are important for digital circuits. Dynamic-bias analog circuits may adapt to the signal and interference situation.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"2020 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121060804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Girard, C. Landrault, S. Pravossoudovitch, D. Séverac
With the advent of portable and high density microelectronic devices, the power dissipation of VLSI circuits is becoming a critical concern. In this paper we propose a post-mapping technique that can reduce the power dissipation by performing gate resizing. This technique consists of replacing some gates of the circuit with devices in a complete cell library having smaller area and, therefore, smaller gate capacitance with lower power consumption. The slack time of each gate in the circuit is first computed to determine the set of gates that can be down-sized. A global optimization procedure based on integer linear programming and the simplex method is then applied to determine the best overall gate resizing solution. Experimental results on benchmark circuits have shown a power reduction in the range from 2.8 to 27.9% compared to circuits without resizing. The most relevant features of our technique are that it is applicable to large digital circuits and gives an optimal resizing solution in a short computation time (no more than 15.8 seconds).
{"title":"A gate resizing technique for high reduction in power consumption","authors":"P. Girard, C. Landrault, S. Pravossoudovitch, D. Séverac","doi":"10.1145/263272.263352","DOIUrl":"https://doi.org/10.1145/263272.263352","url":null,"abstract":"With the advent of portable and high density microelectronic devices, the power dissipation of VLSI circuits is becoming a critical concern. In this paper we propose a post-mapping technique that can reduce the power dissipation by performing gate resizing. This technique consists of replacing some gates of the circuit with devices in a complete cell library having smaller area and, therefore, smaller gate capacitance with lower power consumption. The slack time of each gate in the circuit is first computed to determine the set of gates that can be down-sized. A global optimization procedure based on integer linear programming and the simplex method is then applied to determine the best overall gate resizing solution. Experimental results on benchmark circuits have shown a power reduction in the range from 2.8 to 27.9% compared to circuits without resizing. The most relevant features of our technique are that it is applicable to large digital circuits and gives an optimal resizing solution in a short computation time (no more than 15.8 seconds).","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129919702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we note and analyze a key trade-off: as the complexity of caches increases (higher set-associativity, larger block size, and larger overall size), the power consumed by a cache access increases. However, because the hit rate also increases, the number of main memory accesses decreases and thus the power consumed by a memory access decreases. Recent papers which consider the power consumption of caches tend to ignore hit rates. This is unfortunate, because it is undesirable to have energy-efficient caches which are also very slow. Hit rates also play a key role in truly evaluating the energy efficiency of a cache, because low hit rates lead to more frequent main memory accesses which consume more power than cache accesses.
{"title":"Analysis of power consumption in memory hierarchies","authors":"Patrick Hicks, Matthew Walnock, R. Owens","doi":"10.1145/263272.263342","DOIUrl":"https://doi.org/10.1145/263272.263342","url":null,"abstract":"In this paper, we note and analyze a key trade-off: as the complexity of caches increases (higher set-associativity, larger block size, and larger overall size), the power consumed by a cache access increases. However, because the hit rate also increases, the number of main memory accesses decreases and thus the power consumed by a memory access decreases. Recent papers which consider the power consumption of caches tend to ignore hit rates. This is unfortunate, because it is undesirable to have energy-efficient caches which are also very slow. Hit rates also play a key role in truly evaluating the energy efficiency of a cache, because low hit rates lead to more frequent main memory accesses which consume more power than cache accesses.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130745525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We suggest a new technique to reduce energy consumption in the processor datapath without sacrificing performance by exploiting operand value locality at run time. Data locality is one of the major characteristics of video streams as well as other commonly used applications. We use a cache-like scheme to store a selective history of computation results, and the resultant re-use leads to power savings. The cache is indexed by the operands. Based on our model, an 8 to 128 entry execution cache reduces power consumption by 20% to 60%.
{"title":"Low power data processing by elimination of redundant computations","authors":"Mir Azam, P. Franzon, Wentai Liu","doi":"10.1145/263272.263348","DOIUrl":"https://doi.org/10.1145/263272.263348","url":null,"abstract":"We suggest a new technique to reduce energy consumption in the processor datapath without sacrificing performance by exploiting operand value locality at run time. Data locality is one of the major characteristics of video streams as well as other commonly used applications. We use a cache-like scheme to store a selective history of computation results, and the resultant re-use leads to power savings. The cache is indexed by the operands. Based on our model, an 8 to 128 entry execution cache reduces power consumption by 20% to 60%.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132370875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A digital to analog converter has been developed using switched capacitors as the basic DAC elements. The use of switching capacitors provides excellent matching without sacrificing die area, and allows for very low-power operation. However, the architecture provides significant challenges when used in a continuous-time application requiring a "smooth" output. A realization of this architecture in a standard 0.6 /spl mu/m CMOS process achieved 10 bits of linearity while consuming less than 200 /spl mu/A of current.
{"title":"A capacitor-based D/A converter with continuous time output for low-power applications","authors":"L. Lynn, P. Ferguson","doi":"10.1145/263272.263304","DOIUrl":"https://doi.org/10.1145/263272.263304","url":null,"abstract":"A digital to analog converter has been developed using switched capacitors as the basic DAC elements. The use of switching capacitors provides excellent matching without sacrificing die area, and allows for very low-power operation. However, the architecture provides significant challenges when used in a continuous-time application requiring a \"smooth\" output. A realization of this architecture in a standard 0.6 /spl mu/m CMOS process achieved 10 bits of linearity while consuming less than 200 /spl mu/A of current.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114143081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
U. Narayanan, H. Leong, Ki-Seok Chung, Chien-Liang Liu
The advent of portable digital devices such as lap-top personal computers has made low power circuit design an increasingly important research area. Recently, low power decomposition for simple logic gates such as AND and OR has been extensively researched. However, the problem of MUX decomposition to minimize power dissipation has not been addressed. In this paper, we study the problem of low power multiplexer (MUX) decomposition. MUX decomposition is the procedure of transforming an n-to-one MUX into an equivalent tree of two-to-one MUXes. We propose a formulation for the minimum power MUX decomposition problem based on the common CMOS pass transistor implementation of a MUX. Given the occurrence probabilities of the data signals and their on probabilities, we analyze the power dissipation of OUT MUX implementation and give a general method for computing the power dissipation of a MUX tree decomposition. We then present several algorithms which efficiently generate minimum power MUX decompositions. We demonstrate the effectiveness of our algorithms with experimental results.
{"title":"Low power multiplexer decomposition","authors":"U. Narayanan, H. Leong, Ki-Seok Chung, Chien-Liang Liu","doi":"10.1145/263272.263350","DOIUrl":"https://doi.org/10.1145/263272.263350","url":null,"abstract":"The advent of portable digital devices such as lap-top personal computers has made low power circuit design an increasingly important research area. Recently, low power decomposition for simple logic gates such as AND and OR has been extensively researched. However, the problem of MUX decomposition to minimize power dissipation has not been addressed. In this paper, we study the problem of low power multiplexer (MUX) decomposition. MUX decomposition is the procedure of transforming an n-to-one MUX into an equivalent tree of two-to-one MUXes. We propose a formulation for the minimum power MUX decomposition problem based on the common CMOS pass transistor implementation of a MUX. Given the occurrence probabilities of the data signals and their on probabilities, we analyze the power dissipation of OUT MUX implementation and give a general method for computing the power dissipation of a MUX tree decomposition. We then present several algorithms which efficiently generate minimum power MUX decompositions. We demonstrate the effectiveness of our algorithms with experimental results.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132447554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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