Energy considerations are at the heart of important paradigm shifts in next-generation designs, especially in systems-on-a-chip era. Voltage might very well become a variable design parameter. Hybrid architectures mixing a variety of computational models are bound to be integrated on a single die. Exploiting the opportunities offered by these architectural innovations requires a well-thought out design methodology, combining high-level prediction and analysis tools with partitioning, optimization and mapping techniques. The paper presents a plausible composition of such a design environment.
{"title":"System-level power estimation and optimization-challenges and perspectives","authors":"J. Rabaey","doi":"10.1109/LPE.1997.621270","DOIUrl":"https://doi.org/10.1109/LPE.1997.621270","url":null,"abstract":"Energy considerations are at the heart of important paradigm shifts in next-generation designs, especially in systems-on-a-chip era. Voltage might very well become a variable design parameter. Hybrid architectures mixing a variety of computational models are bound to be integrated on a single die. Exploiting the opportunities offered by these architectural innovations requires a well-thought out design methodology, combining high-level prediction and analysis tools with partitioning, optimization and mapping techniques. The paper presents a plausible composition of such a design environment.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133167906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present detailed analytical models for estimating the energy dissipation in conventional caches as well as low energy cache architectures. The analytical models use the run time statistics such as hit/miss counts, fraction of read/write requests and assume stochastical distributions for signal values. These models are validated by comparing the power estimated using these models against the power estimated using a detailed simulator called CAPE (CAache Power Estimator). The analytical models for conventional caches are found to be accurate to within 2% error. However, these analytical models over-predict the dissipations of low-power caches by as much as 30%. The inaccuracies can be attributed to correlated signal values and locality of reference, both of which are exploited in making some cache organizations energy efficient.
我们提出了详细的分析模型来估计传统缓存和低能量缓存架构的能量耗散。分析模型使用运行时统计数据，如命中/未命中计数、读/写请求的比例，并假设信号值的随机分布。通过比较使用这些模型估计的功率与使用称为CAPE (CAache power Estimator)的详细模拟器估计的功率来验证这些模型。结果表明，常规贮藏物的分析模型误差在2%以内。然而，这些分析模型高估了低功耗缓存的耗散高达30%。不准确性可归因于相关信号值和参考的局部性，这两者都被用于使一些缓存组织节能。
{"title":"Analytical energy dissipation models for low power caches","authors":"M. Kamble, K. Ghose","doi":"10.1109/LPE.1997.621264","DOIUrl":"https://doi.org/10.1109/LPE.1997.621264","url":null,"abstract":"We present detailed analytical models for estimating the energy dissipation in conventional caches as well as low energy cache architectures. The analytical models use the run time statistics such as hit/miss counts, fraction of read/write requests and assume stochastical distributions for signal values. These models are validated by comparing the power estimated using these models against the power estimated using a detailed simulator called CAPE (CAache Power Estimator). The analytical models for conventional caches are found to be accurate to within 2% error. However, these analytical models over-predict the dissipations of low-power caches by as much as 30%. The inaccuracies can be attributed to correlated signal values and locality of reference, both of which are exploited in making some cache organizations energy efficient.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"20 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127527101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We have shown that by introducing a triangular window in the traditional /spl Delta/-/spl Sigma/ counting FDC, /spl Delta/-/spl Sigma/ noise-shaping and decimation results. A simple way to implement the windowing function is by using a double module counter or a sinc/sup 2/ decimator. By in this way using a /spl Delta/-/spl Sigma/ decimator as a /spl Delta/-/spl Sigma/ counting FDC a higher digital resolution can be achieved than by using a standard count-and-dump FDC as the quantization error is noise-shaped.
{"title":"/spl Delta/-/spl Sigma/ frequency-to-time conversion by triangularly weighted ZC counter","authors":"M. Høvin, S. Kiaei, T. Lande","doi":"10.1109/lpe.1997.621233","DOIUrl":"https://doi.org/10.1109/lpe.1997.621233","url":null,"abstract":"We have shown that by introducing a triangular window in the traditional /spl Delta/-/spl Sigma/ counting FDC, /spl Delta/-/spl Sigma/ noise-shaping and decimation results. A simple way to implement the windowing function is by using a double module counter or a sinc/sup 2/ decimator. By in this way using a /spl Delta/-/spl Sigma/ decimator as a /spl Delta/-/spl Sigma/ counting FDC a higher digital resolution can be achieved than by using a standard count-and-dump FDC as the quantization error is noise-shaped.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126416358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes some of the circuit level techniques for low-power CMOS designs. V/sub TH/ control circuits are necessary for achieving low-threshold voltage in high-speed low-voltage applications. As for the low swing circuit techniques, applications to a clock system, logic part, and I/O's are discussed.
{"title":"Low-power CMOS design through V/sub TH/ control and low-swing circuits","authors":"T. Sakurai, H. Kawaguchi, T. Kuroda","doi":"10.1109/LPE.1997.621198","DOIUrl":"https://doi.org/10.1109/LPE.1997.621198","url":null,"abstract":"This paper describes some of the circuit level techniques for low-power CMOS designs. V/sub TH/ control circuits are necessary for achieving low-threshold voltage in high-speed low-voltage applications. As for the low swing circuit techniques, applications to a clock system, logic part, and I/O's are discussed.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124116418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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