Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606337
A. Strandjord, W. B. Rogers, Y. Ida, R.R. DeVeillis, S. Shiau, E. Moyer, D. Scheck, P.E. Garron
Photosensitive benzocyclobutene (Photo-BCB) has been widely reported on for use as a dielectric material in multilayer packaging applications, including: MCMs, IO redistribution, and flat panel display. Photo-BCB has many properties which are highly attractive for these applications, including: a simple processing scheme which is compatible with existing IC manufacturing techniques, low level of ionics, low moisture uptake, low cure temperatures, rapid thermal curing, high optical transparency, high planarization level, high thermal stability, high solvent resistance, very low outgassing, and a low dielectric constant. Photo-BCB is also being actively evaluated for wafer-level applications such as stress-buffer and passivation. In this paper, we discuss the Photo-BCB properties and processing steps as they relate to these two applications. We also compare the manufacturing scheme based on a one mask process for memory die, to the steps in a two mask process for stress-buffer and passivation.
{"title":"Photosensitive benzocyclobutene for stress-buffer and passivation applications (one mask manufacturing process)","authors":"A. Strandjord, W. B. Rogers, Y. Ida, R.R. DeVeillis, S. Shiau, E. Moyer, D. Scheck, P.E. Garron","doi":"10.1109/ECTC.1997.606337","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606337","url":null,"abstract":"Photosensitive benzocyclobutene (Photo-BCB) has been widely reported on for use as a dielectric material in multilayer packaging applications, including: MCMs, IO redistribution, and flat panel display. Photo-BCB has many properties which are highly attractive for these applications, including: a simple processing scheme which is compatible with existing IC manufacturing techniques, low level of ionics, low moisture uptake, low cure temperatures, rapid thermal curing, high optical transparency, high planarization level, high thermal stability, high solvent resistance, very low outgassing, and a low dielectric constant. Photo-BCB is also being actively evaluated for wafer-level applications such as stress-buffer and passivation. In this paper, we discuss the Photo-BCB properties and processing steps as they relate to these two applications. We also compare the manufacturing scheme based on a one mask process for memory die, to the steps in a two mask process for stress-buffer and passivation.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115413423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606170
L. J. Norton, F. Carney, N. Choi, C. Chun, R. Denton, D. Diaz, J. Knapp, M. Meyering, C. Ngo, S. Planer, G. Raskin, E. Reyes, J. Sauvageau, D. Schwartz, S. G. Shook, J. Yoder, Y. Wen
Parallel fiber interconnects have received considerable attention recently due to the potential systems level advantages offered by optics. Designers of large computer systems and central office equipment are attracted by the advantages of size, EMI, electrical isolation and the performance at distances not achievable by traditional copper solutions. In spite of these advantages, designers do not want to pay a premium for optical solutions at comparable data rates and distance to copper. Therefore, it is critical to optical product implementation that there be a large added performance over copper for the same cost. OPTOBUS/sup TM/ I is a solution that addresses the tradeoffs between manufacturing cost and system design. It is a simple, low cost, 400 Mb/s 10-bit bidirectional optical data link for distances up to several hundred meters.
{"title":"OPTOBUS/sup TM/ I: a production parallel fiber optical interconnect","authors":"L. J. Norton, F. Carney, N. Choi, C. Chun, R. Denton, D. Diaz, J. Knapp, M. Meyering, C. Ngo, S. Planer, G. Raskin, E. Reyes, J. Sauvageau, D. Schwartz, S. G. Shook, J. Yoder, Y. Wen","doi":"10.1109/ECTC.1997.606170","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606170","url":null,"abstract":"Parallel fiber interconnects have received considerable attention recently due to the potential systems level advantages offered by optics. Designers of large computer systems and central office equipment are attracted by the advantages of size, EMI, electrical isolation and the performance at distances not achievable by traditional copper solutions. In spite of these advantages, designers do not want to pay a premium for optical solutions at comparable data rates and distance to copper. Therefore, it is critical to optical product implementation that there be a large added performance over copper for the same cost. OPTOBUS/sup TM/ I is a solution that addresses the tradeoffs between manufacturing cost and system design. It is a simple, low cost, 400 Mb/s 10-bit bidirectional optical data link for distances up to several hundred meters.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124061726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606297
Y. Hotta, A. Mochizuki, M. Sakamoto, M. Yoshioka, A. Prabhu, S. Akizuki
The characteristics demanded of the packages are being diversified; from the anti-popcorn package that was always the main problem in the past 10 years to improving on the package size towards a smaller and thinner size, for example CSP (Chip size package), other concerns being productivity, thermal management and environmental measures. We propose FPAC (Foil covered PACkage) as a packaging technology which can satisfy such requirements. We are also developing the production process and the material which makes this package. FPAC technology can be used to make the package of the thin type, with the high heat dissipation, and high humidity reliability. The process itself is easy with less amount of trash. We report on the current state about this development in this paper.
{"title":"New packaging system and materials for FPAC","authors":"Y. Hotta, A. Mochizuki, M. Sakamoto, M. Yoshioka, A. Prabhu, S. Akizuki","doi":"10.1109/ECTC.1997.606297","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606297","url":null,"abstract":"The characteristics demanded of the packages are being diversified; from the anti-popcorn package that was always the main problem in the past 10 years to improving on the package size towards a smaller and thinner size, for example CSP (Chip size package), other concerns being productivity, thermal management and environmental measures. We propose FPAC (Foil covered PACkage) as a packaging technology which can satisfy such requirements. We are also developing the production process and the material which makes this package. FPAC technology can be used to make the package of the thin type, with the high heat dissipation, and high humidity reliability. The process itself is easy with less amount of trash. We report on the current state about this development in this paper.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124236762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606214
A. Shibuya, I. Hazeyama, T. Shimoto, N. Takahashi, N. Senba, M. Kimura, Y. Shimada, H. Matsuzawa, F. Mori
A RISC (reduced instruction set computer) module, which contains secondary cache memories and is called an MCM for use in a high-performance workstation has been developed. The design consists of a D/L (deposited organic thin film on laminated printed-circuit board) base substrate, a glass-ceramic-based organic-thin-film multilayer build-up CSP (chip size package), and glass-ceramic 3-dimensional memory (3DM) modules. The characteristics of this newly developed MCM are as follows. The D/L base substrate has 179 I/O (input/output) pins and signal lines of 25-/spl mu/m width and 50-/spl mu/m pitch. The CSP carrier signal lines are as fine as those of the D/L, and the CSP carrier features 525 I/O pads and 80-/spl mu/m diameter chip bonding pads with 108-/spl mu/m pitch. The 3DM is almost the same size as a conventional single chip mold package; with the stacking of ten memory chips in the space of four 3DMs, the area required is roughly only that of four single chip packages.
{"title":"New MCM composed of D/L base substrate, high-density-wiring CSP and 3D memory modules","authors":"A. Shibuya, I. Hazeyama, T. Shimoto, N. Takahashi, N. Senba, M. Kimura, Y. Shimada, H. Matsuzawa, F. Mori","doi":"10.1109/ECTC.1997.606214","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606214","url":null,"abstract":"A RISC (reduced instruction set computer) module, which contains secondary cache memories and is called an MCM for use in a high-performance workstation has been developed. The design consists of a D/L (deposited organic thin film on laminated printed-circuit board) base substrate, a glass-ceramic-based organic-thin-film multilayer build-up CSP (chip size package), and glass-ceramic 3-dimensional memory (3DM) modules. The characteristics of this newly developed MCM are as follows. The D/L base substrate has 179 I/O (input/output) pins and signal lines of 25-/spl mu/m width and 50-/spl mu/m pitch. The CSP carrier signal lines are as fine as those of the D/L, and the CSP carrier features 525 I/O pads and 80-/spl mu/m diameter chip bonding pads with 108-/spl mu/m pitch. The 3DM is almost the same size as a conventional single chip mold package; with the stacking of ten memory chips in the space of four 3DMs, the area required is roughly only that of four single chip packages.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121794928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606229
Y. Joshi, M. Pecht, W. Nakayama
In the 1980's, University of Maryland faculty began teaching courses on electronic packaging and wrote the first book on this topic. As a result of two subsequent /spl epsi/ grants under the U.S. Government Technology Re-investment Program, the Computer-Aided Life-Cycle Engineering (CALCE) Electronic Packaging Research Center (EPRC), an academic center of the University of Maryland, today provides a cross-disciplinary undergraduate and graduate curriculum on Electronic Packaging and Reliability (EPAR). Offered through the Mechanical Engineering Department, students from all engineering disciplines including Electrical Engineering, Materials Science and Reliability Engineering enroll in the program. The success of the EPAR graduate program is evidenced by the respect it has gained from the electronics industry. All graduates of this program have been keenly sought after, and have enjoyed excellent job opportunities. In the era of dwindling enrollments in many graduate engineering programs, the EPAR program has seen a consistent growth. The instructional methodologies employed in this curriculum development effort are described and can serve as models for other multi-disciplinary programs.
{"title":"Electronic packaging and reliability education for the 21st century: the University of Maryland CALCE EPRC Program","authors":"Y. Joshi, M. Pecht, W. Nakayama","doi":"10.1109/ECTC.1997.606229","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606229","url":null,"abstract":"In the 1980's, University of Maryland faculty began teaching courses on electronic packaging and wrote the first book on this topic. As a result of two subsequent /spl epsi/ grants under the U.S. Government Technology Re-investment Program, the Computer-Aided Life-Cycle Engineering (CALCE) Electronic Packaging Research Center (EPRC), an academic center of the University of Maryland, today provides a cross-disciplinary undergraduate and graduate curriculum on Electronic Packaging and Reliability (EPAR). Offered through the Mechanical Engineering Department, students from all engineering disciplines including Electrical Engineering, Materials Science and Reliability Engineering enroll in the program. The success of the EPAR graduate program is evidenced by the respect it has gained from the electronics industry. All graduates of this program have been keenly sought after, and have enjoyed excellent job opportunities. In the era of dwindling enrollments in many graduate engineering programs, the EPAR program has seen a consistent growth. The instructional methodologies employed in this curriculum development effort are described and can serve as models for other multi-disciplinary programs.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"298 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123257099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606191
M. Amagai, H. Sano, T. Maeda, T. Imura, T. Saitoh
Memory chip scale package (MCSP) has been developed for center pad memory devices. The MCSP is classified into two designs, tapeless lead on chip (LOC) and flexible substrate, respectively. The MCSP with a tapeless LOC design consists of a polyimide-deposited chip which is bonded to a lead frame and then encapsulated with a molding compound. The MCSP made with a flexible substrate consists of a polyimide-deposited chip which is bonded to the flexible substrate with a thermoplastic polyimide and subsequently encapsulated with a liquid epoxy compound. Wire bonding technology was used for both of MCSPs. A 52 ball package are composed of solder balls (1.0 mm in diameter on a 1.27 mm pitch) attached to either the lead frame or the flexible substrate. The optimum material properties, the wafer fabrication and packaging process parameters, and the experimental and simulated reliability and performance results of the MCSPs are presented.
{"title":"Development of chip scale packages (CSP) for center pad devices","authors":"M. Amagai, H. Sano, T. Maeda, T. Imura, T. Saitoh","doi":"10.1109/ECTC.1997.606191","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606191","url":null,"abstract":"Memory chip scale package (MCSP) has been developed for center pad memory devices. The MCSP is classified into two designs, tapeless lead on chip (LOC) and flexible substrate, respectively. The MCSP with a tapeless LOC design consists of a polyimide-deposited chip which is bonded to a lead frame and then encapsulated with a molding compound. The MCSP made with a flexible substrate consists of a polyimide-deposited chip which is bonded to the flexible substrate with a thermoplastic polyimide and subsequently encapsulated with a liquid epoxy compound. Wire bonding technology was used for both of MCSPs. A 52 ball package are composed of solder balls (1.0 mm in diameter on a 1.27 mm pitch) attached to either the lead frame or the flexible substrate. The optimum material properties, the wafer fabrication and packaging process parameters, and the experimental and simulated reliability and performance results of the MCSPs are presented.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123670404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606309
F. Hua, Z. Mei, H. Holder, J. Glazer
Low adhesion strength of Sn-Pb solder joints to Alloy 42, a widely used material for electronic component lead-frame, is a well known but little studied problem in the electronic packaging and assembly industry. In this study, the adhesion strength of two lead-frame materials, Cu and Alloy 42, soldered with 63Sn-37Pb were compared in push-off tests. It was found that the adhesion to Alloy 42 is weaker than to Cu. Higher reflow temperature and longer reflow time strengthen the adhesion, but the effect is not significant in the temperature and time ranges which are practical for electronic assembly. The failure analysis indicates that the solder joints on Cu failed within the solder, while the solder joints on Alloy 42 failed by a clean separation between solder and the lead. Similarly, poor adhesion to Alloy 42 was also observed with 43Pb-43Sn-14Bi, and the problem was more severe. The push-off strength of the 43Pb-43Sn-14Bi joints on Alloy 42 leads was only 50% of 63Sn-37Pb on Cu leads.
{"title":"Adhesion strength of solder joints to Alloy 42 component leads","authors":"F. Hua, Z. Mei, H. Holder, J. Glazer","doi":"10.1109/ECTC.1997.606309","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606309","url":null,"abstract":"Low adhesion strength of Sn-Pb solder joints to Alloy 42, a widely used material for electronic component lead-frame, is a well known but little studied problem in the electronic packaging and assembly industry. In this study, the adhesion strength of two lead-frame materials, Cu and Alloy 42, soldered with 63Sn-37Pb were compared in push-off tests. It was found that the adhesion to Alloy 42 is weaker than to Cu. Higher reflow temperature and longer reflow time strengthen the adhesion, but the effect is not significant in the temperature and time ranges which are practical for electronic assembly. The failure analysis indicates that the solder joints on Cu failed within the solder, while the solder joints on Alloy 42 failed by a clean separation between solder and the lead. Similarly, poor adhesion to Alloy 42 was also observed with 43Pb-43Sn-14Bi, and the problem was more severe. The push-off strength of the 43Pb-43Sn-14Bi joints on Alloy 42 leads was only 50% of 63Sn-37Pb on Cu leads.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129414500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606169
J. R. Broomall, H. Van Deusen
As data processing speeds increase, systems designers are continually bumping into the limitations of traditional wiring methods and become tempted to cross the barrier into fiber optics technology. Several techniques for increasing the useful range of copper based interconnects in both bandwidth and distance have been developed. These can lead to cost effective alternatives to implementing fiber optic solutions, especially for distances up to 100 meters. Critical to maximizing the benefits of these techniques is to take a system approach which goes beyond just improving cable or connector design. This paper discusses the typical challenges facing interconnect designers along with potential solutions that can be generally applied to a variety of applications. Improvements in cabling technology are shown including reduced skew, tightened impedance control, higher density designs, multi-signal termination techniques and built-in equalization. Suitable connector types are also presented to evaluate compatibility and availability. System considerations such as parallel vs. serial, driver and receiver types, selection of characteristic impedance and encoding schemes are included for further background on design issues. All of this information is presented in light of typical concerns such as signal fidelity, cable size, EMC, and cost. Tradeoffs between copper and fiber optic based systems are presented based on current and expected future costs. As the need for a fiber optic link becomes more evident, a seamless migration approach is outlined which allows fiber optic links to be selectively installed on an as needed basis for longer distance runs.
{"title":"Extending the useful range of copper interconnects for high data rate signal transmission","authors":"J. R. Broomall, H. Van Deusen","doi":"10.1109/ECTC.1997.606169","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606169","url":null,"abstract":"As data processing speeds increase, systems designers are continually bumping into the limitations of traditional wiring methods and become tempted to cross the barrier into fiber optics technology. Several techniques for increasing the useful range of copper based interconnects in both bandwidth and distance have been developed. These can lead to cost effective alternatives to implementing fiber optic solutions, especially for distances up to 100 meters. Critical to maximizing the benefits of these techniques is to take a system approach which goes beyond just improving cable or connector design. This paper discusses the typical challenges facing interconnect designers along with potential solutions that can be generally applied to a variety of applications. Improvements in cabling technology are shown including reduced skew, tightened impedance control, higher density designs, multi-signal termination techniques and built-in equalization. Suitable connector types are also presented to evaluate compatibility and availability. System considerations such as parallel vs. serial, driver and receiver types, selection of characteristic impedance and encoding schemes are included for further background on design issues. All of this information is presented in light of typical concerns such as signal fidelity, cable size, EMC, and cost. Tradeoffs between copper and fiber optic based systems are presented based on current and expected future costs. As the need for a fiber optic link becomes more evident, a seamless migration approach is outlined which allows fiber optic links to be selectively installed on an as needed basis for longer distance runs.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130088882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606279
N.A. Gildersleeve, K. Collins
There has been a great upsurge in research and failure analysis on automotive interconnections over the past 10 years. Failures are often attributed to a combination of loss of normal force, fretting corrosion, general corrosion, overheating, plating degradation, and others. Much of the research effort has been to establish a reproducible link between material system and electrical performance reliability. Metal alloy producers and material platers have attempted to contribute to this effort by performing specific coupon studies which characterize the electrical performance of their products. Generally, these coupon studies do not address the critical differences between the performance of a flat coupon sample and a formed connector. Within the automotive industry, there are various performance tests applied to interconnection components which evaluate electrical performance results after simulated or accelerated service conditions. This paper describes the development of a test method which is capable of simulating the key performance characteristics of an automotive interconnection. Recommendations for future improvements are included. The goal of this development was to provide a testing system which evaluates the degradation of contact resistance in samples which closely represent formed components, without the encumbrance of complete component fabrication. The following criteria were selected as minimum test system requirements : Samples must be easily fabricated from the material systems of interest; The environment must provide for thermal cycling (Delta T=125/spl deg/C, min.); Provide for stress relaxation of a formed contact spring to manifest in the performance result; Provide for the motion required for fretting corrosion at the contact surface; The change in contact resistance with time must be measured at intervals close enough to identify critical phenomena; Samples must be easily retrieved and prepared for contact surface analysis after cycle testing is completed. Initial results comparing heavy hot tin coatings on both brass and copper beryllium show an extremely high difference in the rate of increase in contact resistance.
{"title":"Material coupon test method to simulate contact performance under automotive conditions","authors":"N.A. Gildersleeve, K. Collins","doi":"10.1109/ECTC.1997.606279","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606279","url":null,"abstract":"There has been a great upsurge in research and failure analysis on automotive interconnections over the past 10 years. Failures are often attributed to a combination of loss of normal force, fretting corrosion, general corrosion, overheating, plating degradation, and others. Much of the research effort has been to establish a reproducible link between material system and electrical performance reliability. Metal alloy producers and material platers have attempted to contribute to this effort by performing specific coupon studies which characterize the electrical performance of their products. Generally, these coupon studies do not address the critical differences between the performance of a flat coupon sample and a formed connector. Within the automotive industry, there are various performance tests applied to interconnection components which evaluate electrical performance results after simulated or accelerated service conditions. This paper describes the development of a test method which is capable of simulating the key performance characteristics of an automotive interconnection. Recommendations for future improvements are included. The goal of this development was to provide a testing system which evaluates the degradation of contact resistance in samples which closely represent formed components, without the encumbrance of complete component fabrication. The following criteria were selected as minimum test system requirements : Samples must be easily fabricated from the material systems of interest; The environment must provide for thermal cycling (Delta T=125/spl deg/C, min.); Provide for stress relaxation of a formed contact spring to manifest in the performance result; Provide for the motion required for fretting corrosion at the contact surface; The change in contact resistance with time must be measured at intervals close enough to identify critical phenomena; Samples must be easily retrieved and prepared for contact surface analysis after cycle testing is completed. Initial results comparing heavy hot tin coatings on both brass and copper beryllium show an extremely high difference in the rate of increase in contact resistance.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130308076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606272
R. Bonda, T. Fang, B. Hileman, D. Spigler, J. Stafford, G. Swan, G. Tam
Motorola SPS has developed an assembly process for a three-chip multichip module using a fluxless bonding technique. The substrate is a 25 mm/spl times/25 mm glass that containing two layers of electroplated metallization with vias connecting the two layers and dielectric layer separating them. A test substrate is designed to characterize the continuity and leakage of the assembled modules. One of the chips has two staggered rows of 384 total bumps on the periphery with 80 /spl mu/m pitch and 45 /spl mu/m bump size. The other two chips have three staggered rows, 222 bumps on each chip, 210 /spl mu/m pitch and 100 /spl mu/m bump size. The bump composition is Pb-Sn with low Sn content. All three chips are bonded to the substrate using a fluxless plasma process followed by reflow in a nitrogen furnace. A high precision robot is used for placement and tacking of the chips on the substrate. After the bonding, the chips are underfilled with a proprietary underfill epoxy, and tested for reliability. All the reliability criteria for the specific application of this module have been met. Physical design and assembly process of this multichip module will be presented.
{"title":"Development of fluxless flip chip bonding to a thin film multichip module substrate","authors":"R. Bonda, T. Fang, B. Hileman, D. Spigler, J. Stafford, G. Swan, G. Tam","doi":"10.1109/ECTC.1997.606272","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606272","url":null,"abstract":"Motorola SPS has developed an assembly process for a three-chip multichip module using a fluxless bonding technique. The substrate is a 25 mm/spl times/25 mm glass that containing two layers of electroplated metallization with vias connecting the two layers and dielectric layer separating them. A test substrate is designed to characterize the continuity and leakage of the assembled modules. One of the chips has two staggered rows of 384 total bumps on the periphery with 80 /spl mu/m pitch and 45 /spl mu/m bump size. The other two chips have three staggered rows, 222 bumps on each chip, 210 /spl mu/m pitch and 100 /spl mu/m bump size. The bump composition is Pb-Sn with low Sn content. All three chips are bonded to the substrate using a fluxless plasma process followed by reflow in a nitrogen furnace. A high precision robot is used for placement and tacking of the chips on the substrate. After the bonding, the chips are underfilled with a proprietary underfill epoxy, and tested for reliability. All the reliability criteria for the specific application of this module have been met. Physical design and assembly process of this multichip module will be presented.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125303648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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