Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606185
Z. Yang, X. A. Wang, J. Ewanich
Expanded from the thermal characteristics of single chip packages, a matrix form thermal characteristic for MCM and MCPs is introduced in this paper. The validity of this characteristic is investigated through a few most commonly used MCM, MCP assembly configurations and mounting boards. A detail discussion is made on the relationship between the thermal characteristic, /spl theta/ matrix and its thermal circuit representation. In addition, two techniques are introduced to extract the equivalent thermal network from a given /spl theta/ matrix or directly from numerical modeling. The extracted thermal network is also tested by numerical examples and has proved to be accurate enough for higher system level applications.
{"title":"The MCM/MCP thermal characteristic and its circuit representations","authors":"Z. Yang, X. A. Wang, J. Ewanich","doi":"10.1109/ECTC.1997.606185","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606185","url":null,"abstract":"Expanded from the thermal characteristics of single chip packages, a matrix form thermal characteristic for MCM and MCPs is introduced in this paper. The validity of this characteristic is investigated through a few most commonly used MCM, MCP assembly configurations and mounting boards. A detail discussion is made on the relationship between the thermal characteristic, /spl theta/ matrix and its thermal circuit representation. In addition, two techniques are introduced to extract the equivalent thermal network from a given /spl theta/ matrix or directly from numerical modeling. The extracted thermal network is also tested by numerical examples and has proved to be accurate enough for higher system level applications.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123360179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606268
J.C. Bolger
New resin and filler types now allow epoxy encapsulants to have higher filler loadings and lower expansion coefficients. Reducing encapsulant shrinkage in a wire bonded plastic package has the advantages of lower die stress and less warpage, but if shrinkage is too low, early corrosion failure may occur during humidity tests. To explain why, it has been proposed (1) that compression forces, due to encapsulant shrinkage, can prevent the water which is needed for corrosion from accumulating at the bond pad surface. The objective of this paper is to quantify this corrosion mechanism. The Nernst equation plus heat of adsorption data are used to predict that the minimum compression stress, normal to the bond pads, which is needed to prevent water accumulation and corrosion, should be at least 20 times the partial pressure of water vapor at the test temperature. For example, at 121/spl deg/C/30 psia, the compression stress from the encapsulant should be at least 600 psi. Shrinkage and expansion data, measured for 5 epoxy encapsulants and 7 epoxy and polyimide die attach adhesives, were used to calculate die stress for each adhesive-encapsulant combination. All 12 materials had low ionic extractables (C1/sup -/<20 ppm) but major differences had been found in failure times in pressure cooker tests. The corrosion results correlate with the calculated Z-axis stresses and support the prediction that the minimum stress should be /spl ges/20 P/sub w/. Die surface stresses depend on the adhesive, adhesive thickness, adhesive cure and die size as well as on the encapsulant.
{"title":"Optimization of shrinkage and expansion properties of epoxy encapsulants","authors":"J.C. Bolger","doi":"10.1109/ECTC.1997.606268","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606268","url":null,"abstract":"New resin and filler types now allow epoxy encapsulants to have higher filler loadings and lower expansion coefficients. Reducing encapsulant shrinkage in a wire bonded plastic package has the advantages of lower die stress and less warpage, but if shrinkage is too low, early corrosion failure may occur during humidity tests. To explain why, it has been proposed (1) that compression forces, due to encapsulant shrinkage, can prevent the water which is needed for corrosion from accumulating at the bond pad surface. The objective of this paper is to quantify this corrosion mechanism. The Nernst equation plus heat of adsorption data are used to predict that the minimum compression stress, normal to the bond pads, which is needed to prevent water accumulation and corrosion, should be at least 20 times the partial pressure of water vapor at the test temperature. For example, at 121/spl deg/C/30 psia, the compression stress from the encapsulant should be at least 600 psi. Shrinkage and expansion data, measured for 5 epoxy encapsulants and 7 epoxy and polyimide die attach adhesives, were used to calculate die stress for each adhesive-encapsulant combination. All 12 materials had low ionic extractables (C1/sup -/<20 ppm) but major differences had been found in failure times in pressure cooker tests. The corrosion results correlate with the calculated Z-axis stresses and support the prediction that the minimum stress should be /spl ges/20 P/sub w/. Die surface stresses depend on the adhesive, adhesive thickness, adhesive cure and die size as well as on the encapsulant.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125994228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606158
D. Peterson, J. Sweet, S. Burchett, A. Hsia
We report the first measurements of in-situ flip-chip assembly mechanical stresses using a CMOS piezoresistive test chip repatterned with a fine pitch full area array. A special printed circuit board substrate was designed at Sandia and fabricated by the Hadco Corp. The flip-chip solder attach (FCA) and underfill was performed by a SEMATECH member company. The measured incremental stresses produced by the underfill are reported and discussed for several underfill materials used in this experiment. A FEM of a one-quarter section of the square assembly has been developed to compare with the measured as-assembled and underfill die surface stresses. The initial model utilized linear elastic constitutive models for the Si, solder, underfill, and PC board components. Detailed comparisons between theory and experiment are presented and discussed.
{"title":"Stresses from flip-chip assembly and underfill; measurements with the ATC4.1 assembly test chip and analysis by finite element method","authors":"D. Peterson, J. Sweet, S. Burchett, A. Hsia","doi":"10.1109/ECTC.1997.606158","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606158","url":null,"abstract":"We report the first measurements of in-situ flip-chip assembly mechanical stresses using a CMOS piezoresistive test chip repatterned with a fine pitch full area array. A special printed circuit board substrate was designed at Sandia and fabricated by the Hadco Corp. The flip-chip solder attach (FCA) and underfill was performed by a SEMATECH member company. The measured incremental stresses produced by the underfill are reported and discussed for several underfill materials used in this experiment. A FEM of a one-quarter section of the square assembly has been developed to compare with the measured as-assembled and underfill die surface stresses. The initial model utilized linear elastic constitutive models for the Si, solder, underfill, and PC board components. Detailed comparisons between theory and experiment are presented and discussed.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"2022 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121787758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606246
N. Chang, J C Lee, Barford, B. Troyanovsky
The capability of time domain simulation with frequency domain data exists in some time-domain simulators, but the computations can be time-consuming. We decrease this computational burden by exploiting S-parameter fitter and fast recursive convolution methods. With recursive convolution the frequencies at which the S-parameters are sampled may be spaced in any way. For example, a logarithmic frequency spacing allows S-parameters to be sampled over a broader band without increasing the number of frequencies measured. We use two different system identification techniques for extracting the closed-form equations describing measured or simulated S-parameter data. Lumped parameter systems are approximated as a rational polynomial modulated by a complex exponential. Distributed parameter systems are approximated by the sum of complex exponentials. The recursive convolution engine handles both forms. The HP SPICE circuit simulator has been extended to allow fast, recursive convolution methods to be employed for transient analysis. The resulting simulator is called SSpice v2. Significant speed-up in the simulation of several circuits have been achieved using this new technique compared to both the traditional approach in SPICE and our previous direct-convolution-based approach in SSpice v1. In this paper, we present the algorithms and applications of the simulator. Three applications are demonstrated in the paper which are MR head flex line modeling, chip-to-chip signal modeling on MCM, and on-chip inductor modeling.
{"title":"Fast time domain simulation in SPICE with frequency domain data","authors":"N. Chang, J C Lee, Barford, B. Troyanovsky","doi":"10.1109/ECTC.1997.606246","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606246","url":null,"abstract":"The capability of time domain simulation with frequency domain data exists in some time-domain simulators, but the computations can be time-consuming. We decrease this computational burden by exploiting S-parameter fitter and fast recursive convolution methods. With recursive convolution the frequencies at which the S-parameters are sampled may be spaced in any way. For example, a logarithmic frequency spacing allows S-parameters to be sampled over a broader band without increasing the number of frequencies measured. We use two different system identification techniques for extracting the closed-form equations describing measured or simulated S-parameter data. Lumped parameter systems are approximated as a rational polynomial modulated by a complex exponential. Distributed parameter systems are approximated by the sum of complex exponentials. The recursive convolution engine handles both forms. The HP SPICE circuit simulator has been extended to allow fast, recursive convolution methods to be employed for transient analysis. The resulting simulator is called SSpice v2. Significant speed-up in the simulation of several circuits have been achieved using this new technique compared to both the traditional approach in SPICE and our previous direct-convolution-based approach in SSpice v1. In this paper, we present the algorithms and applications of the simulator. Three applications are demonstrated in the paper which are MR head flex line modeling, chip-to-chip signal modeling on MCM, and on-chip inductor modeling.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122044860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606274
R. Lachance, H. Lavoie, A. Montanari
Temperature, humidity and voltage (bias) represent a well-known combination of stress parameters that activate failure mechanisms and decrease reliability of microelectronic packages. The following work focuses mainly on the impact of such mechanisms on a high volume flip chip package at IBM. This package consists of a silicon flip chip on alumina with C4 enhancement underfill and a package overcoat The test conditions for HAST were 130 C, 85%RH and 5 V, while 85 C, 85% RH and 5 V were used for THB. In order to have a sampling most representative of manufacturing conditions, two IBM manufacturing sites were selected to both build and stress parts. Parts were selected from respective sites at a rate of 6 parts per week over a 6-month period. Results showed that the underfill and overcoating environment postpones the metal migration mechanism far beyond the product life cycle. The study also revealed that the Cr/Cu/Cr conductor lines and the Pb/Sn C4 structures were the regions most susceptible to migration. The acceleration factor of copper conductor migration between HAST and THB was 86 based on a visual inspection at 100X, yielding an activation energy (Ea) of 1.23 eV using the Arrhenius model. It was not possible to calculate the acceleration factor involving Pb/Sn sites, but electrical failures were found in HAST. The failure mechanism was Pb migration between C4 balls and the nearest Cr/Cu/Cr conductor line. It has also been identified that a C4 having a large void will fail earlier due to the bigger diameter. Based on a recent study (S. Peck), the average Ea in the microelectronics packaging industry has evolved from 0.79 eV some 10 years ago to about 0.9 eV today. In light of this, an Ea of 1.23 ev (copper migration) for an application with 50 microns cathode-to-anode is deemed very acceptable.
{"title":"Corrosion/migration study of flip chip underfill and ceramic overcoating","authors":"R. Lachance, H. Lavoie, A. Montanari","doi":"10.1109/ECTC.1997.606274","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606274","url":null,"abstract":"Temperature, humidity and voltage (bias) represent a well-known combination of stress parameters that activate failure mechanisms and decrease reliability of microelectronic packages. The following work focuses mainly on the impact of such mechanisms on a high volume flip chip package at IBM. This package consists of a silicon flip chip on alumina with C4 enhancement underfill and a package overcoat The test conditions for HAST were 130 C, 85%RH and 5 V, while 85 C, 85% RH and 5 V were used for THB. In order to have a sampling most representative of manufacturing conditions, two IBM manufacturing sites were selected to both build and stress parts. Parts were selected from respective sites at a rate of 6 parts per week over a 6-month period. Results showed that the underfill and overcoating environment postpones the metal migration mechanism far beyond the product life cycle. The study also revealed that the Cr/Cu/Cr conductor lines and the Pb/Sn C4 structures were the regions most susceptible to migration. The acceleration factor of copper conductor migration between HAST and THB was 86 based on a visual inspection at 100X, yielding an activation energy (Ea) of 1.23 eV using the Arrhenius model. It was not possible to calculate the acceleration factor involving Pb/Sn sites, but electrical failures were found in HAST. The failure mechanism was Pb migration between C4 balls and the nearest Cr/Cu/Cr conductor line. It has also been identified that a C4 having a large void will fail earlier due to the bigger diameter. Based on a recent study (S. Peck), the average Ea in the microelectronics packaging industry has evolved from 0.79 eV some 10 years ago to about 0.9 eV today. In light of this, an Ea of 1.23 ev (copper migration) for an application with 50 microns cathode-to-anode is deemed very acceptable.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126277898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606153
A. Iida, Y. Kizaki, Y. Fukuda, M. Mori
The authors have developed a new repairable chip-on-glass (COG) bonding technique for liquid crystal display (LCD) panels. Gold (Au) bumps on an LSI chip were bonded directly to aluminum (Al) electrodes on a glass substrate by formation of Al-Au intermetallic compounds in the diffusion layer. The developed repairable bonding technique consists of two-level bonding process. First, the chip was bonded at 250/spl deg/C. Partial interconnection could be obtained at the local contact portions between the Au bump and the Al electrode. If the electrical connection failed, the bonded chip was removed. There was a distribution of the area formed Al-Au intermetallic compounds at local contact portions for 250/spl deg/C bonding. Some areas formed Al-Au intermetallic compounds of the Al electrode and were sometimes removed with the chip removal, with an underlying metal layer locally exposed at the surface. Then, a new chip was bonded on the same Al electrodes under the same conditions at 250/spl deg/C. After obtaining the electrical connection, the second bonding was done at 350/spl deg/C. An AlAu/sub 4/ intermetallic formation was obtained by this bonding in the diffusion layer. Reliability tests of second bonded samples were carried out and the contact resistance between the Au bumps and the Al electrodes was measured by the four-probe resistance measurement. In the case that the exposed area ratio of the underlying metal layer was less than 30% of bonding area for each Al electrode, a stable electrical connection was achieved for a high temperature storage test and a thermal shock test. Thus it was confirmed that a stable electrical connection had been obtained by the proposed repairable bonding process.
{"title":"The development of repairable Au-Al solid phase diffusion flip-chip bonding","authors":"A. Iida, Y. Kizaki, Y. Fukuda, M. Mori","doi":"10.1109/ECTC.1997.606153","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606153","url":null,"abstract":"The authors have developed a new repairable chip-on-glass (COG) bonding technique for liquid crystal display (LCD) panels. Gold (Au) bumps on an LSI chip were bonded directly to aluminum (Al) electrodes on a glass substrate by formation of Al-Au intermetallic compounds in the diffusion layer. The developed repairable bonding technique consists of two-level bonding process. First, the chip was bonded at 250/spl deg/C. Partial interconnection could be obtained at the local contact portions between the Au bump and the Al electrode. If the electrical connection failed, the bonded chip was removed. There was a distribution of the area formed Al-Au intermetallic compounds at local contact portions for 250/spl deg/C bonding. Some areas formed Al-Au intermetallic compounds of the Al electrode and were sometimes removed with the chip removal, with an underlying metal layer locally exposed at the surface. Then, a new chip was bonded on the same Al electrodes under the same conditions at 250/spl deg/C. After obtaining the electrical connection, the second bonding was done at 350/spl deg/C. An AlAu/sub 4/ intermetallic formation was obtained by this bonding in the diffusion layer. Reliability tests of second bonded samples were carried out and the contact resistance between the Au bumps and the Al electrodes was measured by the four-probe resistance measurement. In the case that the exposed area ratio of the underlying metal layer was less than 30% of bonding area for each Al electrode, a stable electrical connection was achieved for a high temperature storage test and a thermal shock test. Thus it was confirmed that a stable electrical connection had been obtained by the proposed repairable bonding process.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131785409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606177
P. Elenius
Soldered flip chips require the formation of a solder bump on the semiconductor device. Traditional solder deposition methods of evaporation and plating have limitations both from a cost structure as well as in capability to meet product requirements. Presented in this paper are the capabilities and reliability results of the FOC (Flex on Cap) solder paste bumping process developed by Delco Electronics and practiced by Flip Chip Technologies. This paper will describe the fine pitch capabilities, solder alloys, bump height uniformity, alloy control and reliability data for the FOC process. The ability of the solder paste process to meet the Pb free requirements of alpha particle sensitive devices and future environmental requirements will be discussed. The importance of the UBM (Under Bump Metallization) for reliable eutectic Pb/Sn and other high Sn content solders that are important for the DCA (Direct Chip Attach) market will be shown. The system level cost savings of having all the necessary solder present on the IC eliminating the deposition of solder on the board will be given. Examples will be provided on the cost of wafer bumping as related to both DCA applications and IC packaging.
焊接倒装芯片需要在半导体器件上形成一个焊料凸起。传统的蒸发和电镀焊锡沉积方法在成本结构和满足产品要求的能力方面都有局限性。本文介绍了Delco Electronics开发并由Flip Chip Technologies实施的FOC (Flex on Cap)焊膏碰撞工艺的性能和可靠性结果。本文将描述FOC工艺的细间距能力、焊料合金、凹凸高度均匀性、合金控制和可靠性数据。将讨论锡膏工艺满足α粒子敏感器件无铅要求和未来环境要求的能力。UBM(碰撞金属化)对于可靠的共晶Pb/Sn和其他高锡含量焊料的重要性，这对DCA(直接芯片连接)市场很重要。将所有必要的焊料都放在集成电路上，从而消除了焊料在电路板上的沉积，从而节省了系统级成本。我们将举例说明与DCA应用和IC封装相关的晶圆碰撞成本。
{"title":"Flex on cap-solder paste bumping","authors":"P. Elenius","doi":"10.1109/ECTC.1997.606177","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606177","url":null,"abstract":"Soldered flip chips require the formation of a solder bump on the semiconductor device. Traditional solder deposition methods of evaporation and plating have limitations both from a cost structure as well as in capability to meet product requirements. Presented in this paper are the capabilities and reliability results of the FOC (Flex on Cap) solder paste bumping process developed by Delco Electronics and practiced by Flip Chip Technologies. This paper will describe the fine pitch capabilities, solder alloys, bump height uniformity, alloy control and reliability data for the FOC process. The ability of the solder paste process to meet the Pb free requirements of alpha particle sensitive devices and future environmental requirements will be discussed. The importance of the UBM (Under Bump Metallization) for reliable eutectic Pb/Sn and other high Sn content solders that are important for the DCA (Direct Chip Attach) market will be shown. The system level cost savings of having all the necessary solder present on the IC eliminating the deposition of solder on the board will be given. Examples will be provided on the cost of wafer bumping as related to both DCA applications and IC packaging.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132682865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606321
Y. Li, E.L. Bradawy, E.L. Sharawy, L. Polka, A. Madrid, J. Liao, D. Figueroa
This paper presents a Finite-Difference Time-Domain (FDTD) analysis of meshed power planes that exist in multilayer plastic packages. The structure is divided into unit cells, and the analysis is used to find an equivalent circuit. An ABCD matrix of a periodic meshed plane is derived based on the FDTD analysis of a unit cell. The Bloch impedance and characteristic equation are solved to find the line impedance. This combined electromagnetic and circuit solution optimizes the accuracy and computational efficiency of the analysis. Experimental validation using a plastic land grid array (PLGA) test coupon is used to determine the accuracy of the theoretical analysis. The test coupon consists of a meshed plane structure with traces running beneath both the solid and the gap areas of the plane. Time-domain reflectometry (TDR) is used to measure the effects of the plane geometry on the impedance and propagation characteristics of the trace.
{"title":"Modeling and experimental validation of interconnects with meshed power planes","authors":"Y. Li, E.L. Bradawy, E.L. Sharawy, L. Polka, A. Madrid, J. Liao, D. Figueroa","doi":"10.1109/ECTC.1997.606321","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606321","url":null,"abstract":"This paper presents a Finite-Difference Time-Domain (FDTD) analysis of meshed power planes that exist in multilayer plastic packages. The structure is divided into unit cells, and the analysis is used to find an equivalent circuit. An ABCD matrix of a periodic meshed plane is derived based on the FDTD analysis of a unit cell. The Bloch impedance and characteristic equation are solved to find the line impedance. This combined electromagnetic and circuit solution optimizes the accuracy and computational efficiency of the analysis. Experimental validation using a plastic land grid array (PLGA) test coupon is used to determine the accuracy of the theoretical analysis. The test coupon consists of a meshed plane structure with traces running beneath both the solid and the gap areas of the plane. Time-domain reflectometry (TDR) is used to measure the effects of the plane geometry on the impedance and propagation characteristics of the trace.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133361080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606147
L. Nguyen, J. Jackson, C. H. Teo, S. Chillara, C. Asanasavest, T. Burke, R. Walberg, R. Lo, P. Weiler, D. Ho, H. Rauhut
Twenty different epoxy compound formulations were evaluated to assess the moldability and the resulting wire sweep propensity in a manual gang-pot molding machine. Effects such as filler content, filler shape and size, hardener viscosity, catalyst level, resin type, and thixotropic index were considered. Results obtained on a 160-lead PQFP with wire lengths up to 160 mils helped reduce the selection down to 5 formulations, which were then tested in a fully automated gang-pot system in a production environment. Aside from wire sweep, effects on die pad shift was also considered. This paper will discuss the relationship between the compound formulations, moldability, wire sweep, and pad shift. Although results were obtained on a test die with 100 /spl mu/m pad pitch, the information garnered should be extendible down to finer pitch.
{"title":"Wire sweep control with mold compound formulations [plastic packaging]","authors":"L. Nguyen, J. Jackson, C. H. Teo, S. Chillara, C. Asanasavest, T. Burke, R. Walberg, R. Lo, P. Weiler, D. Ho, H. Rauhut","doi":"10.1109/ECTC.1997.606147","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606147","url":null,"abstract":"Twenty different epoxy compound formulations were evaluated to assess the moldability and the resulting wire sweep propensity in a manual gang-pot molding machine. Effects such as filler content, filler shape and size, hardener viscosity, catalyst level, resin type, and thixotropic index were considered. Results obtained on a 160-lead PQFP with wire lengths up to 160 mils helped reduce the selection down to 5 formulations, which were then tested in a fully automated gang-pot system in a production environment. Aside from wire sweep, effects on die pad shift was also considered. This paper will discuss the relationship between the compound formulations, moldability, wire sweep, and pad shift. Although results were obtained on a test die with 100 /spl mu/m pad pitch, the information garnered should be extendible down to finer pitch.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133518440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606289
N. Umehara, M. Amagai, M. Kobayashi
The mechanical stability of plastic packages such as QFP, BGA, and CSP used in surface mount technology is our primary concern. The dominant issue is the interfacial delamination around the die attach materials. Furthermore, significant production cost increases occur due to a variety of chip sizes requiring numerous die pads for lead frame designs. To address these issues, a unique process has been developed, called "Polyimide-Transferred Wafer Process". This technology allows the thermoplastic polyimide to be perfectly transferred from its coating dicing tapes to the wafer backside at an elevated temperature prior to the dicing process. The polyimide-deposited chip replaces the die attach dispense process and has given rise to the possibility of all sorts of cost efficient lead frame designs.
{"title":"Application of die attachless process for plastic packages (Thermoplastic Polyimide-Transferred Wafer Technology)","authors":"N. Umehara, M. Amagai, M. Kobayashi","doi":"10.1109/ECTC.1997.606289","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606289","url":null,"abstract":"The mechanical stability of plastic packages such as QFP, BGA, and CSP used in surface mount technology is our primary concern. The dominant issue is the interfacial delamination around the die attach materials. Furthermore, significant production cost increases occur due to a variety of chip sizes requiring numerous die pads for lead frame designs. To address these issues, a unique process has been developed, called \"Polyimide-Transferred Wafer Process\". This technology allows the thermoplastic polyimide to be perfectly transferred from its coating dicing tapes to the wafer backside at an elevated temperature prior to the dicing process. The polyimide-deposited chip replaces the die attach dispense process and has given rise to the possibility of all sorts of cost efficient lead frame designs.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132172912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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