Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606198
H. Kosaka, M. Kajita, M. Yamada, Y. Sugimoto, K. Kurata, T. Tanabe, Y. Kasukawa
We have developed one-dimensional and two-dimensional push/pull-receptacle-type vertical-cavity surface-emitting laser (VCSEL)-array modules. The one-dimensional (1-D) 8-channel module connects with a conventional mechanically-transferable multifiber push-on (MPO) fiber connector. For the two-dimensional (2-D) 16-channel module, we developed an 8/spl times/2 2-D push/pull fiber connector. These modules employ plastic-based receptacle packages directly joined to the fiber connector. After the VCSEL-array chip was self-aligned to the Si substrate by using flip-chip bonding, the substrate was also self-aligned to the package by using a self-alignment mounting machine. Optical coupling losses for the 1-D and the 2-D modules were respectively 2.1/spl plusmn/0.4 and 2.1/spl plusmn/0.8 dB. The modules were operated at a bit rate of 1 Gbps/ch without an isolator and showed floorless BER performance up to 70/spl deg/C. At 1 Gbps/ch their optical sensitivities were respectively -25.0 dBm/spl plusmn/1.0 dB and -26.0 dBm/spl plusmn/0.9 dB. These structures and techniques are applicable to high-density, high-throughput interconnection.
{"title":"Plastic-based receptacle-type VCSEL-array modules with one and two dimensions fabricated using the self-alignment mounting technique","authors":"H. Kosaka, M. Kajita, M. Yamada, Y. Sugimoto, K. Kurata, T. Tanabe, Y. Kasukawa","doi":"10.1109/ECTC.1997.606198","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606198","url":null,"abstract":"We have developed one-dimensional and two-dimensional push/pull-receptacle-type vertical-cavity surface-emitting laser (VCSEL)-array modules. The one-dimensional (1-D) 8-channel module connects with a conventional mechanically-transferable multifiber push-on (MPO) fiber connector. For the two-dimensional (2-D) 16-channel module, we developed an 8/spl times/2 2-D push/pull fiber connector. These modules employ plastic-based receptacle packages directly joined to the fiber connector. After the VCSEL-array chip was self-aligned to the Si substrate by using flip-chip bonding, the substrate was also self-aligned to the package by using a self-alignment mounting machine. Optical coupling losses for the 1-D and the 2-D modules were respectively 2.1/spl plusmn/0.4 and 2.1/spl plusmn/0.8 dB. The modules were operated at a bit rate of 1 Gbps/ch without an isolator and showed floorless BER performance up to 70/spl deg/C. At 1 Gbps/ch their optical sensitivities were respectively -25.0 dBm/spl plusmn/1.0 dB and -26.0 dBm/spl plusmn/0.9 dB. These structures and techniques are applicable to high-density, high-throughput interconnection.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127894060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606287
T. Swirbel
Photosensitive epoxy resins are being developed to use as an innerlayer dielectric use in the printed circuit board industry. Using photoimageable dielectrics instead of traditional epoxy laminate is becoming a preferred method for fabricating high density circuit boards such as those used in multichip module (MCM-L) applications. Photoimageable epoxy has a significantly lower cost than polyimide or benzocyclobutene (BCB). If the material performance of the photoimageable epoxies is acceptable, the potential for lower fabrication costs for multichip modules on inorganic substrates such as ceramic, glass, and silicon is possible. The photoimageable materials evaluated in this study were a modified epoxy from Ciba Geigy, an acryclic-based epoxy from Enthone, and a polybutadiene-based epoxy from Shipley. They were evaluated for substrate adhesion, metal adhesion, and via formation. These materials had very good photoimaging properties and were capable of forming 10 /spl mu/m features in a 5 /spl mu/m thick dielectric layer. Multilayer modules with 25 /spl mu/m design rules have been successfully fabricated on glass and ceramic substrates using the acrylic and polybutadiene as the innerlayer dielectric. These modules have not had dielectric, via, or metallization failures through high temperature reflows, humidity testing, or -55/spl deg/C to 125/spl deg/C temperature cycling.
{"title":"Process for fabricating thin film multilayer modules using photosensitive epoxy dielectrics","authors":"T. Swirbel","doi":"10.1109/ECTC.1997.606287","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606287","url":null,"abstract":"Photosensitive epoxy resins are being developed to use as an innerlayer dielectric use in the printed circuit board industry. Using photoimageable dielectrics instead of traditional epoxy laminate is becoming a preferred method for fabricating high density circuit boards such as those used in multichip module (MCM-L) applications. Photoimageable epoxy has a significantly lower cost than polyimide or benzocyclobutene (BCB). If the material performance of the photoimageable epoxies is acceptable, the potential for lower fabrication costs for multichip modules on inorganic substrates such as ceramic, glass, and silicon is possible. The photoimageable materials evaluated in this study were a modified epoxy from Ciba Geigy, an acryclic-based epoxy from Enthone, and a polybutadiene-based epoxy from Shipley. They were evaluated for substrate adhesion, metal adhesion, and via formation. These materials had very good photoimaging properties and were capable of forming 10 /spl mu/m features in a 5 /spl mu/m thick dielectric layer. Multilayer modules with 25 /spl mu/m design rules have been successfully fabricated on glass and ceramic substrates using the acrylic and polybutadiene as the innerlayer dielectric. These modules have not had dielectric, via, or metallization failures through high temperature reflows, humidity testing, or -55/spl deg/C to 125/spl deg/C temperature cycling.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126209181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606304
Tai-Yu-Chou, F. Wu, J. Lau, Kuan-Luen Chen
This paper presents a new class of low cost, electrically and thermally optimized ball grid array packages, called NuBGA (new and useful ball grid array). The package is suitable for both low and high pin count applications. NuBGA is a cavity down package with a metal heatspreader covering the entire back surface of the package. Heat spreader is laminated with a single core double sided organic substrate. Optimized electrical performance is achieved using the design concepts of Split-Wrap-Around (SWA) and Split-Via-Connections (SVC). All traces on the core substrate can be designed into /spl mu/-stripline and co-planar stripline structures. Further enhanced thermal and electrical performance NuBGA can be achieved by applying an additional metal stiffener and thinner core substrate. In this paper, the presentation is focus on (1) the unique design concept, (2) the electrical analysis, (3) the electrical measurement, and (4) the performance comparison with standard packages.
{"title":"Electrical design of a low cost and high performance plastic ball grid array package-NuBGA","authors":"Tai-Yu-Chou, F. Wu, J. Lau, Kuan-Luen Chen","doi":"10.1109/ECTC.1997.606304","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606304","url":null,"abstract":"This paper presents a new class of low cost, electrically and thermally optimized ball grid array packages, called NuBGA (new and useful ball grid array). The package is suitable for both low and high pin count applications. NuBGA is a cavity down package with a metal heatspreader covering the entire back surface of the package. Heat spreader is laminated with a single core double sided organic substrate. Optimized electrical performance is achieved using the design concepts of Split-Wrap-Around (SWA) and Split-Via-Connections (SVC). All traces on the core substrate can be designed into /spl mu/-stripline and co-planar stripline structures. Further enhanced thermal and electrical performance NuBGA can be achieved by applying an additional metal stiffener and thinner core substrate. In this paper, the presentation is focus on (1) the unique design concept, (2) the electrical analysis, (3) the electrical measurement, and (4) the performance comparison with standard packages.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126378871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606166
G. Selvaduray, F. Baret
This paper describes the development of an engineering education curriculum in microelectronic packaging at both the undergraduate and graduate levels, at the College of Engineering, San Jose State University. Motivation for establishing courses to support such a curriculum and the needs of the local electronics industry are discussed. The undergraduate courses are taught in the lecture/laboratory mode, thus requiring students to conduct experiments. The interdisciplinary graduate curriculum is offered as an area of specialization within the Master of Science in Engineering program. Guest speakers from industry are invited to discuss advances and challenges present in this constantly evolving field. The College also offers short courses for engineers practicing in industry. With NSF funding, workshops for skills enhancement of university faculty are currently in the planning stage; four such workshops will be offered during 1997-1998.
{"title":"Microelectronics packaging curriculum development at San Jose State University","authors":"G. Selvaduray, F. Baret","doi":"10.1109/ECTC.1997.606166","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606166","url":null,"abstract":"This paper describes the development of an engineering education curriculum in microelectronic packaging at both the undergraduate and graduate levels, at the College of Engineering, San Jose State University. Motivation for establishing courses to support such a curriculum and the needs of the local electronics industry are discussed. The undergraduate courses are taught in the lecture/laboratory mode, thus requiring students to conduct experiments. The interdisciplinary graduate curriculum is offered as an area of specialization within the Master of Science in Engineering program. Guest speakers from industry are invited to discuss advances and challenges present in this constantly evolving field. The College also offers short courses for engineers practicing in industry. With NSF funding, workshops for skills enhancement of university faculty are currently in the planning stage; four such workshops will be offered during 1997-1998.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114268159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606323
Wenge Zhang, Derick Wu, B. Su, S. Hareb, Y.C. Lee
The effect of underfill epoxy on mechanical behavior was investigated by measuring the thermally-induced warpage on both a real flip chip thermosonic bonded assembly and a simulated tri-layered assembly. The assembly's mechanical behavior was dominated by the underfill epoxy rather than solder joints. Such a dominant role was not affected even when the assembly had 196 solder joints under a 5.8 mm/spl times/5.8 mm chip. Epoxy properties are well characterized by the curing and the glass transition temperatures, and these characteristic temperatures clearly divide the warpage levels into two distinctive regions. When the maximum temperature the assembly exposed to was less than the glass transition temperature (Tg), the mechanical behavior was characterized by the curing temperature. When the maximum temperature was higher than the Tg, the behavior was characterized by the Tg. Corresponding to different characteristic temperatures, e.g. 80/spl deg/C for curing and 130/spl deg/C for Tg, the warpage as well as the Von Misses stress each could increase by as much as a factor of two. Such an increase could affect device reliability for RF packages and alignment for optoelectronic packages. With the selected epoxy materials, mechanical behavior of a flip-chip with underfill epoxy is stable and predictable.
{"title":"The effect of underfill epoxy on mechanical behavior of flip chip assembly","authors":"Wenge Zhang, Derick Wu, B. Su, S. Hareb, Y.C. Lee","doi":"10.1109/ECTC.1997.606323","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606323","url":null,"abstract":"The effect of underfill epoxy on mechanical behavior was investigated by measuring the thermally-induced warpage on both a real flip chip thermosonic bonded assembly and a simulated tri-layered assembly. The assembly's mechanical behavior was dominated by the underfill epoxy rather than solder joints. Such a dominant role was not affected even when the assembly had 196 solder joints under a 5.8 mm/spl times/5.8 mm chip. Epoxy properties are well characterized by the curing and the glass transition temperatures, and these characteristic temperatures clearly divide the warpage levels into two distinctive regions. When the maximum temperature the assembly exposed to was less than the glass transition temperature (Tg), the mechanical behavior was characterized by the curing temperature. When the maximum temperature was higher than the Tg, the behavior was characterized by the Tg. Corresponding to different characteristic temperatures, e.g. 80/spl deg/C for curing and 130/spl deg/C for Tg, the warpage as well as the Von Misses stress each could increase by as much as a factor of two. Such an increase could affect device reliability for RF packages and alignment for optoelectronic packages. With the selected epoxy materials, mechanical behavior of a flip-chip with underfill epoxy is stable and predictable.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127639588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606273
T. Zhou, M. Hundt, C. Villa, R. Bond, T. Lao
Thermal characteristics of flip chip on FR4 boards are presented. The thermal resistances are determined for different die and board constructions, underfill material, and heat sink applications. Thermal paths are analyzed to understand the flip chip heat dissipation mechanism. It is realized that the junction to ambient thermal resistance is dominated by the system environment. The package resistance is only a trivial portion of the total resistance. Improvement of thermal performance should be concentrated on the system level. Thermal performance of flip chip is compared to that of PQFP and PBGA. Recommendations in flip chip thermal management are given at the end. This work is based on both experimental and numerical studies.
{"title":"Thermal study for flip chip on FR-4 boards","authors":"T. Zhou, M. Hundt, C. Villa, R. Bond, T. Lao","doi":"10.1109/ECTC.1997.606273","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606273","url":null,"abstract":"Thermal characteristics of flip chip on FR4 boards are presented. The thermal resistances are determined for different die and board constructions, underfill material, and heat sink applications. Thermal paths are analyzed to understand the flip chip heat dissipation mechanism. It is realized that the junction to ambient thermal resistance is dominated by the system environment. The package resistance is only a trivial portion of the total resistance. Improvement of thermal performance should be concentrated on the system level. Thermal performance of flip chip is compared to that of PQFP and PBGA. Recommendations in flip chip thermal management are given at the end. This work is based on both experimental and numerical studies.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127823528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606126
N. Takehashi, M. Horii
This paper describes a new premolded organic packaging technology for low cost E/O applications. This premolded packaging technology provides a low cost packaging option for E/O devices with high reliability was requirements. A reliability test method for premold technology was used to evaluate water penetration into the package cavity; it evaluates dew temperature after high temperature and high humidity storage. Measurement results indicate package performance very close to that of a ceramic package. This new low water penetration organic material has been developed to supply high reliability, low cost packaging technology to the E/O market. This paper proposes a design concept utilizing this premold material. The design includes an optical fiber pipe molded in the side wall of package.
{"title":"A new premolded packaging technology for low cost E/O device applications","authors":"N. Takehashi, M. Horii","doi":"10.1109/ECTC.1997.606126","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606126","url":null,"abstract":"This paper describes a new premolded organic packaging technology for low cost E/O applications. This premolded packaging technology provides a low cost packaging option for E/O devices with high reliability was requirements. A reliability test method for premold technology was used to evaluate water penetration into the package cavity; it evaluates dew temperature after high temperature and high humidity storage. Measurement results indicate package performance very close to that of a ceramic package. This new low water penetration organic material has been developed to supply high reliability, low cost packaging technology to the E/O market. This paper proposes a design concept utilizing this premold material. The design includes an optical fiber pipe molded in the side wall of package.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127840885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606179
L. Levine
The process of using a ball bonder to form bumps on a chip, for subsequent TAB or Flip Chip attachment to a substrate, has now reached the production stage. A number of companies are using the process for full scale production. Other companies are using the process for rapid prototyping and limited quantity production. The advantages of the ball bumping process are that it requires no expensive masks or wet processing. It also uses existing equipment, experienced personnel, and it has the flexibility and ease of manufacturing associated with wire bonding. The yields and reliability of wire bonding are well established, and the ball bumping process is the same as the ball bonding portion of the wire bond process. Similar yields are expected. In many cases ball bumping provides the most cost effective method for depositing bumps on chips. Two process variations are prevalent. 1. Bumping and coining, is a process where a normal ball bond with a short ductile fracture tip protruding from the top of the ball is bonded to the device. Optionally, the bumps are then coined flat by a second stage operation. 2. The stud bumping process produces a short loop with the crescent bond placed on the shoulder of the ball.
{"title":"Ball bumping and coining operations for TAB and flip chip","authors":"L. Levine","doi":"10.1109/ECTC.1997.606179","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606179","url":null,"abstract":"The process of using a ball bonder to form bumps on a chip, for subsequent TAB or Flip Chip attachment to a substrate, has now reached the production stage. A number of companies are using the process for full scale production. Other companies are using the process for rapid prototyping and limited quantity production. The advantages of the ball bumping process are that it requires no expensive masks or wet processing. It also uses existing equipment, experienced personnel, and it has the flexibility and ease of manufacturing associated with wire bonding. The yields and reliability of wire bonding are well established, and the ball bumping process is the same as the ball bonding portion of the wire bond process. Similar yields are expected. In many cases ball bumping provides the most cost effective method for depositing bumps on chips. Two process variations are prevalent. 1. Bumping and coining, is a process where a normal ball bond with a short ductile fracture tip protruding from the top of the ball is bonded to the device. Optionally, the bumps are then coined flat by a second stage operation. 2. The stud bumping process produces a short loop with the crescent bond placed on the shoulder of the ball.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122345158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606222
S.X. Wu, C. Zhang, C. Yeh, S. Wille, K. Wyatt
The curing reaction of a conductive adhesive was studied with a differential scanning calorimeter (DSC) under isothermal conditions in the range of 100-160/spl deg/C. An autocatalyzed kinetic model was used to describe the curing reaction. The rate constant and the reaction orders were determined and used in the model to predict the progress of the curing reactions. A good agreement is found between the proposed kinetic model and the experimental reaction rate data. The reaction rate constants were correlated with the isothermal temperature by the Arrhenius equation. The activation energy for the curing reaction is determined to be 94.9 kJ/mol. The reaction order which represents the effects of the unreacted materials is found to be a parabolic function of temperature. But the effects of the reacted materials on the reaction rate change sharply at around 120/spl deg/C. Unlike some previous results on epoxy curing kinetics, the sum of the two reaction orders is not a constant for this conductive adhesive. Thermogravimetric Analyzer (TGA) was used to study the weight loss during thermal processes. The degradation temperature of the conductive adhesive was found to be 250/spl deg/C. The properties of the corresponding unfilled epoxy were also studied with the DSC and TGA. Results were compared with those obtained from the conductive adhesive. Tests were conducted to investigate the mechanical and electrical property changes during cure.
{"title":"Cure kinetics and mechanical properties of conductive adhesive","authors":"S.X. Wu, C. Zhang, C. Yeh, S. Wille, K. Wyatt","doi":"10.1109/ECTC.1997.606222","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606222","url":null,"abstract":"The curing reaction of a conductive adhesive was studied with a differential scanning calorimeter (DSC) under isothermal conditions in the range of 100-160/spl deg/C. An autocatalyzed kinetic model was used to describe the curing reaction. The rate constant and the reaction orders were determined and used in the model to predict the progress of the curing reactions. A good agreement is found between the proposed kinetic model and the experimental reaction rate data. The reaction rate constants were correlated with the isothermal temperature by the Arrhenius equation. The activation energy for the curing reaction is determined to be 94.9 kJ/mol. The reaction order which represents the effects of the unreacted materials is found to be a parabolic function of temperature. But the effects of the reacted materials on the reaction rate change sharply at around 120/spl deg/C. Unlike some previous results on epoxy curing kinetics, the sum of the two reaction orders is not a constant for this conductive adhesive. Thermogravimetric Analyzer (TGA) was used to study the weight loss during thermal processes. The degradation temperature of the conductive adhesive was found to be 250/spl deg/C. The properties of the corresponding unfilled epoxy were also studied with the DSC and TGA. Results were compared with those obtained from the conductive adhesive. Tests were conducted to investigate the mechanical and electrical property changes during cure.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122955302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606159
Minfu Lu, W. Ren, Sheng Liu, D. Shangguan
A recently developed multi-axial sub-micron thermomechanical fatigue tester has been used for investigating the behaviors of small specimens, particularly in the field of electronic packaging materials and structures. Materials tested include a copper wire, polycarbonate and polyimide films and a lead-free solder alloy. An active alignment monitoring and adjustment has been found to be important for realistic characteristics of tiny points.
{"title":"A unified multi-axial sub-micron fatigue tester with applications to electronic packaging materials","authors":"Minfu Lu, W. Ren, Sheng Liu, D. Shangguan","doi":"10.1109/ECTC.1997.606159","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606159","url":null,"abstract":"A recently developed multi-axial sub-micron thermomechanical fatigue tester has been used for investigating the behaviors of small specimens, particularly in the field of electronic packaging materials and structures. Materials tested include a copper wire, polycarbonate and polyimide films and a lead-free solder alloy. An active alignment monitoring and adjustment has been found to be important for realistic characteristics of tiny points.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124042790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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