Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606273
T. Zhou, M. Hundt, C. Villa, R. Bond, T. Lao
Thermal characteristics of flip chip on FR4 boards are presented. The thermal resistances are determined for different die and board constructions, underfill material, and heat sink applications. Thermal paths are analyzed to understand the flip chip heat dissipation mechanism. It is realized that the junction to ambient thermal resistance is dominated by the system environment. The package resistance is only a trivial portion of the total resistance. Improvement of thermal performance should be concentrated on the system level. Thermal performance of flip chip is compared to that of PQFP and PBGA. Recommendations in flip chip thermal management are given at the end. This work is based on both experimental and numerical studies.
{"title":"Thermal study for flip chip on FR-4 boards","authors":"T. Zhou, M. Hundt, C. Villa, R. Bond, T. Lao","doi":"10.1109/ECTC.1997.606273","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606273","url":null,"abstract":"Thermal characteristics of flip chip on FR4 boards are presented. The thermal resistances are determined for different die and board constructions, underfill material, and heat sink applications. Thermal paths are analyzed to understand the flip chip heat dissipation mechanism. It is realized that the junction to ambient thermal resistance is dominated by the system environment. The package resistance is only a trivial portion of the total resistance. Improvement of thermal performance should be concentrated on the system level. Thermal performance of flip chip is compared to that of PQFP and PBGA. Recommendations in flip chip thermal management are given at the end. This work is based on both experimental and numerical studies.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127823528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606126
N. Takehashi, M. Horii
This paper describes a new premolded organic packaging technology for low cost E/O applications. This premolded packaging technology provides a low cost packaging option for E/O devices with high reliability was requirements. A reliability test method for premold technology was used to evaluate water penetration into the package cavity; it evaluates dew temperature after high temperature and high humidity storage. Measurement results indicate package performance very close to that of a ceramic package. This new low water penetration organic material has been developed to supply high reliability, low cost packaging technology to the E/O market. This paper proposes a design concept utilizing this premold material. The design includes an optical fiber pipe molded in the side wall of package.
{"title":"A new premolded packaging technology for low cost E/O device applications","authors":"N. Takehashi, M. Horii","doi":"10.1109/ECTC.1997.606126","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606126","url":null,"abstract":"This paper describes a new premolded organic packaging technology for low cost E/O applications. This premolded packaging technology provides a low cost packaging option for E/O devices with high reliability was requirements. A reliability test method for premold technology was used to evaluate water penetration into the package cavity; it evaluates dew temperature after high temperature and high humidity storage. Measurement results indicate package performance very close to that of a ceramic package. This new low water penetration organic material has been developed to supply high reliability, low cost packaging technology to the E/O market. This paper proposes a design concept utilizing this premold material. The design includes an optical fiber pipe molded in the side wall of package.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127840885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606198
H. Kosaka, M. Kajita, M. Yamada, Y. Sugimoto, K. Kurata, T. Tanabe, Y. Kasukawa
We have developed one-dimensional and two-dimensional push/pull-receptacle-type vertical-cavity surface-emitting laser (VCSEL)-array modules. The one-dimensional (1-D) 8-channel module connects with a conventional mechanically-transferable multifiber push-on (MPO) fiber connector. For the two-dimensional (2-D) 16-channel module, we developed an 8/spl times/2 2-D push/pull fiber connector. These modules employ plastic-based receptacle packages directly joined to the fiber connector. After the VCSEL-array chip was self-aligned to the Si substrate by using flip-chip bonding, the substrate was also self-aligned to the package by using a self-alignment mounting machine. Optical coupling losses for the 1-D and the 2-D modules were respectively 2.1/spl plusmn/0.4 and 2.1/spl plusmn/0.8 dB. The modules were operated at a bit rate of 1 Gbps/ch without an isolator and showed floorless BER performance up to 70/spl deg/C. At 1 Gbps/ch their optical sensitivities were respectively -25.0 dBm/spl plusmn/1.0 dB and -26.0 dBm/spl plusmn/0.9 dB. These structures and techniques are applicable to high-density, high-throughput interconnection.
{"title":"Plastic-based receptacle-type VCSEL-array modules with one and two dimensions fabricated using the self-alignment mounting technique","authors":"H. Kosaka, M. Kajita, M. Yamada, Y. Sugimoto, K. Kurata, T. Tanabe, Y. Kasukawa","doi":"10.1109/ECTC.1997.606198","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606198","url":null,"abstract":"We have developed one-dimensional and two-dimensional push/pull-receptacle-type vertical-cavity surface-emitting laser (VCSEL)-array modules. The one-dimensional (1-D) 8-channel module connects with a conventional mechanically-transferable multifiber push-on (MPO) fiber connector. For the two-dimensional (2-D) 16-channel module, we developed an 8/spl times/2 2-D push/pull fiber connector. These modules employ plastic-based receptacle packages directly joined to the fiber connector. After the VCSEL-array chip was self-aligned to the Si substrate by using flip-chip bonding, the substrate was also self-aligned to the package by using a self-alignment mounting machine. Optical coupling losses for the 1-D and the 2-D modules were respectively 2.1/spl plusmn/0.4 and 2.1/spl plusmn/0.8 dB. The modules were operated at a bit rate of 1 Gbps/ch without an isolator and showed floorless BER performance up to 70/spl deg/C. At 1 Gbps/ch their optical sensitivities were respectively -25.0 dBm/spl plusmn/1.0 dB and -26.0 dBm/spl plusmn/0.9 dB. These structures and techniques are applicable to high-density, high-throughput interconnection.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127894060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606311
B. Schluter, J. De La Rosa, R. Mattsen, K. Pearsall
With the increasing complexity of electronic assemblies, a greater number of interconnections between electronic cards are needed. In many cases, longer and higher density connectors are being used to supply this increased number of interconnections. As such the match of the thermal expansion of the printed circuit board (PCB) to that of the connectors is becoming more critical for proper assembly. This paper explores the dimensional changes to the card assemblies as these pin-in-hole (PIH) connectors and other large components are soldered to the card during the wave solder process. The relevant characteristics of both the connectors and the FR4 material are evaluated and the contributions of the significant processing variables are discussed. This includes the dimensional changes to the PCB and the connectors around the glass transition temperature and the melting temperature of the eutectic solder used in the wave solder machine. The distortion due to asymmetrical board lay-up is discussed independently. These effects are then related to the overall flatness of the card assembly after completion of the process. In conclusion there are some recommendations to minimize these effects for specific applications.
{"title":"Thermal effects on PCB's with connectors during solder attachment","authors":"B. Schluter, J. De La Rosa, R. Mattsen, K. Pearsall","doi":"10.1109/ECTC.1997.606311","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606311","url":null,"abstract":"With the increasing complexity of electronic assemblies, a greater number of interconnections between electronic cards are needed. In many cases, longer and higher density connectors are being used to supply this increased number of interconnections. As such the match of the thermal expansion of the printed circuit board (PCB) to that of the connectors is becoming more critical for proper assembly. This paper explores the dimensional changes to the card assemblies as these pin-in-hole (PIH) connectors and other large components are soldered to the card during the wave solder process. The relevant characteristics of both the connectors and the FR4 material are evaluated and the contributions of the significant processing variables are discussed. This includes the dimensional changes to the PCB and the connectors around the glass transition temperature and the melting temperature of the eutectic solder used in the wave solder machine. The distortion due to asymmetrical board lay-up is discussed independently. These effects are then related to the overall flatness of the card assembly after completion of the process. In conclusion there are some recommendations to minimize these effects for specific applications.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132374962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606231
E. Pennings
It is the purpose of this paper to investigate the challenges that are posed to optoelectronic packaging by WDM. The main thrust of this paper is to review two key components of WDM systems, i.e. the wavelength (de)multiplexer and the WDM laser source, and to compare an integrated optoelectronic approach versus a hybrid or modular approach. This allows us to compare different alternatives and provides insight into the relevant packaging issues as well. The paper starts with a review of network and component trends, an analysis of the WDM market, and a discussion on optoelectronic integration issues. Conclusions are presented at the end.
{"title":"Challenges in optoelectronic packaging for high performance WDM networks","authors":"E. Pennings","doi":"10.1109/ECTC.1997.606231","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606231","url":null,"abstract":"It is the purpose of this paper to investigate the challenges that are posed to optoelectronic packaging by WDM. The main thrust of this paper is to review two key components of WDM systems, i.e. the wavelength (de)multiplexer and the WDM laser source, and to compare an integrated optoelectronic approach versus a hybrid or modular approach. This allows us to compare different alternatives and provides insight into the relevant packaging issues as well. The paper starts with a review of network and component trends, an analysis of the WDM market, and a discussion on optoelectronic integration issues. Conclusions are presented at the end.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"03 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130997594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606296
Y. Yamaji, H. Juso, Y. Ohara, Yuji Matsune, K. Miyata, Y. Sota, A. Narai, T. Kimura, K. Fujita, M. Kada
High density packages are demanded due to recent miniaturization for personal tools. In order to satisfy these demands, development is being done in various companies in CSP (Chip-Size-Package or Chip-Scale-Package) in which its package size in nearly the same as LSI chip and function is close to bare chip. We have developed and mass production of CSP using current equipment based on a proven packaging technology involving wire bonding and transfer mold technology. We can realize 0.8 mm terminal pitch and from the memory with a few to ASIC with 300 in pin counts using this technology and correspond to various matrix layout independent of LSI chip size. The CSP developed by us uses polyimide with one side pattern. After mounting the LSI chip and connecting with wire bonding, one side is contained with mold resin. External terminals use solder ball which is of area array structure. In order to minimize the outline size of the package to be as close to the LSI chip as possible, various technologies were developed such as ultra-short loop wire bonding technology of a half length compared to conventional loop length, super-small solder ball mounting technology how far size of 0.3 mm /spl phi/, low stress high precision cutting technology with laser and fine pattern technology of substrate. Furthermore, in order to maintain high reliability to the level attained in conventional plastic packages, development was done on thermally resistant insulator and on mold resin which increase the adherence with substrate. Work was also done to reduce the effect of moisture in package through vent hole in pattern substrate. Regarding mounting to the PCB, the CSP developed by us is able to be mounted by merely recognizing of package's high precision outline with laser cutting technology and mounting with other packages is possible due to collective reflow which utilize conventional technologies. Reliability evaluation after mounting has shown that it is very realistic levels for us. By developing the above technologies and developing new materials, packaging technology for a highly reliable CSP was made possible.
{"title":"Development of highly reliable CSP","authors":"Y. Yamaji, H. Juso, Y. Ohara, Yuji Matsune, K. Miyata, Y. Sota, A. Narai, T. Kimura, K. Fujita, M. Kada","doi":"10.1109/ECTC.1997.606296","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606296","url":null,"abstract":"High density packages are demanded due to recent miniaturization for personal tools. In order to satisfy these demands, development is being done in various companies in CSP (Chip-Size-Package or Chip-Scale-Package) in which its package size in nearly the same as LSI chip and function is close to bare chip. We have developed and mass production of CSP using current equipment based on a proven packaging technology involving wire bonding and transfer mold technology. We can realize 0.8 mm terminal pitch and from the memory with a few to ASIC with 300 in pin counts using this technology and correspond to various matrix layout independent of LSI chip size. The CSP developed by us uses polyimide with one side pattern. After mounting the LSI chip and connecting with wire bonding, one side is contained with mold resin. External terminals use solder ball which is of area array structure. In order to minimize the outline size of the package to be as close to the LSI chip as possible, various technologies were developed such as ultra-short loop wire bonding technology of a half length compared to conventional loop length, super-small solder ball mounting technology how far size of 0.3 mm /spl phi/, low stress high precision cutting technology with laser and fine pattern technology of substrate. Furthermore, in order to maintain high reliability to the level attained in conventional plastic packages, development was done on thermally resistant insulator and on mold resin which increase the adherence with substrate. Work was also done to reduce the effect of moisture in package through vent hole in pattern substrate. Regarding mounting to the PCB, the CSP developed by us is able to be mounted by merely recognizing of package's high precision outline with laser cutting technology and mounting with other packages is possible due to collective reflow which utilize conventional technologies. Reliability evaluation after mounting has shown that it is very realistic levels for us. By developing the above technologies and developing new materials, packaging technology for a highly reliable CSP was made possible.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134507566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606211
R. Murphy, S. Sitaraman
The objective of this work is to develop two- and three-dimensional numerical models of VSPA, a new peripheral array package, and study its solder joint reliability. VSPA has multiple rows of butt-type leads around its periphery and is surface mounted on a standard FR-4 printed circuit board. The FR-4 and various package materials were modeled as temperature-dependent and elastic while the eutectic solder was modeled as temperature-dependent, elastic-plastic. The package and board assembly were subjected to a temperature increase (/spl Delta/T) of 85/spl deg/C with the assumption that the assembly is stress-free at room temperature. The results obtained from a three-dimensional 1/8th section model are compared with the results from 2-D plane-strain and plane-stress models and with 3-D "strip" models.
{"title":"Two and three-dimensional modeling of VSPA butt solder joints","authors":"R. Murphy, S. Sitaraman","doi":"10.1109/ECTC.1997.606211","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606211","url":null,"abstract":"The objective of this work is to develop two- and three-dimensional numerical models of VSPA, a new peripheral array package, and study its solder joint reliability. VSPA has multiple rows of butt-type leads around its periphery and is surface mounted on a standard FR-4 printed circuit board. The FR-4 and various package materials were modeled as temperature-dependent and elastic while the eutectic solder was modeled as temperature-dependent, elastic-plastic. The package and board assembly were subjected to a temperature increase (/spl Delta/T) of 85/spl deg/C with the assumption that the assembly is stress-free at room temperature. The results obtained from a three-dimensional 1/8th section model are compared with the results from 2-D plane-strain and plane-stress models and with 3-D \"strip\" models.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132167005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606179
L. Levine
The process of using a ball bonder to form bumps on a chip, for subsequent TAB or Flip Chip attachment to a substrate, has now reached the production stage. A number of companies are using the process for full scale production. Other companies are using the process for rapid prototyping and limited quantity production. The advantages of the ball bumping process are that it requires no expensive masks or wet processing. It also uses existing equipment, experienced personnel, and it has the flexibility and ease of manufacturing associated with wire bonding. The yields and reliability of wire bonding are well established, and the ball bumping process is the same as the ball bonding portion of the wire bond process. Similar yields are expected. In many cases ball bumping provides the most cost effective method for depositing bumps on chips. Two process variations are prevalent. 1. Bumping and coining, is a process where a normal ball bond with a short ductile fracture tip protruding from the top of the ball is bonded to the device. Optionally, the bumps are then coined flat by a second stage operation. 2. The stud bumping process produces a short loop with the crescent bond placed on the shoulder of the ball.
{"title":"Ball bumping and coining operations for TAB and flip chip","authors":"L. Levine","doi":"10.1109/ECTC.1997.606179","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606179","url":null,"abstract":"The process of using a ball bonder to form bumps on a chip, for subsequent TAB or Flip Chip attachment to a substrate, has now reached the production stage. A number of companies are using the process for full scale production. Other companies are using the process for rapid prototyping and limited quantity production. The advantages of the ball bumping process are that it requires no expensive masks or wet processing. It also uses existing equipment, experienced personnel, and it has the flexibility and ease of manufacturing associated with wire bonding. The yields and reliability of wire bonding are well established, and the ball bumping process is the same as the ball bonding portion of the wire bond process. Similar yields are expected. In many cases ball bumping provides the most cost effective method for depositing bumps on chips. Two process variations are prevalent. 1. Bumping and coining, is a process where a normal ball bond with a short ductile fracture tip protruding from the top of the ball is bonded to the device. Optionally, the bumps are then coined flat by a second stage operation. 2. The stud bumping process produces a short loop with the crescent bond placed on the shoulder of the ball.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122345158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606222
S.X. Wu, C. Zhang, C. Yeh, S. Wille, K. Wyatt
The curing reaction of a conductive adhesive was studied with a differential scanning calorimeter (DSC) under isothermal conditions in the range of 100-160/spl deg/C. An autocatalyzed kinetic model was used to describe the curing reaction. The rate constant and the reaction orders were determined and used in the model to predict the progress of the curing reactions. A good agreement is found between the proposed kinetic model and the experimental reaction rate data. The reaction rate constants were correlated with the isothermal temperature by the Arrhenius equation. The activation energy for the curing reaction is determined to be 94.9 kJ/mol. The reaction order which represents the effects of the unreacted materials is found to be a parabolic function of temperature. But the effects of the reacted materials on the reaction rate change sharply at around 120/spl deg/C. Unlike some previous results on epoxy curing kinetics, the sum of the two reaction orders is not a constant for this conductive adhesive. Thermogravimetric Analyzer (TGA) was used to study the weight loss during thermal processes. The degradation temperature of the conductive adhesive was found to be 250/spl deg/C. The properties of the corresponding unfilled epoxy were also studied with the DSC and TGA. Results were compared with those obtained from the conductive adhesive. Tests were conducted to investigate the mechanical and electrical property changes during cure.
{"title":"Cure kinetics and mechanical properties of conductive adhesive","authors":"S.X. Wu, C. Zhang, C. Yeh, S. Wille, K. Wyatt","doi":"10.1109/ECTC.1997.606222","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606222","url":null,"abstract":"The curing reaction of a conductive adhesive was studied with a differential scanning calorimeter (DSC) under isothermal conditions in the range of 100-160/spl deg/C. An autocatalyzed kinetic model was used to describe the curing reaction. The rate constant and the reaction orders were determined and used in the model to predict the progress of the curing reactions. A good agreement is found between the proposed kinetic model and the experimental reaction rate data. The reaction rate constants were correlated with the isothermal temperature by the Arrhenius equation. The activation energy for the curing reaction is determined to be 94.9 kJ/mol. The reaction order which represents the effects of the unreacted materials is found to be a parabolic function of temperature. But the effects of the reacted materials on the reaction rate change sharply at around 120/spl deg/C. Unlike some previous results on epoxy curing kinetics, the sum of the two reaction orders is not a constant for this conductive adhesive. Thermogravimetric Analyzer (TGA) was used to study the weight loss during thermal processes. The degradation temperature of the conductive adhesive was found to be 250/spl deg/C. The properties of the corresponding unfilled epoxy were also studied with the DSC and TGA. Results were compared with those obtained from the conductive adhesive. Tests were conducted to investigate the mechanical and electrical property changes during cure.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122955302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606159
Minfu Lu, W. Ren, Sheng Liu, D. Shangguan
A recently developed multi-axial sub-micron thermomechanical fatigue tester has been used for investigating the behaviors of small specimens, particularly in the field of electronic packaging materials and structures. Materials tested include a copper wire, polycarbonate and polyimide films and a lead-free solder alloy. An active alignment monitoring and adjustment has been found to be important for realistic characteristics of tiny points.
{"title":"A unified multi-axial sub-micron fatigue tester with applications to electronic packaging materials","authors":"Minfu Lu, W. Ren, Sheng Liu, D. Shangguan","doi":"10.1109/ECTC.1997.606159","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606159","url":null,"abstract":"A recently developed multi-axial sub-micron thermomechanical fatigue tester has been used for investigating the behaviors of small specimens, particularly in the field of electronic packaging materials and structures. Materials tested include a copper wire, polycarbonate and polyimide films and a lead-free solder alloy. An active alignment monitoring and adjustment has been found to be important for realistic characteristics of tiny points.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124042790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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