Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606211
R. Murphy, S. Sitaraman
The objective of this work is to develop two- and three-dimensional numerical models of VSPA, a new peripheral array package, and study its solder joint reliability. VSPA has multiple rows of butt-type leads around its periphery and is surface mounted on a standard FR-4 printed circuit board. The FR-4 and various package materials were modeled as temperature-dependent and elastic while the eutectic solder was modeled as temperature-dependent, elastic-plastic. The package and board assembly were subjected to a temperature increase (/spl Delta/T) of 85/spl deg/C with the assumption that the assembly is stress-free at room temperature. The results obtained from a three-dimensional 1/8th section model are compared with the results from 2-D plane-strain and plane-stress models and with 3-D "strip" models.
{"title":"Two and three-dimensional modeling of VSPA butt solder joints","authors":"R. Murphy, S. Sitaraman","doi":"10.1109/ECTC.1997.606211","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606211","url":null,"abstract":"The objective of this work is to develop two- and three-dimensional numerical models of VSPA, a new peripheral array package, and study its solder joint reliability. VSPA has multiple rows of butt-type leads around its periphery and is surface mounted on a standard FR-4 printed circuit board. The FR-4 and various package materials were modeled as temperature-dependent and elastic while the eutectic solder was modeled as temperature-dependent, elastic-plastic. The package and board assembly were subjected to a temperature increase (/spl Delta/T) of 85/spl deg/C with the assumption that the assembly is stress-free at room temperature. The results obtained from a three-dimensional 1/8th section model are compared with the results from 2-D plane-strain and plane-stress models and with 3-D \"strip\" models.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132167005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606260
D. Goodwill, R. Fan, R. B. Hooker, Yung-Cheng Lee, B. McComas, A. Mickelson, N. Morozova, D. Tomic
Optoelectronic technologies and devices have developed at a rapid rate, resulting in a large array of materials systems and structures that may be integrated into optoelectronic modules and subsystems. However, because these devices are made of a variety of materials systems, there is a fundamental mismatch between their optical modes. This mismatch affects coupling efficiency and sensitivity to tolerances. The coupling efficiency between laser diode arrays or OEIC components and single-mode fiber ribbons drops rapidly with increasing misalignment tolerance. There are trade-offs between the allowed minimum coupled power and the cost of establishing the required alignment. We are using a polymeric waveguide film that contains optical structures to transform optical mode patterns between components made from dissimilar materials systems. We demonstrate how tapered polymer waveguides may be used to match the laser mode to the fiber mode, resulting in a module with decreased alignment requirements for a given coupling efficiency Waveguides which simultaneously taper the mode both laterally and vertically have been designed. Waveguides with tapered mode profiles have been constructed using photobleaching of a guest/host dye/polymer system. Amoco 4212 polyimide doped with DCM dye was chosen as the waveguide material due to its good thermal stability and its simple processing. We present numerical results showing the variation of coupling efficiency into tapered waveguides with component misalignment. The alignment between components is established by self-aligned flip-chip solder bonding.
{"title":"Polymer tapered waveguides and flip-chip solder bonding as compatible technologies for efficient OEIC coupling","authors":"D. Goodwill, R. Fan, R. B. Hooker, Yung-Cheng Lee, B. McComas, A. Mickelson, N. Morozova, D. Tomic","doi":"10.1109/ECTC.1997.606260","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606260","url":null,"abstract":"Optoelectronic technologies and devices have developed at a rapid rate, resulting in a large array of materials systems and structures that may be integrated into optoelectronic modules and subsystems. However, because these devices are made of a variety of materials systems, there is a fundamental mismatch between their optical modes. This mismatch affects coupling efficiency and sensitivity to tolerances. The coupling efficiency between laser diode arrays or OEIC components and single-mode fiber ribbons drops rapidly with increasing misalignment tolerance. There are trade-offs between the allowed minimum coupled power and the cost of establishing the required alignment. We are using a polymeric waveguide film that contains optical structures to transform optical mode patterns between components made from dissimilar materials systems. We demonstrate how tapered polymer waveguides may be used to match the laser mode to the fiber mode, resulting in a module with decreased alignment requirements for a given coupling efficiency Waveguides which simultaneously taper the mode both laterally and vertically have been designed. Waveguides with tapered mode profiles have been constructed using photobleaching of a guest/host dye/polymer system. Amoco 4212 polyimide doped with DCM dye was chosen as the waveguide material due to its good thermal stability and its simple processing. We present numerical results showing the variation of coupling efficiency into tapered waveguides with component misalignment. The alignment between components is established by self-aligned flip-chip solder bonding.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"358 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116132896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606302
L. Eyman, G. Kromann
An experimental study was performed to investigate various heat sinks and attach methods commercially available for the high-performance 119-lead plastic ball grid array (PBGA) package. Attach methods investigated in this study include a pressure-sensitive adhesive, mechanical clips, and thermally conductive adhesives. This work will show the effects of heat sink attach methods on the package structural integrity and solder ball interconnect reliability. This work is necessary to better provide total solutions for customers who will need to dissipate high levels of power from this package. The heat sinks were attached to the 119-lead PBGA packages which were mounted on multi-layer printed-circuit boards. These assemblies were then subjected to accelerated-life testing (ALT) using air-to-air thermal cycling between 0/spl deg/C and 100/spl deg/C to determine the effect of attaching heat sinks to the packages on the electrical reliability of the solder joint connection. Besides interconnect reliability, ALT was used to determine the effect of thermal cycling on the reliability of the heat sink attach mechanism. The heat sink attach mechanisms were tested by three different methods. The first was to simply observe the heat sinks to see if they fall off during thermal cycling. Mechanical shock tests then were performed using a package drop tester. Samples that underwent 1000, 2000, and 11400 thermal cycles, as well as no thermal cycling, were subjected to this test. Finally, shear strength tests using a constant strain-rate mechanical testing machine were performed on the packages with heat sinks attached using adhesives. Several modes of failure appeared in the experiments. These failures included extremely low interconnect life in thermal cycling, heat sink detachment during drop tests and during thermal cycling, and low adhesion strength in shear tests. While some attachment methods were obviously not suitable, others provided robust solutions to the heat sink attachment problem.
{"title":"Investigation of heat sink attach methodologies and the effects on package structural integrity and interconnect reliability of the 119-lead plastic ball grid array","authors":"L. Eyman, G. Kromann","doi":"10.1109/ECTC.1997.606302","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606302","url":null,"abstract":"An experimental study was performed to investigate various heat sinks and attach methods commercially available for the high-performance 119-lead plastic ball grid array (PBGA) package. Attach methods investigated in this study include a pressure-sensitive adhesive, mechanical clips, and thermally conductive adhesives. This work will show the effects of heat sink attach methods on the package structural integrity and solder ball interconnect reliability. This work is necessary to better provide total solutions for customers who will need to dissipate high levels of power from this package. The heat sinks were attached to the 119-lead PBGA packages which were mounted on multi-layer printed-circuit boards. These assemblies were then subjected to accelerated-life testing (ALT) using air-to-air thermal cycling between 0/spl deg/C and 100/spl deg/C to determine the effect of attaching heat sinks to the packages on the electrical reliability of the solder joint connection. Besides interconnect reliability, ALT was used to determine the effect of thermal cycling on the reliability of the heat sink attach mechanism. The heat sink attach mechanisms were tested by three different methods. The first was to simply observe the heat sinks to see if they fall off during thermal cycling. Mechanical shock tests then were performed using a package drop tester. Samples that underwent 1000, 2000, and 11400 thermal cycles, as well as no thermal cycling, were subjected to this test. Finally, shear strength tests using a constant strain-rate mechanical testing machine were performed on the packages with heat sinks attached using adhesives. Several modes of failure appeared in the experiments. These failures included extremely low interconnect life in thermal cycling, heat sink detachment during drop tests and during thermal cycling, and low adhesion strength in shear tests. While some attachment methods were obviously not suitable, others provided robust solutions to the heat sink attachment problem.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115396868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606238
R. Fillion, B. Burdick, D. Shaddock, P. Piacente
An increasing number of electronic designers, fabricators and users see Chip Scale Packaging (CSP) as a way to obtain the benefits foreseen in multichip packaging and Chip-on-Board (COB) without the problems and limitations currently associated with each. The Chip-on-Flex (COF) multichip packaging technology has been demonstrated to be applicable to single chip packages that meet chip scale packaging goals. This paper looks at the Chip-on-Flex Chip Scale technology and addresses issues including the process, structure, assembly, yields and reliability.
{"title":"Chip scale packaging using chip-on-flex technology","authors":"R. Fillion, B. Burdick, D. Shaddock, P. Piacente","doi":"10.1109/ECTC.1997.606238","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606238","url":null,"abstract":"An increasing number of electronic designers, fabricators and users see Chip Scale Packaging (CSP) as a way to obtain the benefits foreseen in multichip packaging and Chip-on-Board (COB) without the problems and limitations currently associated with each. The Chip-on-Flex (COF) multichip packaging technology has been demonstrated to be applicable to single chip packages that meet chip scale packaging goals. This paper looks at the Chip-on-Flex Chip Scale technology and addresses issues including the process, structure, assembly, yields and reliability.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"203 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115563611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606292
P. Simpson
This overview paper outlines the areas of future semiconductor packaging challenge for the dynamic telecommunications industry. The declining cost of both bandwidth and digital computing coupled with deregulation and the opening of global markets has created a wealth of business opportunities for new and established competitors. All network sectors are searching for methods to increase performance, reliability and functional density while cost reducing the manufacturing process. Achieving this goal requires innovation in system architecture and software, semiconductors, optoelectronics and interconnect technologies. This paper focuses on the link between future network trends and the semiconductor packaging technology needed to serve the future telecom industry.
{"title":"Semiconductor packaging for the telecommunications industry","authors":"P. Simpson","doi":"10.1109/ECTC.1997.606292","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606292","url":null,"abstract":"This overview paper outlines the areas of future semiconductor packaging challenge for the dynamic telecommunications industry. The declining cost of both bandwidth and digital computing coupled with deregulation and the opening of global markets has created a wealth of business opportunities for new and established competitors. All network sectors are searching for methods to increase performance, reliability and functional density while cost reducing the manufacturing process. Achieving this goal requires innovation in system architecture and software, semiconductors, optoelectronics and interconnect technologies. This paper focuses on the link between future network trends and the semiconductor packaging technology needed to serve the future telecom industry.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121738796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606154
M. Ko, Myungwhan Kim, Dongsuk Shin, Inhee Lim, Myungsun Moon, Yongjoon Park
High loading of filler is known as an effective method for lowering the moisture absorption of the encapsulating compound since the filler itself does not absorb moisture. This also significantly increases the mechanical strength of the cured compound at reflow temperature. However, the detailed effect of the filler on the characteristic of the encapsulating compound was not fully disclosed. In this paper, the encapsulating compounds filled with an amorphous silica were prepared to study their characteristics relating to the reliability of an IC package and its workability. We have investigated the effect of the filler size and shape on the flowability of the compound. Both ultra fine and more spherical shaped filler are very effective to increase the spiral flow. We have also examined the properties of the encapsulating compound containing the filler chemically modified with the different silanes. The study reveals that the modification of the filler with reactive silane chemicals has a great influence on the properties of the compound including the mechanical strength, flowability, the flash/bleed and the shelf life. So, the proper modification of the filler is critical for balancing the reliability and moldability of an IC package.
{"title":"The effect of filler on the properties of molding compounds and their moldability","authors":"M. Ko, Myungwhan Kim, Dongsuk Shin, Inhee Lim, Myungsun Moon, Yongjoon Park","doi":"10.1109/ECTC.1997.606154","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606154","url":null,"abstract":"High loading of filler is known as an effective method for lowering the moisture absorption of the encapsulating compound since the filler itself does not absorb moisture. This also significantly increases the mechanical strength of the cured compound at reflow temperature. However, the detailed effect of the filler on the characteristic of the encapsulating compound was not fully disclosed. In this paper, the encapsulating compounds filled with an amorphous silica were prepared to study their characteristics relating to the reliability of an IC package and its workability. We have investigated the effect of the filler size and shape on the flowability of the compound. Both ultra fine and more spherical shaped filler are very effective to increase the spiral flow. We have also examined the properties of the encapsulating compound containing the filler chemically modified with the different silanes. The study reveals that the modification of the filler with reactive silane chemicals has a great influence on the properties of the compound including the mechanical strength, flowability, the flash/bleed and the shelf life. So, the proper modification of the filler is critical for balancing the reliability and moldability of an IC package.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123610366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606186
F. Wu, J. Lau, K. Chen
NuBGA is a low cost, single core, two-metal layer, cavity down plastic ball grid array package. With special design concepts, NuBGA provides electrical and thermal enhancements for electronic packaging applications. In this paper, the concepts of these innovative designs are briefly described. Thermal resistance of junction to air is investigated first by finite element simulations, and the results are then compared to experimental measurements. Thermal measurements are carried out for both with and without heat sink attachment. Geometric dependence of thermal resistance on structural parameters such as thickness of the copper heat spreader and organic substrate, power and ground planes in print circuit board, and the size of PCB are also discussed.
{"title":"Thermal evaluation of a cost-effective plastic ball grid array package-NuBGA","authors":"F. Wu, J. Lau, K. Chen","doi":"10.1109/ECTC.1997.606186","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606186","url":null,"abstract":"NuBGA is a low cost, single core, two-metal layer, cavity down plastic ball grid array package. With special design concepts, NuBGA provides electrical and thermal enhancements for electronic packaging applications. In this paper, the concepts of these innovative designs are briefly described. Thermal resistance of junction to air is investigated first by finite element simulations, and the results are then compared to experimental measurements. Thermal measurements are carried out for both with and without heat sink attachment. Geometric dependence of thermal resistance on structural parameters such as thickness of the copper heat spreader and organic substrate, power and ground planes in print circuit board, and the size of PCB are also discussed.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121531993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606264
A. Dansky, H.H. Smith, P. Williams
A methodology based on closed form expressions and 3D capacitance extraction is used to predict noise and timing impact due to line to line coupling. In this paper, details of the methodology described include the quantification of closed form expressions used for noise voltage prediction, assumptions made to factor in uncertainties of the coupling topology and the databases used to improve the accuracy of this approach. A sophisticated 3D capacitance extraction process is also discussed in some detail. Other issues such as the timing impact due to noise are also examined by including additional equations which relate the delay adjustment due to the total noise for each net with minimal timing margin. Finally, a statistical summary of the number of nets being analyzed at the chip level, with associated pertinent parameters such as coupling coefficients and coupled segment information is also shown. Other details as macro coupled noise analysis are discussed in context to the limitation of the global methodology described with recommendations for future work in this area. Such an approach uniquely relates complex issues of on-chip noise prediction with sophisticated database manipulation and sound engineering judgement to provide a comprehensive solution to the problem at hand.
{"title":"On-chip coupled noise analysis of a high performance S/390 microprocessor","authors":"A. Dansky, H.H. Smith, P. Williams","doi":"10.1109/ECTC.1997.606264","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606264","url":null,"abstract":"A methodology based on closed form expressions and 3D capacitance extraction is used to predict noise and timing impact due to line to line coupling. In this paper, details of the methodology described include the quantification of closed form expressions used for noise voltage prediction, assumptions made to factor in uncertainties of the coupling topology and the databases used to improve the accuracy of this approach. A sophisticated 3D capacitance extraction process is also discussed in some detail. Other issues such as the timing impact due to noise are also examined by including additional equations which relate the delay adjustment due to the total noise for each net with minimal timing margin. Finally, a statistical summary of the number of nets being analyzed at the chip level, with associated pertinent parameters such as coupling coefficients and coupled segment information is also shown. Other details as macro coupled noise analysis are discussed in context to the limitation of the global methodology described with recommendations for future work in this area. Such an approach uniquely relates complex issues of on-chip noise prediction with sophisticated database manipulation and sound engineering judgement to provide a comprehensive solution to the problem at hand.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128697507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606254
R. Natarajan, J. Dougherty
Recent trend in integrated ceramics is to have a 3-dimensional integration of passive components onto the low permittivity dielectric substrate to achieve a monolithic multilayer ceramic (MMC) substrate. MMC substrates offer significant gain in both circuit density and device hermiticity leading to increased reliability and low cost packages. Low-temperature glass-ceramic based low K tapes have been demonstrated to have good compatibility with silver metallization and resistor inks. To push the level of passive component integration one step forward, we studied the materials compatibility and co-firing aspects of low K tapes with high dielectric constant Pb-based relaxer materials. Li salt addition to high K ceramic tape was found to be effective in reducing the sintering temperature to match with that of low K tape. It also improved the dielectric properties and, most importantly, gave a wider processing window for the high K material. This paper describes the optimization of the high K tape casting process such as slurry preparation, rheology, solid content, tape release, lamination, and shrinkage matching with the low-K substrate. This paper also demonstrates the successful integration of high and low K materials.
{"title":"Material compatibility and dielectric properties of co-fired high and low dielectric constant ceramic packages","authors":"R. Natarajan, J. Dougherty","doi":"10.1109/ECTC.1997.606254","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606254","url":null,"abstract":"Recent trend in integrated ceramics is to have a 3-dimensional integration of passive components onto the low permittivity dielectric substrate to achieve a monolithic multilayer ceramic (MMC) substrate. MMC substrates offer significant gain in both circuit density and device hermiticity leading to increased reliability and low cost packages. Low-temperature glass-ceramic based low K tapes have been demonstrated to have good compatibility with silver metallization and resistor inks. To push the level of passive component integration one step forward, we studied the materials compatibility and co-firing aspects of low K tapes with high dielectric constant Pb-based relaxer materials. Li salt addition to high K ceramic tape was found to be effective in reducing the sintering temperature to match with that of low K tape. It also improved the dielectric properties and, most importantly, gave a wider processing window for the high K material. This paper describes the optimization of the high K tape casting process such as slurry preparation, rheology, solid content, tape release, lamination, and shrinkage matching with the low-K substrate. This paper also demonstrates the successful integration of high and low K materials.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129891509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-05-18DOI: 10.1109/ECTC.1997.606231
E. Pennings
It is the purpose of this paper to investigate the challenges that are posed to optoelectronic packaging by WDM. The main thrust of this paper is to review two key components of WDM systems, i.e. the wavelength (de)multiplexer and the WDM laser source, and to compare an integrated optoelectronic approach versus a hybrid or modular approach. This allows us to compare different alternatives and provides insight into the relevant packaging issues as well. The paper starts with a review of network and component trends, an analysis of the WDM market, and a discussion on optoelectronic integration issues. Conclusions are presented at the end.
{"title":"Challenges in optoelectronic packaging for high performance WDM networks","authors":"E. Pennings","doi":"10.1109/ECTC.1997.606231","DOIUrl":"https://doi.org/10.1109/ECTC.1997.606231","url":null,"abstract":"It is the purpose of this paper to investigate the challenges that are posed to optoelectronic packaging by WDM. The main thrust of this paper is to review two key components of WDM systems, i.e. the wavelength (de)multiplexer and the WDM laser source, and to compare an integrated optoelectronic approach versus a hybrid or modular approach. This allows us to compare different alternatives and provides insight into the relevant packaging issues as well. The paper starts with a review of network and component trends, an analysis of the WDM market, and a discussion on optoelectronic integration issues. Conclusions are presented at the end.","PeriodicalId":339633,"journal":{"name":"1997 Proceedings 47th Electronic Components and Technology Conference","volume":"03 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130997594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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