Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746251
Feng Yi, Xiaobo Wu
A novel coefficient automatic calculation (CAC) method for Sinc filter is proposed. Using CAC method, filter coefficients at full accuracy could be accessed with state transition and accumulator chain, without any coefficients storage. The illustrated method is an alternative to standard cascaded integrators and comb (CIC) approach and reaches maximum 41% power saving at cases. The performances of the proposed CAC and CIC approach are compared for general cases under different filter orders and decimation factors. Comparison shows that when filter order is low, the proposed CAC approach could be preferable for that in this case its power dissipation is much lower than CIC while keeping the acceptable area. All synthesis results are obtained under supply voltage of 1.62 V using TSMC 0.18 mum CMOS technology.
{"title":"A novel coefficient automatic calculation method for sinc filter in sigma-delta ADCs","authors":"Feng Yi, Xiaobo Wu","doi":"10.1109/APCCAS.2008.4746251","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746251","url":null,"abstract":"A novel coefficient automatic calculation (CAC) method for Sinc filter is proposed. Using CAC method, filter coefficients at full accuracy could be accessed with state transition and accumulator chain, without any coefficients storage. The illustrated method is an alternative to standard cascaded integrators and comb (CIC) approach and reaches maximum 41% power saving at cases. The performances of the proposed CAC and CIC approach are compared for general cases under different filter orders and decimation factors. Comparison shows that when filter order is low, the proposed CAC approach could be preferable for that in this case its power dissipation is much lower than CIC while keeping the acceptable area. All synthesis results are obtained under supply voltage of 1.62 V using TSMC 0.18 mum CMOS technology.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123063014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746129
Jinguo Liu, Shugen Ma, Yuechao Wang, Bin Li, Cong Wang
In this paper, we present a four-layered representing architecture for the configurations of a link-type reconfigurable mobile robot. Decimal numbers are used to represent all these possibilities in joint space. Binary codes are introduced to represent the links with consideration of adjacent interventions. To find out all the mobile configurations completely and accurately, configuration matrices are proposed to represent the configurations physically and to detect the multi-module interventions. Lastly, we take a three-module self-reconfigurable robot, AMOEBA-I, as an example to validate the proposed four-layered approach.
{"title":"Configuration representation of a link-type self-reconfigurable mobile robot","authors":"Jinguo Liu, Shugen Ma, Yuechao Wang, Bin Li, Cong Wang","doi":"10.1109/APCCAS.2008.4746129","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746129","url":null,"abstract":"In this paper, we present a four-layered representing architecture for the configurations of a link-type reconfigurable mobile robot. Decimal numbers are used to represent all these possibilities in joint space. Binary codes are introduced to represent the links with consideration of adjacent interventions. To find out all the mobile configurations completely and accurately, configuration matrices are proposed to represent the configurations physically and to detect the multi-module interventions. Lastly, we take a three-module self-reconfigurable robot, AMOEBA-I, as an example to validate the proposed four-layered approach.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116664269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746276
Wei-chin Lee, Yao Li, Chen-Yi Lee
In this paper, a VLC decoder supporting to decode coefficient data in blocks of MPEG-2 and CAVLC in H.264 is presented. To achieve programmability of the VLC decoder, a memory-based architecture with improved memory efficiency is proposed. Group-based look-up table (LUT) algorithm is extended to multi-table merging (MTM) which extracts redundancy of groups further. With multi-table merging algorithm, all coding tables are integrated into memory more efficiently. While the memory access may lead to much power consumption, a low-power scheme is proposed to reduce memory access. The distributed cache is adopted to save power and improve the decoding throughput as well. Simulation results show that the cache with replacement method can reduce about 60% ~ 95% memory accesses.
{"title":"Design of a memory-based VLC decoder for portable video applications","authors":"Wei-chin Lee, Yao Li, Chen-Yi Lee","doi":"10.1109/APCCAS.2008.4746276","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746276","url":null,"abstract":"In this paper, a VLC decoder supporting to decode coefficient data in blocks of MPEG-2 and CAVLC in H.264 is presented. To achieve programmability of the VLC decoder, a memory-based architecture with improved memory efficiency is proposed. Group-based look-up table (LUT) algorithm is extended to multi-table merging (MTM) which extracts redundancy of groups further. With multi-table merging algorithm, all coding tables are integrated into memory more efficiently. While the memory access may lead to much power consumption, a low-power scheme is proposed to reduce memory access. The distributed cache is adopted to save power and improve the decoding throughput as well. Simulation results show that the cache with replacement method can reduce about 60% ~ 95% memory accesses.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125027307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746308
L. Po, K. Ng, K. Wong, K. Cheung
Easily trapped in local minima is one of the well-known problems in search point pattern based fast block motion estimation algorithms. This problem is especially serious in one-at-a-time search (OTS) and block-based gradient descent search (BBGDS). These two algorithms can provide very high speedup ratio but with low robustness in prediction accuracy especially for sequences with complex motions. Multi-path search (MPS) using more than one path have been proposed to improve the robustness of BBGDS, but the computational requirement is much increased. To tackle this problem, a novel multi-directional gradient descent search (MDGDS) is proposed in this paper with use of multiple OTSs in eight directions. Basically, the proposed MDGDS performs eight one-dimensional gradient descent searches on the error surface and therefore can trace to the global minimum more efficiently. Experimental results show that a significant improvement in computation reduction can be achieved as compared with well-known fast block motion estimation algorithms.
{"title":"Multi-direction search algorithm for block-based motion estimation","authors":"L. Po, K. Ng, K. Wong, K. Cheung","doi":"10.1109/APCCAS.2008.4746308","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746308","url":null,"abstract":"Easily trapped in local minima is one of the well-known problems in search point pattern based fast block motion estimation algorithms. This problem is especially serious in one-at-a-time search (OTS) and block-based gradient descent search (BBGDS). These two algorithms can provide very high speedup ratio but with low robustness in prediction accuracy especially for sequences with complex motions. Multi-path search (MPS) using more than one path have been proposed to improve the robustness of BBGDS, but the computational requirement is much increased. To tackle this problem, a novel multi-directional gradient descent search (MDGDS) is proposed in this paper with use of multiple OTSs in eight directions. Basically, the proposed MDGDS performs eight one-dimensional gradient descent searches on the error surface and therefore can trace to the global minimum more efficiently. Experimental results show that a significant improvement in computation reduction can be achieved as compared with well-known fast block motion estimation algorithms.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126080636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746223
T. Chakraborty, S. Chakrabarti
In this paper we present a novel technique to reduce silicon area of 128 point, 1 GSPS FFT architecture called as Mixed Radix Multi-path Delay Feedback (MRMDF) architecture proposed in. The architecture has been targeted 180 nm CMOS technology for fabrication. The design is intended to comply with ECMA-368 standard, which is one of the leading MB-OFDM standards for UWB application. The major bottleneck of pipelined FFT architectures is complex multipliers. For high throughput application like UWB, parallel-pipelined architecture is the most suitable choice of design. As a result one can not share complex multipliers much and hence the silicon area becomes quite huge. The proposed technique increases the utilization factor of the elemental blocks of the complex constant multipliers proposed in and hence reduces its area by quite a significant amount of 7.3% i.e. around 193 k sq-micron, without any performance degradation.
{"title":"A reduced area 1 GSPS FFT design using MRMDF architecture for UWB communication","authors":"T. Chakraborty, S. Chakrabarti","doi":"10.1109/APCCAS.2008.4746223","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746223","url":null,"abstract":"In this paper we present a novel technique to reduce silicon area of 128 point, 1 GSPS FFT architecture called as Mixed Radix Multi-path Delay Feedback (MRMDF) architecture proposed in. The architecture has been targeted 180 nm CMOS technology for fabrication. The design is intended to comply with ECMA-368 standard, which is one of the leading MB-OFDM standards for UWB application. The major bottleneck of pipelined FFT architectures is complex multipliers. For high throughput application like UWB, parallel-pipelined architecture is the most suitable choice of design. As a result one can not share complex multipliers much and hence the silicon area becomes quite huge. The proposed technique increases the utilization factor of the elemental blocks of the complex constant multipliers proposed in and hence reduces its area by quite a significant amount of 7.3% i.e. around 193 k sq-micron, without any performance degradation.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126124127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746200
I. Lok, M. Wong
This paper presents a combination of a quasiresonant dc-link (QRDCL) inverter and a generalized three-level inverter. QRDCL inverter can decrease the dc-link voltage to zero in order to provide a zero voltage condition for the power devices. The voltage stresses of the power devices can be released and the switching losses of the inverter can be reduced under zero-voltage switching (ZVS). Generalized multilevel inverter topology provides an alternative way in high level inverter implementation. The generalized multilevel inverter is constructed by several basic cells which enable a higher flexibility in extending the levels of inverter, and moreover it gives the inverter a self voltage balancing ability without any assistance from extra circuits. Control strategy of a generalized three-level QRDCL inverter is proposed. Switching losses of the inverters are also presented to prove the feasibility of a generalized three-level QRDCL inverter.
{"title":"Evaluation of quasi-resonant dc-link technique on generalized three-level inverter","authors":"I. Lok, M. Wong","doi":"10.1109/APCCAS.2008.4746200","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746200","url":null,"abstract":"This paper presents a combination of a quasiresonant dc-link (QRDCL) inverter and a generalized three-level inverter. QRDCL inverter can decrease the dc-link voltage to zero in order to provide a zero voltage condition for the power devices. The voltage stresses of the power devices can be released and the switching losses of the inverter can be reduced under zero-voltage switching (ZVS). Generalized multilevel inverter topology provides an alternative way in high level inverter implementation. The generalized multilevel inverter is constructed by several basic cells which enable a higher flexibility in extending the levels of inverter, and moreover it gives the inverter a self voltage balancing ability without any assistance from extra circuits. Control strategy of a generalized three-level QRDCL inverter is proposed. Switching losses of the inverters are also presented to prove the feasibility of a generalized three-level QRDCL inverter.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123427749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746157
Chih-Hui Ting, Juinn-Dar Huang, Yu-Hsiang Kao
In this paper, we exploit the concept of sequential way access to reduce the number of ways being activated on each access of set-associative cache for low energy consumption while maintaining performance. The proposed architecture accesses each way in sequence, and then eliminates subsequent accesses if a hit is detected. It features smart cache placement and replacement policies to minimize the number of required access cycles. It can also reduce the heavy fanout load of the hit-signal, which suppresses the possible increase of cache cycle time due to more complicated cache control mechanism. The experimental results show that a 32 KB 2-way sequential way-access set-associative cache reduces the energy consumption by 24% compared against a conventional 2-way set-associative cache with the same size at virtually no performance loss.
{"title":"Cycle-time-aware sequential way-access set-associative cache for low energy consumption","authors":"Chih-Hui Ting, Juinn-Dar Huang, Yu-Hsiang Kao","doi":"10.1109/APCCAS.2008.4746157","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746157","url":null,"abstract":"In this paper, we exploit the concept of sequential way access to reduce the number of ways being activated on each access of set-associative cache for low energy consumption while maintaining performance. The proposed architecture accesses each way in sequence, and then eliminates subsequent accesses if a hit is detected. It features smart cache placement and replacement policies to minimize the number of required access cycles. It can also reduce the heavy fanout load of the hit-signal, which suppresses the possible increase of cache cycle time due to more complicated cache control mechanism. The experimental results show that a 32 KB 2-way sequential way-access set-associative cache reduces the energy consumption by 24% compared against a conventional 2-way set-associative cache with the same size at virtually no performance loss.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126656691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746156
D. Sheng, Ching-Che Chung, Chen-Yi Lee
In this paper, a programmable all-digital spread spectrum clock generator (ADSSCG) suitable for system-on-chip (SoC) applications with ultra-low-power capability is presented. Based on the timing constraint of system, the programmable ADSSCG can provide the suitable frequency spread ratio to obtain the optimal combination of timing deviation and EMI reduction for system applications. Besides, the proposed ADSSCG employs an ultra-low-power digitally controlled oscillator (DCO) to save overall power consumption to 560 muW (@400 MHz) and the peak EMI power reduction is large than 25 dB. In addition, the proposed ADSSCG can be implemented only with standard cells; as a result, the area can be saved without any passive component, and making it easily portable to different processes and very suitable for SoC applications.
{"title":"An all digital spread spectrum clock generator with programmable spread ratio for SoC applications","authors":"D. Sheng, Ching-Che Chung, Chen-Yi Lee","doi":"10.1109/APCCAS.2008.4746156","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746156","url":null,"abstract":"In this paper, a programmable all-digital spread spectrum clock generator (ADSSCG) suitable for system-on-chip (SoC) applications with ultra-low-power capability is presented. Based on the timing constraint of system, the programmable ADSSCG can provide the suitable frequency spread ratio to obtain the optimal combination of timing deviation and EMI reduction for system applications. Besides, the proposed ADSSCG employs an ultra-low-power digitally controlled oscillator (DCO) to save overall power consumption to 560 muW (@400 MHz) and the peak EMI power reduction is large than 25 dB. In addition, the proposed ADSSCG can be implemented only with standard cells; as a result, the area can be saved without any passive component, and making it easily portable to different processes and very suitable for SoC applications.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115084166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746215
Yun-rui Gong, Di He, Chen He, Ling-ge Jiang
The performances of pseudo-chaotic communication time-hopping UWB system with efficient modulation schemes are compared on the classic AWGN channel propagation and the realistic IEEE-UWB channel model. By employing different versions of modulation at the transmitters, the performances of an optimal receiver and a Rake receiver with various combining schemes are studied in this paper. The numerical results for several compared cases illustrate the tradeoff between transmitter diversity and receiver complexity. It is shown that the actual performance of the PAM-PCTH scheme can be better in both kinds of channel propagation. We also find that the PCTH-based UWB system with the Rake receiver has better performance than the conventional proposal for overcoming the multipath propagation effects in the UWB indoor environment.
{"title":"Efficient modulation on the performance of coherent receivers for pseudo-chaotic TH-UWB system","authors":"Yun-rui Gong, Di He, Chen He, Ling-ge Jiang","doi":"10.1109/APCCAS.2008.4746215","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746215","url":null,"abstract":"The performances of pseudo-chaotic communication time-hopping UWB system with efficient modulation schemes are compared on the classic AWGN channel propagation and the realistic IEEE-UWB channel model. By employing different versions of modulation at the transmitters, the performances of an optimal receiver and a Rake receiver with various combining schemes are studied in this paper. The numerical results for several compared cases illustrate the tradeoff between transmitter diversity and receiver complexity. It is shown that the actual performance of the PAM-PCTH scheme can be better in both kinds of channel propagation. We also find that the PCTH-based UWB system with the Rake receiver has better performance than the conventional proposal for overcoming the multipath propagation effects in the UWB indoor environment.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122906463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A voltage-controlled ring oscillator in 90 nm CMOS technology with ultra wide-band and low phase noise for digital TV-tuner is presented. By introducing pre-amplifying transistors to get novel four outputs delay stage, tuning range is greatly widened. Pre-charging transistors with optimized control method decrease phase noise without increasing parasitic capacitances. The oscillator can be operated from 38 MHz to 1.38 GHz, while worst phase noises are -107 dBc/Hz at 1 MHz offset and -85 dBc/Hz at 100 KHz offset in full frequency range. It maximally consumes 11.1 mA with 1.8 V supply voltage.
{"title":"A 90nm CMOS wide-band voltage-controlled ring oscillator for digital TV-tuner","authors":"Kai Yu, X. Zou, Jianming Lei, Guoyi Yu, Sizhen Li, Yunwu Chen","doi":"10.1109/APCCAS.2008.4746282","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746282","url":null,"abstract":"A voltage-controlled ring oscillator in 90 nm CMOS technology with ultra wide-band and low phase noise for digital TV-tuner is presented. By introducing pre-amplifying transistors to get novel four outputs delay stage, tuning range is greatly widened. Pre-charging transistors with optimized control method decrease phase noise without increasing parasitic capacitances. The oscillator can be operated from 38 MHz to 1.38 GHz, while worst phase noises are -107 dBc/Hz at 1 MHz offset and -85 dBc/Hz at 100 KHz offset in full frequency range. It maximally consumes 11.1 mA with 1.8 V supply voltage.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122519835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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