Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746067
D. Niu, Yongli Wang, Xiaoyong Ma
Safety management is one of the main components of project management. Regarding to power plant construction, safety management evaluation is useful for the construction unit to find the potential hazard source, do practical precautions and generalize lessons for the future. The purpose of this paper is to establish an evaluation model for safety management evaluation. In this paper, the method of principle component analysis were used to deal with the original indexes, it selects the factors which are important for power plant construction evaluation through the method to pre-process all the influenced factors. Based on the pre-processed method, the fuzzy neural network was adopted to establish an evaluation model and classify the evaluation result. This was a new thought for the fuzzy neural network to be used in safety management evaluation for power plant construction project.
{"title":"Power plant construction project safety management evaluation with fuzzy neural network model","authors":"D. Niu, Yongli Wang, Xiaoyong Ma","doi":"10.1109/APCCAS.2008.4746067","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746067","url":null,"abstract":"Safety management is one of the main components of project management. Regarding to power plant construction, safety management evaluation is useful for the construction unit to find the potential hazard source, do practical precautions and generalize lessons for the future. The purpose of this paper is to establish an evaluation model for safety management evaluation. In this paper, the method of principle component analysis were used to deal with the original indexes, it selects the factors which are important for power plant construction evaluation through the method to pre-process all the influenced factors. Based on the pre-processed method, the fuzzy neural network was adopted to establish an evaluation model and classify the evaluation result. This was a new thought for the fuzzy neural network to be used in safety management evaluation for power plant construction project.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"51 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125798515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746008
W. Lei, M. Dong, Jun Shi, Binbin Fu
This paper presents a novel approach to the intelligent heart rhythm recognition, via integration of Hermite based orthogonal polynomial decomposition (OPD) and support vector machines (SVMs) classification. In regard to feature characterization, the orthogonal transformation based on Hermite basis polynomials is proposed to characterize the morphological features of ECG data. For the goal of multi-class ECG classification, the one-against-all (OAA) strategy is applied to reduce the multi-class SVMs into several binary SVMs. In this study, most of the heart rhythm type in MIT-BIH arrhythmia database is concerned. The numerical result shows out the good performance of proposed automatic interpreter in reliability and accuracy.
{"title":"Automatic ECG interpretation via morphological feature extraction and SVM inference nets","authors":"W. Lei, M. Dong, Jun Shi, Binbin Fu","doi":"10.1109/APCCAS.2008.4746008","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746008","url":null,"abstract":"This paper presents a novel approach to the intelligent heart rhythm recognition, via integration of Hermite based orthogonal polynomial decomposition (OPD) and support vector machines (SVMs) classification. In regard to feature characterization, the orthogonal transformation based on Hermite basis polynomials is proposed to characterize the morphological features of ECG data. For the goal of multi-class ECG classification, the one-against-all (OAA) strategy is applied to reduce the multi-class SVMs into several binary SVMs. In this study, most of the heart rhythm type in MIT-BIH arrhythmia database is concerned. The numerical result shows out the good performance of proposed automatic interpreter in reliability and accuracy.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125984266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746322
Yong-Woo Kim, Jin-Ku Kang
This paper presents a design of 8B/10B encoder with a modified coding table. The proposed encoder has been designed based on a reduced coding table with a modified disparity control block. After being synthesized using CMOS 0.18 mum process, the proposed encoder shows the operating frequency of 343 MHz and occupies the chip area of 1886 mum2 with 189 logic gates. It consumes 2.74 mW power. Compared to conventional approaches, the operating frequency is improved by 25.6% and chip area is decreased to 43%.
{"title":"An 8B/10B encoder with a modified coding table","authors":"Yong-Woo Kim, Jin-Ku Kang","doi":"10.1109/APCCAS.2008.4746322","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746322","url":null,"abstract":"This paper presents a design of 8B/10B encoder with a modified coding table. The proposed encoder has been designed based on a reduced coding table with a modified disparity control block. After being synthesized using CMOS 0.18 mum process, the proposed encoder shows the operating frequency of 343 MHz and occupies the chip area of 1886 mum2 with 189 logic gates. It consumes 2.74 mW power. Compared to conventional approaches, the operating frequency is improved by 25.6% and chip area is decreased to 43%.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122234259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4745989
M. R. Meher, C. Jong, Chip-Hong Chang
This paper presents a new approach to serial/parallel multiplier design by using parallel 1psilas counters to accumulate the binary partial product bits. The 1psilas in each column of the partial product matrix due to the serially input operands are accumulated using a serial T-flip flop (TFF) counter. Consequently, the column height is reduced from N to [log2 N]+1. This logarithmic reduction results in a very small carry save adder (CSA) array or tree required before the two final summands are added up to obtain the final product. The counters can be clocked at very high frequency (around 1.5 GHz as dictated mainly by the TFF propagation delay) and the accumulation frequency is independent of the operand size. The proposed accumulation method achieves 33%, 38%, 43% gain in speed respectively for 31, 63, 127 operands accumulators and on average 42% reduction in power consumption over CSA based accumulation implemented in 0.18 mum CMOS technology.
{"title":"High-speed and low-power serial accumulator for serial/parallel multiplier","authors":"M. R. Meher, C. Jong, Chip-Hong Chang","doi":"10.1109/APCCAS.2008.4745989","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4745989","url":null,"abstract":"This paper presents a new approach to serial/parallel multiplier design by using parallel 1psilas counters to accumulate the binary partial product bits. The 1psilas in each column of the partial product matrix due to the serially input operands are accumulated using a serial T-flip flop (TFF) counter. Consequently, the column height is reduced from N to [log2 N]+1. This logarithmic reduction results in a very small carry save adder (CSA) array or tree required before the two final summands are added up to obtain the final product. The counters can be clocked at very high frequency (around 1.5 GHz as dictated mainly by the TFF propagation delay) and the accumulation frequency is independent of the operand size. The proposed accumulation method achieves 33%, 38%, 43% gain in speed respectively for 31, 63, 127 operands accumulators and on average 42% reduction in power consumption over CSA based accumulation implemented in 0.18 mum CMOS technology.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131565335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746056
Dae-Yeon Kim, Ki-Hun Han, Yung-Lyul Lee
To reduce spatial redundancies in intra coding, Intra 4times4 mode provides nine directional prediction modes for every 4times4 block. In this paper, an adaptive intra mode bit skip method is proposed to improve coding efficiency in intra coding. The proposed method improves coding efficiency and reduces encoding complexity. Experimental results show that the average bit-rate reduction of 2.86% and 6.58% are achieved at the medium bitrate and low bitrate, respectively. In addition to that, encoding complexity is saved about 42% at the QP values of 27 and 32.
{"title":"Adaptive intra mode bit skip in intra coding","authors":"Dae-Yeon Kim, Ki-Hun Han, Yung-Lyul Lee","doi":"10.1109/APCCAS.2008.4746056","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746056","url":null,"abstract":"To reduce spatial redundancies in intra coding, Intra 4times4 mode provides nine directional prediction modes for every 4times4 block. In this paper, an adaptive intra mode bit skip method is proposed to improve coding efficiency in intra coding. The proposed method improves coding efficiency and reduces encoding complexity. Experimental results show that the average bit-rate reduction of 2.86% and 6.58% are achieved at the medium bitrate and low bitrate, respectively. In addition to that, encoding complexity is saved about 42% at the QP values of 27 and 32.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131831121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746062
G. Izuta
In this paper we investigate the asymptotic stability of a generalised 2-dimensional (2D) digital Roesser type filter, which is expressed by delayed partial difference equations. The work is carried out on the grounds of a doubly congruence transformation and the Lagrange method approach, which is applied on the transformed system to provide the stability conditions. It is worth pointing out that the reports on application of the Lagrange method on even non-delayed discrete systems is not vast as the z-transform and energy method. Finally, we note here that this paper is concerned with the stability analysis of delayed systems, which is still an emerging research field.
{"title":"Stability analysis of a generalised 2D digital Roesser type systems via lagrange method","authors":"G. Izuta","doi":"10.1109/APCCAS.2008.4746062","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746062","url":null,"abstract":"In this paper we investigate the asymptotic stability of a generalised 2-dimensional (2D) digital Roesser type filter, which is expressed by delayed partial difference equations. The work is carried out on the grounds of a doubly congruence transformation and the Lagrange method approach, which is applied on the transformed system to provide the stability conditions. It is worth pointing out that the reports on application of the Lagrange method on even non-delayed discrete systems is not vast as the z-transform and energy method. Finally, we note here that this paper is concerned with the stability analysis of delayed systems, which is still an emerging research field.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129383795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746163
In-Gul Jang, Yong-Eun Kim, Yinan Xu, Jin-Gyun Chung
FFT/IFFT processor is one of the key components in the implementation of OFDM systems such as WiBro, DAB and UWB systems. Most of the researches on the implementation of FFT processors have focused on reducing the complexities of multipliers, memory and control circuits. In this paper, to reduce the register size required for IFFT, we propose a new IFFT design method based on a mapping method. By simulations, it is shown that the proposed IFFT design method achieves more than 60% area reduction and much SQNR (Signal-to-Quantization Noise Ration) gain compared with previous IFFT designs.
{"title":"Efficient IFFT design using mapping method","authors":"In-Gul Jang, Yong-Eun Kim, Yinan Xu, Jin-Gyun Chung","doi":"10.1109/APCCAS.2008.4746163","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746163","url":null,"abstract":"FFT/IFFT processor is one of the key components in the implementation of OFDM systems such as WiBro, DAB and UWB systems. Most of the researches on the implementation of FFT processors have focused on reducing the complexities of multipliers, memory and control circuits. In this paper, to reduce the register size required for IFFT, we propose a new IFFT design method based on a mapping method. By simulations, it is shown that the proposed IFFT design method achieves more than 60% area reduction and much SQNR (Signal-to-Quantization Noise Ration) gain compared with previous IFFT designs.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125239244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746086
Yijiang Shen, N. Wong, E. Lam
This paper reports on a numerical analysis of interconnect thermal profile with fourth-order accuracy in space. The interconnect thermal simulation is described in a partial differential equation (PDE), and solved by finite difference time domain (FDTD) techniques using a fourth-order approximation of the spatial partial derivative in the PDE. A recently developed numerically stable algorithm for inversion of block tridiagonal and banded matrices is applied when the thermal simulation is conducted using Crank-Nicolson method with fourth-order spatial accuracy. We have promising simulation results, showing that the proposed method can have more accurate temperature profile before reaching the steady state than the traditional menthols and the runtime is linearly proportional to the number of nodes.
{"title":"Interconnect thermal simulation with higher order spatial accuracy","authors":"Yijiang Shen, N. Wong, E. Lam","doi":"10.1109/APCCAS.2008.4746086","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746086","url":null,"abstract":"This paper reports on a numerical analysis of interconnect thermal profile with fourth-order accuracy in space. The interconnect thermal simulation is described in a partial differential equation (PDE), and solved by finite difference time domain (FDTD) techniques using a fourth-order approximation of the spatial partial derivative in the PDE. A recently developed numerically stable algorithm for inversion of block tridiagonal and banded matrices is applied when the thermal simulation is conducted using Crank-Nicolson method with fourth-order spatial accuracy. We have promising simulation results, showing that the proposed method can have more accurate temperature profile before reaching the steady state than the traditional menthols and the runtime is linearly proportional to the number of nodes.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130825197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For a SOC communication architecture, an efficient arbitration algorithm to resolve contention schemes for managing simultaneous access requests to the shared communication resources are required to prevent system performance degradation.This paper presents the design and performance analysis of an arbiter with a hybrid arbitration algorithm. The hybrid arbitration algorithm contains static fixed priority algorithm in conjunction with dynamic algorithm to gain better system performance is described. The performance analysis for the various combinations of the arbitration algorithms under different traffic loads is simulated. The results indicate a better performance can be achieved as compared with the traditional arbitration assignment scheme. Based on the performance analysis, the hybrid arbitration can be custom-tuned to meet the design requirements. The implementation of the arbiter with hybrid arbitration scheme for system on chip applications is also explained. The reconfigurable arbiter was implemented by FPGA and synthesized by Synopsys design complier with a TSMC 0.18 mum cell library.
{"title":"A reconfigurable arbiter for SOC applications","authors":"Ching-Chien Yuan, Yu-Jung Huang, Shih-Jhe Lin, Kai-Hsiang Huang","doi":"10.1109/APCCAS.2008.4746123","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746123","url":null,"abstract":"For a SOC communication architecture, an efficient arbitration algorithm to resolve contention schemes for managing simultaneous access requests to the shared communication resources are required to prevent system performance degradation.This paper presents the design and performance analysis of an arbiter with a hybrid arbitration algorithm. The hybrid arbitration algorithm contains static fixed priority algorithm in conjunction with dynamic algorithm to gain better system performance is described. The performance analysis for the various combinations of the arbitration algorithms under different traffic loads is simulated. The results indicate a better performance can be achieved as compared with the traditional arbitration assignment scheme. Based on the performance analysis, the hybrid arbitration can be custom-tuned to meet the design requirements. The implementation of the arbiter with hybrid arbitration scheme for system on chip applications is also explained. The reconfigurable arbiter was implemented by FPGA and synthesized by Synopsys design complier with a TSMC 0.18 mum cell library.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130935170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746037
Mauro Santos, C. Pires, J. Guilherme, N. Horta
This paper describes some design challenges and trade-offs faced by CMOS integrated circuits and switched mode power supplies in a radiation environment as it is common in space applications. Circuit techniques to ensure radiation hardening are described. The power converter design constraints are identified and some solutions are suggested for a multiple output converter.
{"title":"Overview of radiation effects and design constraints off fully custom SMPS","authors":"Mauro Santos, C. Pires, J. Guilherme, N. Horta","doi":"10.1109/APCCAS.2008.4746037","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746037","url":null,"abstract":"This paper describes some design challenges and trade-offs faced by CMOS integrated circuits and switched mode power supplies in a radiation environment as it is common in space applications. Circuit techniques to ensure radiation hardening are described. The power converter design constraints are identified and some solutions are suggested for a multiple output converter.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131184958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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