Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746113
Hwang-Cherng Chow, Z. Hor
A new method to detect the power supply and ground noise (PSN) in ICs is proposed in this paper. We improve the conventional peak detector sample and hold circuits (PDSH) and apply them to detect the PSN. The maximum overshoot or undershoot noise will be both detected and held in a holding capacitor. This consequence enables the next processing circuit to operate conveniently without further speed restriction. The noise detector is verified able to detect 1 GHz PSN with the magnitude from 10% to 45% VDD within 5% error. As compared to the prior art, both the detection range and speed are improved significantly.
{"title":"A high performance peak detector sample and hold circuit for detecting power supply noise","authors":"Hwang-Cherng Chow, Z. Hor","doi":"10.1109/APCCAS.2008.4746113","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746113","url":null,"abstract":"A new method to detect the power supply and ground noise (PSN) in ICs is proposed in this paper. We improve the conventional peak detector sample and hold circuits (PDSH) and apply them to detect the PSN. The maximum overshoot or undershoot noise will be both detected and held in a holding capacitor. This consequence enables the next processing circuit to operate conveniently without further speed restriction. The noise detector is verified able to detect 1 GHz PSN with the magnitude from 10% to 45% VDD within 5% error. As compared to the prior art, both the detection range and speed are improved significantly.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133708183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746300
K. Kwok, Zhiping Lin, Yonghong Zeng
In multiple-input multiple-output (MIMO) communications systems, a crucial role is played by channel estimation as the accuracy of estimation will have a substantial effect on the overall system performance. In this paper we consider designing precoding matrices and blind channel estimation algorithms for MIMO single carrier with frequency domain equalization (MIMO-SC-FDE) systems. By deriving the relationship between the MIMO orthogonal frequency division multiplexing (MIMO-OFDM) and MIMO-SC-FDE, the theories for precoding and channel estimation for MIMO-OFDM can be directly used for MIMO-SC-FDE. Based on this, several new precoding matrices are designed and tested. The proposed precodings will not affect the power of the precoded block. Furthermore, fast algorithms are used for the implementation of the precoding and decoding.
{"title":"Precoded MIMO-SC-FDE and blind channel estimation","authors":"K. Kwok, Zhiping Lin, Yonghong Zeng","doi":"10.1109/APCCAS.2008.4746300","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746300","url":null,"abstract":"In multiple-input multiple-output (MIMO) communications systems, a crucial role is played by channel estimation as the accuracy of estimation will have a substantial effect on the overall system performance. In this paper we consider designing precoding matrices and blind channel estimation algorithms for MIMO single carrier with frequency domain equalization (MIMO-SC-FDE) systems. By deriving the relationship between the MIMO orthogonal frequency division multiplexing (MIMO-OFDM) and MIMO-SC-FDE, the theories for precoding and channel estimation for MIMO-OFDM can be directly used for MIMO-SC-FDE. Based on this, several new precoding matrices are designed and tested. The proposed precodings will not affect the power of the precoded block. Furthermore, fast algorithms are used for the implementation of the precoding and decoding.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132436357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746128
Fuming Sun, Xiaoying Li, Qin Wang, Chunlin Tang
Since the latest IC technology supports the integration of soft or hard CPU cores with dedicated logic on a single silicon chip, it leads FPGA into embedded system design and arouses the innovation of design methodology. In this paper, a general introduction of embedded system and the FPGA-based SOPC development are discussed. The FPGA-based embedded system can contain microprocessor IP cores and support embedded operating system. The mixed design flow is illustrated and a data transmitting/receiving converter between serial port and network interface is taken as a design example.
{"title":"FPGA-based embedded system design","authors":"Fuming Sun, Xiaoying Li, Qin Wang, Chunlin Tang","doi":"10.1109/APCCAS.2008.4746128","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746128","url":null,"abstract":"Since the latest IC technology supports the integration of soft or hard CPU cores with dedicated logic on a single silicon chip, it leads FPGA into embedded system design and arouses the innovation of design methodology. In this paper, a general introduction of embedded system and the FPGA-based SOPC development are discussed. The FPGA-based embedded system can contain microprocessor IP cores and support embedded operating system. The mixed design flow is illustrated and a data transmitting/receiving converter between serial port and network interface is taken as a design example.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133190821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746162
Gang Li, Chaogeng Huang, Jingyu Hua, Bin Huang
In this paper, based on a new parametrization of the input-balanced realizations a novel structure is proposed for implementation of 2nd order digital filters. Like the normalized lattice structure, it contains a Givens rotation. The expression of roundoff noise gain for this structure is derived. This proposed structure is simpler than the normalized structure. Though having the same number of structure parameters as that of the classical optimal state-space roundoff realizations, it can be implemented much more efficiently using the CORDIC techniques. Numerical examples show that the proposed structure also outperforms the normalized structure and the classical optimal state-space realizations in terms of minimizing roundoff noise.
{"title":"A novel structure for 2nd order digital filters","authors":"Gang Li, Chaogeng Huang, Jingyu Hua, Bin Huang","doi":"10.1109/APCCAS.2008.4746162","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746162","url":null,"abstract":"In this paper, based on a new parametrization of the input-balanced realizations a novel structure is proposed for implementation of 2nd order digital filters. Like the normalized lattice structure, it contains a Givens rotation. The expression of roundoff noise gain for this structure is derived. This proposed structure is simpler than the normalized structure. Though having the same number of structure parameters as that of the classical optimal state-space roundoff realizations, it can be implemented much more efficiently using the CORDIC techniques. Numerical examples show that the proposed structure also outperforms the normalized structure and the classical optimal state-space realizations in terms of minimizing roundoff noise.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"67 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133238424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746355
Yi-Mao Hsiao, T. Lo, Y. Chu, Shi-Wu Lo
In this paper we propose a low power technique named Power Block Manager (PBM) to reduce power consumption in various function units within a microprocessor. Power Block Manager considers each function block as an independent object. To disable running those function units which neither work nor affect the output results, the system can save the dynamic power dissipation. The PBM architecture involves three parts. The instruction type detector classifies the instructions. The power block table points out which power blocks can be turned on or off according to the instruction type. The scheduler arranges the power control signals to meet the pipelined system. We apply the PBM system to a 32-bit microprocessor named UniRISC which is designed by CCU SoC Center, and take three applications to examine the power. After the Post-Layout experiment, the processor with PBM system can save 20.1~30.2% power consumption.
{"title":"Low power 32-bit UniRISC with Power Block Manager","authors":"Yi-Mao Hsiao, T. Lo, Y. Chu, Shi-Wu Lo","doi":"10.1109/APCCAS.2008.4746355","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746355","url":null,"abstract":"In this paper we propose a low power technique named Power Block Manager (PBM) to reduce power consumption in various function units within a microprocessor. Power Block Manager considers each function block as an independent object. To disable running those function units which neither work nor affect the output results, the system can save the dynamic power dissipation. The PBM architecture involves three parts. The instruction type detector classifies the instructions. The power block table points out which power blocks can be turned on or off according to the instruction type. The scheduler arranges the power control signals to meet the pipelined system. We apply the PBM system to a 32-bit microprocessor named UniRISC which is designed by CCU SoC Center, and take three applications to examine the power. After the Post-Layout experiment, the processor with PBM system can save 20.1~30.2% power consumption.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131662797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746044
Chi-Chun Huang, Shou-Fu Yen, Chua-Chin Wang
A Li-ion battery charging design for wireless medical implants is presented. Not only the power density is limited in the medical implants, but also the inherent lack of efficiency in a wireless powered system restricts the stability of power supply for medical implants. Therefore, a simple and power saving circuit is proposed to charge the Li-ion battery with 0.1 C. In order to resist the ripple of the voltage supplied of the carrier wave from the inducing coil, a special bias circuit to generate a bias voltage which varies with supply voltage has been designed. Moreover, the proposed design with a protection circuit can limit over-charge voltage of the Li-ion battery to prevent any damage.
{"title":"A Li-ion battery charging design for biomedical implants","authors":"Chi-Chun Huang, Shou-Fu Yen, Chua-Chin Wang","doi":"10.1109/APCCAS.2008.4746044","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746044","url":null,"abstract":"A Li-ion battery charging design for wireless medical implants is presented. Not only the power density is limited in the medical implants, but also the inherent lack of efficiency in a wireless powered system restricts the stability of power supply for medical implants. Therefore, a simple and power saving circuit is proposed to charge the Li-ion battery with 0.1 C. In order to resist the ripple of the voltage supplied of the carrier wave from the inducing coil, a special bias circuit to generate a bias voltage which varies with supply voltage has been designed. Moreover, the proposed design with a protection circuit can limit over-charge voltage of the Li-ion battery to prevent any damage.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115335669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746149
Yiqing Zhou, T. Ng
This paper investigates the power allocation in orthogonal frequency and code division multiplexing (OFCDM) systems with multiple input multiple output (MIMO) multiplexing (MIMO-OFCDM). Since time-multiplexed pilot channels are employed for channel estimation, the total transmission power should be properly assigned to the pilot and data channels to achieve the best performance. By minimizing the mean square error (MSE) during signal detection, a closed form expression is derived for the optimal power ratio between the pilot and data channels. It is shown that the optimal power ratio is mainly decided by the number of transmit antennas and the number of pilot and data symbols in a packet, while it is not sensitive to other system parameters like signal-to-noise ratio (SNR) and the frequency domain spreading factor. Simulations demonstrate the accuracy of the derived optimal power ratio.
{"title":"Optimal power allocation for channel estimation in MIMO-OFCDM systems","authors":"Yiqing Zhou, T. Ng","doi":"10.1109/APCCAS.2008.4746149","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746149","url":null,"abstract":"This paper investigates the power allocation in orthogonal frequency and code division multiplexing (OFCDM) systems with multiple input multiple output (MIMO) multiplexing (MIMO-OFCDM). Since time-multiplexed pilot channels are employed for channel estimation, the total transmission power should be properly assigned to the pilot and data channels to achieve the best performance. By minimizing the mean square error (MSE) during signal detection, a closed form expression is derived for the optimal power ratio between the pilot and data channels. It is shown that the optimal power ratio is mainly decided by the number of transmit antennas and the number of pilot and data symbols in a packet, while it is not sensitive to other system parameters like signal-to-noise ratio (SNR) and the frequency domain spreading factor. Simulations demonstrate the accuracy of the derived optimal power ratio.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124421958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746388
Yiqing Huang, Qin Liu, T. Ikenaga
In H.264/AVC standard, the improvement of motion estimation (ME) part helps to enhance the performance greatly. However, the ME part, especially the integer motion estimation (IME) occupies computation complexity dramatically, which leads to complexity in hardware implementation. Many works have been done to achieve efficient IME engine and propagate partial SAD (PPSAD) architecture is the most efficient one in data path and hardware cost. Based on PPSAD structure, this paper proposes a compressor tree based compact PE array architecture. The 4-2 and 3-2 compressor trees are used to build up this compact structure. The proposed structure is embedded into PPSAD architecture and synthesized under different frequency points. With TSMC 0.18 mum 1P8M technology, the proposed architecture can achieve 10%-13% hardware cost reduction for a single 4times4 PE array compared with most recent work. About 10.7 k, 13.2 k and 6.5 k gates hardware cost can be saved compared with previous PPSAD structures.
{"title":"Compressor tree based processing element optimization in propagate partial SAD architecture","authors":"Yiqing Huang, Qin Liu, T. Ikenaga","doi":"10.1109/APCCAS.2008.4746388","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746388","url":null,"abstract":"In H.264/AVC standard, the improvement of motion estimation (ME) part helps to enhance the performance greatly. However, the ME part, especially the integer motion estimation (IME) occupies computation complexity dramatically, which leads to complexity in hardware implementation. Many works have been done to achieve efficient IME engine and propagate partial SAD (PPSAD) architecture is the most efficient one in data path and hardware cost. Based on PPSAD structure, this paper proposes a compressor tree based compact PE array architecture. The 4-2 and 3-2 compressor trees are used to build up this compact structure. The proposed structure is embedded into PPSAD architecture and synthesized under different frequency points. With TSMC 0.18 mum 1P8M technology, the proposed architecture can achieve 10%-13% hardware cost reduction for a single 4times4 PE array compared with most recent work. About 10.7 k, 13.2 k and 6.5 k gates hardware cost can be saved compared with previous PPSAD structures.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114806128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746413
J. Jin, Huang Qi
High Tc superconducting (HTS) cables have developed for DC power transmission systems with the advantages of high transport current capability, no resistive loss and compact systems. Technical assessments of HTS DC electrical power transmission system behaviors have been carried out with the system models built, and analysis results are presented in this paper.
{"title":"HTS DC power transmission analysis","authors":"J. Jin, Huang Qi","doi":"10.1109/APCCAS.2008.4746413","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746413","url":null,"abstract":"High Tc superconducting (HTS) cables have developed for DC power transmission systems with the advantages of high transport current capability, no resistive loss and compact systems. Technical assessments of HTS DC electrical power transmission system behaviors have been carried out with the system models built, and analysis results are presented in this paper.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114873596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746092
S. Chan, Shaohua Zhao
This paper studies the transmit/receive beamformers design and resources allocation problem for downlink multiuser MIMO-OFDM systems. We propose an algorithm for jointly optimizing the transmit and receive beamformers and resources allocation to minimize the transmission power and at the same time satisfying userspsila quality of service (QoS) in terms of bit error rate (BER) and minimum data rate. In the proposed algorithm, userspsila transmit/receive beamformers are first designed to maximize the sum-rate of each tone. Based on this tone capacity information, an iterative algorithm is developed to allocate the tones to the users. After the tone allocation, the bit rate allocation of each user at the tones allocated is then determined to minimize the total transmission power under the constraint of minimum data rate. This last problem is formulated as a geometric programming (GP) problem. Compared to the traditional algorithms, the proposed approach can make efficient use of the spatial diversity and the frequency diversity of MIMO-OFDM systems, resulting in improved performance. Numerical examples are conducted to demonstrate the effectiveness of the proposed method.
{"title":"Transmit/Receive beamformer design and resource allocation in multiuser MIMO-OFDM systems","authors":"S. Chan, Shaohua Zhao","doi":"10.1109/APCCAS.2008.4746092","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746092","url":null,"abstract":"This paper studies the transmit/receive beamformers design and resources allocation problem for downlink multiuser MIMO-OFDM systems. We propose an algorithm for jointly optimizing the transmit and receive beamformers and resources allocation to minimize the transmission power and at the same time satisfying userspsila quality of service (QoS) in terms of bit error rate (BER) and minimum data rate. In the proposed algorithm, userspsila transmit/receive beamformers are first designed to maximize the sum-rate of each tone. Based on this tone capacity information, an iterative algorithm is developed to allocate the tones to the users. After the tone allocation, the bit rate allocation of each user at the tones allocated is then determined to minimize the total transmission power under the constraint of minimum data rate. This last problem is formulated as a geometric programming (GP) problem. Compared to the traditional algorithms, the proposed approach can make efficient use of the spatial diversity and the frequency diversity of MIMO-OFDM systems, resulting in improved performance. Numerical examples are conducted to demonstrate the effectiveness of the proposed method.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117247177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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