Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746335
Jinbo Xu, Y. Dou, Jie Zhou
We propose an efficient multi-access memory architecture for image applications with multiple interested regions. Conflict-free parallel access of randomly aligned rectangular blocks of data in the interested regions is achieved. Only interested regions in the image are transmitted from main memory to a secondary multi-module memory structure proposed in our work, and overlapped data between different regions are reused without retransfer. The addressing of data is not based on traditional predetermined addressing function, but based on a proposed table structure which maps virtual addresses to physical addresses of secondary memory modules. Synthesis results of our design on FPGA indicate that transfer speedups from 5.5 up to 32.9 in our experiments are achieved when compared with the scheme that accesses main memory directly.
{"title":"Multi-access memory architecture for image applications with multiple interested regions","authors":"Jinbo Xu, Y. Dou, Jie Zhou","doi":"10.1109/APCCAS.2008.4746335","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746335","url":null,"abstract":"We propose an efficient multi-access memory architecture for image applications with multiple interested regions. Conflict-free parallel access of randomly aligned rectangular blocks of data in the interested regions is achieved. Only interested regions in the image are transmitted from main memory to a secondary multi-module memory structure proposed in our work, and overlapped data between different regions are reused without retransfer. The addressing of data is not based on traditional predetermined addressing function, but based on a proposed table structure which maps virtual addresses to physical addresses of secondary memory modules. Synthesis results of our design on FPGA indicate that transfer speedups from 5.5 up to 32.9 in our experiments are achieved when compared with the scheme that accesses main memory directly.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129171072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746225
Silin Liu, Yin Shi
In this paper, a charge-pump based phase-locked loop (CPLL) that can achieve fast locking and tiny deviation is proposed and analyzed. A lock-aid circuit is added to achieve fast locking of the CPLL. Besides, a novel differential charge pump which has good current matching characteristics and a PFD with delay cell has been used in this PLL. The proposed PLL circuit is designed based on the 0.35 um 2P4M CMOS process with 3.3 V/5 V supply voltage. HSPICE simulation shows that the lock time of the proposed CPLL can be reduced by over 72% in comparison to the conventional PLL and its charge pump sink and source current mismatch is only 0.008%.
本文提出并分析了一种基于电荷泵的锁相环(CPLL)，该锁相环可以实现快速锁相和微小的误差。通过加锁辅助电路实现CPLL的快速锁定。此外，该锁相环还采用了具有良好电流匹配特性的差分电荷泵和带延迟单元的PFD。本文设计的锁相环电路基于0.35 um 2P4M CMOS工艺，电源电压为3.3 V/5 V。HSPICE仿真结果表明，该CPLL锁相时间比传统锁相环缩短72%以上，电荷泵吸源电流失配率仅为0.008%。
{"title":"Fast locking and high accurate current matching phase-locked loop","authors":"Silin Liu, Yin Shi","doi":"10.1109/APCCAS.2008.4746225","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746225","url":null,"abstract":"In this paper, a charge-pump based phase-locked loop (CPLL) that can achieve fast locking and tiny deviation is proposed and analyzed. A lock-aid circuit is added to achieve fast locking of the CPLL. Besides, a novel differential charge pump which has good current matching characteristics and a PFD with delay cell has been used in this PLL. The proposed PLL circuit is designed based on the 0.35 um 2P4M CMOS process with 3.3 V/5 V supply voltage. HSPICE simulation shows that the lock time of the proposed CPLL can be reduced by over 72% in comparison to the conventional PLL and its charge pump sink and source current mismatch is only 0.008%.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130584819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746047
R. Weng, C.L. Yen, Chun-Yu Liu
A low voltage wide dynamic range CMOS active pixel sensor (APS) using 0.18 mum standard CMOS process is presented. The dynamic range of the proposed APS is 42 dB and it is twelve times more than a conventional CMOS APS architecture. The power consumption of the APS is 86 nW at 1 V supply. The fill factor is about 40% with 11 mum times 11 mum pixel size.
{"title":"A 1V CMOS active pixel sensor with enhanced dynamic range","authors":"R. Weng, C.L. Yen, Chun-Yu Liu","doi":"10.1109/APCCAS.2008.4746047","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746047","url":null,"abstract":"A low voltage wide dynamic range CMOS active pixel sensor (APS) using 0.18 mum standard CMOS process is presented. The dynamic range of the proposed APS is 42 dB and it is twelve times more than a conventional CMOS APS architecture. The power consumption of the APS is 86 nW at 1 V supply. The fill factor is about 40% with 11 mum times 11 mum pixel size.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123378261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746078
Yidie Ye, Chen Chen, Jin Jin, Lenian He
This paper introduces a method of realizing a monolithic battery management chip for a lithium ion battery pack of multi-cell in series. High precision subtractor amplifiers were employed to extract the voltage information of each battery. With the utilization of the subtractor amplifiers, the whole system was allowed to be implemented in a normal, nonexpensive standard CMOS process with 5 V supply voltage, instead of a costly high-voltage process. A testing chip was implemented by using CSMCpsilas 0.5 mum 5 V N-well CMOS process. The chip was designed for double-cell battery pack and compatible with single-cell application. The testing results showed this chip functioned well in both applications of double-cell and single-cell, and revealed that the present design method would be suitable for the multi-cell battery packs.
介绍了一种多芯串联锂离子电池组单片电池管理芯片的实现方法。采用高精度减法放大器提取每个电池的电压信息。随着减法放大器的使用，整个系统可以在一个正常的、不昂贵的标准CMOS工艺中实现，电源电压为5 V，而不是昂贵的高压工艺。采用CSMCpsilas 0.5 μ m 5 V n阱工艺制作了测试芯片。该芯片专为双芯电池组设计，兼容单芯应用。测试结果表明，该芯片在双电池和单电池的应用中都具有良好的性能，并表明该设计方法适用于多电池包。
{"title":"Li-ion battery management chip for multi-cell battery pack","authors":"Yidie Ye, Chen Chen, Jin Jin, Lenian He","doi":"10.1109/APCCAS.2008.4746078","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746078","url":null,"abstract":"This paper introduces a method of realizing a monolithic battery management chip for a lithium ion battery pack of multi-cell in series. High precision subtractor amplifiers were employed to extract the voltage information of each battery. With the utilization of the subtractor amplifiers, the whole system was allowed to be implemented in a normal, nonexpensive standard CMOS process with 5 V supply voltage, instead of a costly high-voltage process. A testing chip was implemented by using CSMCpsilas 0.5 mum 5 V N-well CMOS process. The chip was designed for double-cell battery pack and compatible with single-cell application. The testing results showed this chip functioned well in both applications of double-cell and single-cell, and revealed that the present design method would be suitable for the multi-cell battery packs.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114082260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4745983
Hsiu-Chun Lai, Zhi-Ming Lin
A fully integrated dual-band LNA that can cover 2-11 GHz and 3.1-10.6 GHz for WiMAX and UWB receiver is proposed based on a current-reused technique with a simple high-pass input matching network and a resonator. Simulated results show that the proposed LNA has 11.5 to 12.2 dB power gain and 2.47 to 3.97 dB noise figure (NF), while consuming only 7.52 mW dc power with 1 V supply voltage.
{"title":"A 1V low noise amplifier for WiMAX / UWB applications","authors":"Hsiu-Chun Lai, Zhi-Ming Lin","doi":"10.1109/APCCAS.2008.4745983","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4745983","url":null,"abstract":"A fully integrated dual-band LNA that can cover 2-11 GHz and 3.1-10.6 GHz for WiMAX and UWB receiver is proposed based on a current-reused technique with a simple high-pass input matching network and a resonator. Simulated results show that the proposed LNA has 11.5 to 12.2 dB power gain and 2.47 to 3.97 dB noise figure (NF), while consuming only 7.52 mW dc power with 1 V supply voltage.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"90 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116302608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746406
Santhos A. Wibowo, Zhang Ting, M. Kono, Tetsuya Taura, Y. Kobori, Haruo Kobayashi
This paper presents an analysis of characteristics of multiphase buck converters with coupled inductors. We derive equivalent inductances that provide both low per-phase steady-state ripple current and fast transient response. The characteristics of coupled-inductor circuits - low per-phase ripple current and fast response - were examined and verified by circuit simulation and experiments.
{"title":"Analysis of coupled inductors for low-ripple fast-response buck converter","authors":"Santhos A. Wibowo, Zhang Ting, M. Kono, Tetsuya Taura, Y. Kobori, Haruo Kobayashi","doi":"10.1109/APCCAS.2008.4746406","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746406","url":null,"abstract":"This paper presents an analysis of characteristics of multiphase buck converters with coupled inductors. We derive equivalent inductances that provide both low per-phase steady-state ripple current and fast transient response. The characteristics of coupled-inductor circuits - low per-phase ripple current and fast response - were examined and verified by circuit simulation and experiments.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121462981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746407
Yang Lu, S. Suresh, D. Czarkowski
A 100 MHz DC-DC switching converter with one-cycle control is proposed for radio frequency power amplifier. All blocks of one-cycle controller are built up on AMI 0.5 mum technology. The power supply has a tracking bandwidth of 5 MHz and an estimated efficiency of 80%. The converter performance is verified by means of simulations.
{"title":"Integrated controller for a 100 MHz DC-DC switching converter","authors":"Yang Lu, S. Suresh, D. Czarkowski","doi":"10.1109/APCCAS.2008.4746407","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746407","url":null,"abstract":"A 100 MHz DC-DC switching converter with one-cycle control is proposed for radio frequency power amplifier. All blocks of one-cycle controller are built up on AMI 0.5 mum technology. The power supply has a tracking bandwidth of 5 MHz and an estimated efficiency of 80%. The converter performance is verified by means of simulations.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121467995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746202
Dongsheng Yuan, Xingcheng Liu, Xiaoyu Zhang, Haengrae Cho
Routing protocol is a key technical issue in wireless sensor networks (WSN), and the appropriate routing scheme can make the energy-constraint sensor node consume as less energy as possible to prolong the network lifetime. The suitable sensor circuits and systems are beneficial to nodes energy savings. In this paper, we propose a protocol called CEERP (Cost-based Energy-Efficient Routing Protocol). Each node finds the appropriate transmission path through calculating and comparing the values of the related cost-functions. Experimental results show that the proposed CEERP outperforms existing methods to maximize network lifetime with less latency.
{"title":"CEERP: Cost-based Energy-Efficient Routing Protocol in wireless sensor networks","authors":"Dongsheng Yuan, Xingcheng Liu, Xiaoyu Zhang, Haengrae Cho","doi":"10.1109/APCCAS.2008.4746202","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746202","url":null,"abstract":"Routing protocol is a key technical issue in wireless sensor networks (WSN), and the appropriate routing scheme can make the energy-constraint sensor node consume as less energy as possible to prolong the network lifetime. The suitable sensor circuits and systems are beneficial to nodes energy savings. In this paper, we propose a protocol called CEERP (Cost-based Energy-Efficient Routing Protocol). Each node finds the appropriate transmission path through calculating and comparing the values of the related cost-functions. Experimental results show that the proposed CEERP outperforms existing methods to maximize network lifetime with less latency.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124503793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4745992
Yi Zhou, S. Chan, K. Ho
The sequential-LMS (S-LMS) family of algorithms are designed for partial update adaptive filtering. Like the LMS algorithm, their performance will be severely degraded by impulsive noises. In this paper, we derive the nonlinear least mean M-estimate (LMM) versions of the S-LMS family from robust M-estimation. The resultant algorithms, named the S-LMM family, have the improved performance in impulsive noise environment. Using the Pricepsilas theorem and its extension, the mean and mean square convergence behaviors of the S-LMS and S-LMM families of algorithms are derived both for Gaussian and contaminated Gaussian (CG) additive noises.
{"title":"A new family of robust sequential partial update least mean M-estimate adaptive filtering algorithms","authors":"Yi Zhou, S. Chan, K. Ho","doi":"10.1109/APCCAS.2008.4745992","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4745992","url":null,"abstract":"The sequential-LMS (S-LMS) family of algorithms are designed for partial update adaptive filtering. Like the LMS algorithm, their performance will be severely degraded by impulsive noises. In this paper, we derive the nonlinear least mean M-estimate (LMM) versions of the S-LMS family from robust M-estimation. The resultant algorithms, named the S-LMM family, have the improved performance in impulsive noise environment. Using the Pricepsilas theorem and its extension, the mean and mean square convergence behaviors of the S-LMS and S-LMM families of algorithms are derived both for Gaussian and contaminated Gaussian (CG) additive noises.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126301937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746201
Haipeng Zhang, Lingling Sun, Lifei Jiang, Lijian Ma, Mi Lin
In this paper process simulation of a novel structural Silicon On Insulator (SOI) LIGBT cell with Trench Gate and Field Plate and Trench Drain (TGFPTD) was done in a sequence of advanced SOI CMOS processes with Silvaco TCAD. The simulated results indicate that the proposed TGFPTD SOI LIGBT cell is feasible to be fabricated in advanced SOI CMOS technologies and the vertical channel length of the vertical gate nMOSFET could be reduced to about 170 nm.
本文采用先进的SOI CMOS工艺，利用Silvaco TCAD对具有沟槽栅极和场板沟槽漏的新型结构SOI (Silicon On Insulator) light电池(TGFPTD)进行了工艺模拟。仿真结果表明，采用先进的SOI CMOS技术制备TGFPTD SOI light电池是可行的，垂直栅极nMOSFET的垂直沟道长度可缩短至约170 nm。
{"title":"Process simulation of Trench Gate and Plate and Trench Drain SOI NLIGBT with TCAD tools","authors":"Haipeng Zhang, Lingling Sun, Lifei Jiang, Lijian Ma, Mi Lin","doi":"10.1109/APCCAS.2008.4746201","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746201","url":null,"abstract":"In this paper process simulation of a novel structural Silicon On Insulator (SOI) LIGBT cell with Trench Gate and Field Plate and Trench Drain (TGFPTD) was done in a sequence of advanced SOI CMOS processes with Silvaco TCAD. The simulated results indicate that the proposed TGFPTD SOI LIGBT cell is feasible to be fabricated in advanced SOI CMOS technologies and the vertical channel length of the vertical gate nMOSFET could be reduced to about 170 nm.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126367539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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