Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746154
L. Loy, Weija Zhang, Z. Kong, W. Goh, K. Yeo
In this paper, we present a new CMOS circuit design for increasing the threshold voltages (VT) of MOSFETS to reduce power consumption. Using a single voltage source VDD, the proposed circuit generates both the high positive and negative voltages, which are connected to the body nodes of MOSFETs to increase the reverse-bias voltage between the source and body in order to raise VT. Consequentially, static power consumption is reduced. The circuit is integrated into a 256-bit Ripple Carry Adder and a 32-bit Braun multiplier. Simulation results based on Chartered Semiconductor Manufacturing Private Limitedpsilas (CHRT) 0.25-mum, 0.18-mum and Berkeley Predictive Technology Modelpsilas (BPTM) 90-nm processes showed good trade-offs between power savings and delay.
{"title":"Body-bootstrapped-buffer circuit for CMOS static power reduction","authors":"L. Loy, Weija Zhang, Z. Kong, W. Goh, K. Yeo","doi":"10.1109/APCCAS.2008.4746154","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746154","url":null,"abstract":"In this paper, we present a new CMOS circuit design for increasing the threshold voltages (VT) of MOSFETS to reduce power consumption. Using a single voltage source VDD, the proposed circuit generates both the high positive and negative voltages, which are connected to the body nodes of MOSFETs to increase the reverse-bias voltage between the source and body in order to raise VT. Consequentially, static power consumption is reduced. The circuit is integrated into a 256-bit Ripple Carry Adder and a 32-bit Braun multiplier. Simulation results based on Chartered Semiconductor Manufacturing Private Limitedpsilas (CHRT) 0.25-mum, 0.18-mum and Berkeley Predictive Technology Modelpsilas (BPTM) 90-nm processes showed good trade-offs between power savings and delay.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132191143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746239
Hegong Wei, U. Chio, Yan Zhu, Sai-Weng Sin, S. U, R. P. Martins
This paper proposes a process- and temperature-insensitive current-controlled delay generator which can be widely used in sampled-data systems. The delay generator provides a large tunable range by adjusting the control current and load capacitance. Full transistor-level simulations, including process corner and Monte-Carlo analysis, are presented. The delay generator is designed in 90 nm CMOS technology and consumes 330 muW power from a 1.2 V power supply, at a typical case of using 10 muA control current and 30 fF load capacitance. The process corner simulation results exhibit a typical delay of 2.09 ns with a corner variation of -7.1% / +7.6%. The 500-times process Monte-Carlo simulation obtains a mean of 2.09 ps with a standard-deviation (sigma) of 28.9 ps (1.38%).
{"title":"A process- and temperature- insensitive current-controlled delay generator for sampled-data systems","authors":"Hegong Wei, U. Chio, Yan Zhu, Sai-Weng Sin, S. U, R. P. Martins","doi":"10.1109/APCCAS.2008.4746239","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746239","url":null,"abstract":"This paper proposes a process- and temperature-insensitive current-controlled delay generator which can be widely used in sampled-data systems. The delay generator provides a large tunable range by adjusting the control current and load capacitance. Full transistor-level simulations, including process corner and Monte-Carlo analysis, are presented. The delay generator is designed in 90 nm CMOS technology and consumes 330 muW power from a 1.2 V power supply, at a typical case of using 10 muA control current and 30 fF load capacitance. The process corner simulation results exhibit a typical delay of 2.09 ns with a corner variation of -7.1% / +7.6%. The 500-times process Monte-Carlo simulation obtains a mean of 2.09 ps with a standard-deviation (sigma) of 28.9 ps (1.38%).","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115562605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746185
José C. García, J. Montiel-Nelson, S. Nooshabadi
This paper presents the design of a low energy CMOS adiabatic inverter (Ib-driver). The proposed Ib-driver structure uses complementary input, output and a dual-rail structure. When implemented on a 0.13 mum CMOS 1.2 V technology, under the large capacitive loading condition, Ib-driver performs better than the reference adiabatic circuit (sk-driver) in terms of the energy-delay product (21%), with active area which is (34%) lower. Proposed inverter has a full swing for high capacitive loads (20 pF).
本文介绍了一种低能CMOS绝热逆变器(Ib-driver)的设计。所提出的ib驱动器结构采用互补的输入、输出和双轨结构。当在0.13 μ m CMOS 1.2 V技术上实现时，在大容性负载条件下，ib -驱动器在能量延迟积(21%)方面优于参考绝热电路(sk-驱动器)，有源面积(34%)低。所提出的逆变器具有高容性负载(20pf)的全摆幅。
{"title":"A CMOS adiabatic inverter operating with a single clock power supply to reduce non-adiabatic loss","authors":"José C. García, J. Montiel-Nelson, S. Nooshabadi","doi":"10.1109/APCCAS.2008.4746185","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746185","url":null,"abstract":"This paper presents the design of a low energy CMOS adiabatic inverter (Ib-driver). The proposed Ib-driver structure uses complementary input, output and a dual-rail structure. When implemented on a 0.13 mum CMOS 1.2 V technology, under the large capacitive loading condition, Ib-driver performs better than the reference adiabatic circuit (sk-driver) in terms of the energy-delay product (21%), with active area which is (34%) lower. Proposed inverter has a full swing for high capacitive loads (20 pF).","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114361895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746284
Yang Hong, C. Chan, Jianping Guo, Y. Ng, Weiwei Shi, L. Leung, K. Leung, O. Choy, K. Pun
This paper presents a low-power, passive, UHF RFID tag design compatible with EPCTM C1G2 protocol. In order to reduce its cost, diode-connected NMOS in a standard CMOS technology is used instead of Schottky diodes. With the help of low-threshold-voltage, triple-well NMOS, a minimum input power of -7.6 dBm is achieved. A sub-1 V, low temperature-coefficient voltage reference using self-biased mutual compensation is proposed without large resistors to save the chip area. In addition, an energy-aware irregular clock structure, together with clock gating, achieves low power consumption in the baseband processor. The whole tag is implemented in a 130 nm CMOS technology and the total chip area is 1200 mum times 1220 mum.
{"title":"Design of passive UHF RFID tag in 130nm CMOS technology","authors":"Yang Hong, C. Chan, Jianping Guo, Y. Ng, Weiwei Shi, L. Leung, K. Leung, O. Choy, K. Pun","doi":"10.1109/APCCAS.2008.4746284","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746284","url":null,"abstract":"This paper presents a low-power, passive, UHF RFID tag design compatible with EPCTM C1G2 protocol. In order to reduce its cost, diode-connected NMOS in a standard CMOS technology is used instead of Schottky diodes. With the help of low-threshold-voltage, triple-well NMOS, a minimum input power of -7.6 dBm is achieved. A sub-1 V, low temperature-coefficient voltage reference using self-biased mutual compensation is proposed without large resistors to save the chip area. In addition, an energy-aware irregular clock structure, together with clock gating, achieves low power consumption in the baseband processor. The whole tag is implemented in a 130 nm CMOS technology and the total chip area is 1200 mum times 1220 mum.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114380038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746002
Gan-gui Yan, Gui-qiang Jiang, Mu Gang, Jun-hui Li, Tao Chen, Ya-feng Huang, Jian Wang
A dynamic model of back-to-back voltage source converter under synchronous rotating d-q coordinate system is developed. The system is transformed to a new equivalent nonlinear system which consists of a linear decoupled subsystem and a nonlinear subsystem characterizing the dynamics of the dc-link voltage in terms of the state variables in the linear subsystem via the feedback linearization technique. Then a decoupled controller which consists of an outer loop for determination of d- and q-axis components of reference currents and an inner loop for tracking the reference currents is designed for active and reactive power exchange control between the VSC and the two ac systems. The validity of the proposed controller is demonstrated by the simulation results under electromagnetic software PSCAD/EMTDC and experimental results on a 30 kVA/380 V prototype system, respectively.
{"title":"Nonlinear decoupled control of back-to-back voltage source converter","authors":"Gan-gui Yan, Gui-qiang Jiang, Mu Gang, Jun-hui Li, Tao Chen, Ya-feng Huang, Jian Wang","doi":"10.1109/APCCAS.2008.4746002","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746002","url":null,"abstract":"A dynamic model of back-to-back voltage source converter under synchronous rotating d-q coordinate system is developed. The system is transformed to a new equivalent nonlinear system which consists of a linear decoupled subsystem and a nonlinear subsystem characterizing the dynamics of the dc-link voltage in terms of the state variables in the linear subsystem via the feedback linearization technique. Then a decoupled controller which consists of an outer loop for determination of d- and q-axis components of reference currents and an inner loop for tracking the reference currents is designed for active and reactive power exchange control between the VSC and the two ac systems. The validity of the proposed controller is demonstrated by the simulation results under electromagnetic software PSCAD/EMTDC and experimental results on a 30 kVA/380 V prototype system, respectively.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114492762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746326
Y. En, Yujuan He, Hongwei Luo, Q. Shi, X. Kuang, Zhijian Pan
The irradiation response of DC-DC power converter is studied using X-ray source. During the test, DC-DC power converter is unsteady and the characteristic parameter such as input current and output voltage was strong influenced by the total-irradiation-dose. It is indicated that optical coupler in DC-DC power converter is tremendous affected by irradiation, but the ultimate failure of DC-DC converter is due to the VDMOSFET broken out.
{"title":"The irradiation effect of DC-DC power converter under X-ray","authors":"Y. En, Yujuan He, Hongwei Luo, Q. Shi, X. Kuang, Zhijian Pan","doi":"10.1109/APCCAS.2008.4746326","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746326","url":null,"abstract":"The irradiation response of DC-DC power converter is studied using X-ray source. During the test, DC-DC power converter is unsteady and the characteristic parameter such as input current and output voltage was strong influenced by the total-irradiation-dose. It is indicated that optical coupler in DC-DC power converter is tremendous affected by irradiation, but the ultimate failure of DC-DC converter is due to the VDMOSFET broken out.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114721007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4745967
Chon Chio Leong, S. Ting, K. Tam
A novel triple U-shaped defected ground structure (DGS) unit is proposed. In contrasts to the conventional single bandgap DGS, the proposed DGS unit provides three controllable bandgaps at different frequencies but still retaining the size as compact as that of the single-bandgap DGS. Cascading this new DGS element to the conventional dual-mode bandpass filter, multi-spurious suppression of the dual-mode filter can be achieved. An example square-loop dual-mode bandpass filter centered at 2.04 GHz and 4.4% fractional bandwidth with the proposed DGS element embedded to the input and output feedlines, obtains better than 30-dB suppression on its second, third and fourth harmonics, resulting in a wide stopband upto 9 GHz.
{"title":"Multi-spurious suppression for microstrip dual-mode bandpass filter using triple U-shaped defected ground structure","authors":"Chon Chio Leong, S. Ting, K. Tam","doi":"10.1109/APCCAS.2008.4745967","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4745967","url":null,"abstract":"A novel triple U-shaped defected ground structure (DGS) unit is proposed. In contrasts to the conventional single bandgap DGS, the proposed DGS unit provides three controllable bandgaps at different frequencies but still retaining the size as compact as that of the single-bandgap DGS. Cascading this new DGS element to the conventional dual-mode bandpass filter, multi-spurious suppression of the dual-mode filter can be achieved. An example square-loop dual-mode bandpass filter centered at 2.04 GHz and 4.4% fractional bandwidth with the proposed DGS element embedded to the input and output feedlines, obtains better than 30-dB suppression on its second, third and fourth harmonics, resulting in a wide stopband upto 9 GHz.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116718181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746221
W. M. Tam, F. Lau, C. Tse
In the traditional study of mobile cellular systems, all users are assumed to have the same behavior. They have the same probability of making/receiving a call and they will move around the network with identical mobility. In a practical environment, each user has a different list of acquaintances including relatives, friends and colleagues, with whom the user will make contact. Also, the size of the list varies with individual users. In addition, depending on various factors such as job nature, different users will acquire different levels of mobility. To evaluate the performance of a mobile cellular system more realistically in this paper, we use the power-law-distributed mobility model under an assumption of a scale-free user network.
{"title":"Traffic analysis of a mobile cellular system based on a scale-free user network and a power-law-distributed mobility model","authors":"W. M. Tam, F. Lau, C. Tse","doi":"10.1109/APCCAS.2008.4746221","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746221","url":null,"abstract":"In the traditional study of mobile cellular systems, all users are assumed to have the same behavior. They have the same probability of making/receiving a call and they will move around the network with identical mobility. In a practical environment, each user has a different list of acquaintances including relatives, friends and colleagues, with whom the user will make contact. Also, the size of the list varies with individual users. In addition, depending on various factors such as job nature, different users will acquire different levels of mobility. To evaluate the performance of a mobile cellular system more realistically in this paper, we use the power-law-distributed mobility model under an assumption of a scale-free user network.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116731975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746131
Xinhua Zhao, Bin Li
This paper presents the inverse dynamics analysis of 3-RRRT parallel manipulator with three translational degrees of freedom. Firstly, kinematic analysis of 3-RRRT parallel manipulator is completed using screw theory. Second, the generalized forces of moving platform and all links are expressed in screw formation. Based on these work, the inverse dynamic formula of the manipulator is gotten by the combination of screw theory and the principle of virtual work, Finally, numerical examples are reported.
{"title":"Inverse dynamics of 3-RRRT parallel manipulator","authors":"Xinhua Zhao, Bin Li","doi":"10.1109/APCCAS.2008.4746131","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746131","url":null,"abstract":"This paper presents the inverse dynamics analysis of 3-RRRT parallel manipulator with three translational degrees of freedom. Firstly, kinematic analysis of 3-RRRT parallel manipulator is completed using screw theory. Second, the generalized forces of moving platform and all links are expressed in screw formation. Based on these work, the inverse dynamic formula of the manipulator is gotten by the combination of screw theory and the principle of virtual work, Finally, numerical examples are reported.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"17 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115498681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746210
D. Prasertsom, W. Tangsrirat, W. Surakampontorn
A low-voltage digitally controlled current differencing buffered amplifier (DC-CDBA) is proposed. The realization scheme is through the cascade connection of a current differencing circuit, a current division network (CDN) and a buffered voltage amplifier. To achieve the digital control of the current gain of the circuit, a novel CDN is also proposed. The proposed DC-CDBA can operate with the low supply voltage of plusmn1.25 V. PSPICE simulations using standard 0.5-mum CMOS process parameters are in agreement with the theory.
提出了一种低压数字控制差分缓冲放大器(DC-CDBA)。其实现方案是将差流电路、分流网络(CDN)和缓冲电压放大器级联起来。为了实现电路电流增益的数字控制，还提出了一种新的CDN。所提出的dc - cba可以在+ 1.25 V的低电源电压下工作。采用标准0.5 μ m CMOS工艺参数的PSPICE仿真与理论一致。
{"title":"Low-voltage digitally controlled current differencing buffered amplifier","authors":"D. Prasertsom, W. Tangsrirat, W. Surakampontorn","doi":"10.1109/APCCAS.2008.4746210","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746210","url":null,"abstract":"A low-voltage digitally controlled current differencing buffered amplifier (DC-CDBA) is proposed. The realization scheme is through the cascade connection of a current differencing circuit, a current division network (CDN) and a buffered voltage amplifier. To achieve the digital control of the current gain of the circuit, a novel CDN is also proposed. The proposed DC-CDBA can operate with the low supply voltage of plusmn1.25 V. PSPICE simulations using standard 0.5-mum CMOS process parameters are in agreement with the theory.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124850998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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