Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746154
L. Loy, Weija Zhang, Z. Kong, W. Goh, K. Yeo
In this paper, we present a new CMOS circuit design for increasing the threshold voltages (VT) of MOSFETS to reduce power consumption. Using a single voltage source VDD, the proposed circuit generates both the high positive and negative voltages, which are connected to the body nodes of MOSFETs to increase the reverse-bias voltage between the source and body in order to raise VT. Consequentially, static power consumption is reduced. The circuit is integrated into a 256-bit Ripple Carry Adder and a 32-bit Braun multiplier. Simulation results based on Chartered Semiconductor Manufacturing Private Limitedpsilas (CHRT) 0.25-mum, 0.18-mum and Berkeley Predictive Technology Modelpsilas (BPTM) 90-nm processes showed good trade-offs between power savings and delay.
{"title":"Body-bootstrapped-buffer circuit for CMOS static power reduction","authors":"L. Loy, Weija Zhang, Z. Kong, W. Goh, K. Yeo","doi":"10.1109/APCCAS.2008.4746154","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746154","url":null,"abstract":"In this paper, we present a new CMOS circuit design for increasing the threshold voltages (VT) of MOSFETS to reduce power consumption. Using a single voltage source VDD, the proposed circuit generates both the high positive and negative voltages, which are connected to the body nodes of MOSFETs to increase the reverse-bias voltage between the source and body in order to raise VT. Consequentially, static power consumption is reduced. The circuit is integrated into a 256-bit Ripple Carry Adder and a 32-bit Braun multiplier. Simulation results based on Chartered Semiconductor Manufacturing Private Limitedpsilas (CHRT) 0.25-mum, 0.18-mum and Berkeley Predictive Technology Modelpsilas (BPTM) 90-nm processes showed good trade-offs between power savings and delay.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132191143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746185
José C. García, J. Montiel-Nelson, S. Nooshabadi
This paper presents the design of a low energy CMOS adiabatic inverter (Ib-driver). The proposed Ib-driver structure uses complementary input, output and a dual-rail structure. When implemented on a 0.13 mum CMOS 1.2 V technology, under the large capacitive loading condition, Ib-driver performs better than the reference adiabatic circuit (sk-driver) in terms of the energy-delay product (21%), with active area which is (34%) lower. Proposed inverter has a full swing for high capacitive loads (20 pF).
本文介绍了一种低能CMOS绝热逆变器(Ib-driver)的设计。所提出的ib驱动器结构采用互补的输入、输出和双轨结构。当在0.13 μ m CMOS 1.2 V技术上实现时，在大容性负载条件下，ib -驱动器在能量延迟积(21%)方面优于参考绝热电路(sk-驱动器)，有源面积(34%)低。所提出的逆变器具有高容性负载(20pf)的全摆幅。
{"title":"A CMOS adiabatic inverter operating with a single clock power supply to reduce non-adiabatic loss","authors":"José C. García, J. Montiel-Nelson, S. Nooshabadi","doi":"10.1109/APCCAS.2008.4746185","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746185","url":null,"abstract":"This paper presents the design of a low energy CMOS adiabatic inverter (Ib-driver). The proposed Ib-driver structure uses complementary input, output and a dual-rail structure. When implemented on a 0.13 mum CMOS 1.2 V technology, under the large capacitive loading condition, Ib-driver performs better than the reference adiabatic circuit (sk-driver) in terms of the energy-delay product (21%), with active area which is (34%) lower. Proposed inverter has a full swing for high capacitive loads (20 pF).","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114361895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746284
Yang Hong, C. Chan, Jianping Guo, Y. Ng, Weiwei Shi, L. Leung, K. Leung, O. Choy, K. Pun
This paper presents a low-power, passive, UHF RFID tag design compatible with EPCTM C1G2 protocol. In order to reduce its cost, diode-connected NMOS in a standard CMOS technology is used instead of Schottky diodes. With the help of low-threshold-voltage, triple-well NMOS, a minimum input power of -7.6 dBm is achieved. A sub-1 V, low temperature-coefficient voltage reference using self-biased mutual compensation is proposed without large resistors to save the chip area. In addition, an energy-aware irregular clock structure, together with clock gating, achieves low power consumption in the baseband processor. The whole tag is implemented in a 130 nm CMOS technology and the total chip area is 1200 mum times 1220 mum.
{"title":"Design of passive UHF RFID tag in 130nm CMOS technology","authors":"Yang Hong, C. Chan, Jianping Guo, Y. Ng, Weiwei Shi, L. Leung, K. Leung, O. Choy, K. Pun","doi":"10.1109/APCCAS.2008.4746284","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746284","url":null,"abstract":"This paper presents a low-power, passive, UHF RFID tag design compatible with EPCTM C1G2 protocol. In order to reduce its cost, diode-connected NMOS in a standard CMOS technology is used instead of Schottky diodes. With the help of low-threshold-voltage, triple-well NMOS, a minimum input power of -7.6 dBm is achieved. A sub-1 V, low temperature-coefficient voltage reference using self-biased mutual compensation is proposed without large resistors to save the chip area. In addition, an energy-aware irregular clock structure, together with clock gating, achieves low power consumption in the baseband processor. The whole tag is implemented in a 130 nm CMOS technology and the total chip area is 1200 mum times 1220 mum.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114380038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4745963
Changming Ma, Xingjun Wu, Chun Zhang, Zhihua Wang
This paper presents in details the architecture and most of RF front-end building blocks of a fully integrated passive radio frequency identification (RFID) transponder operating at UHF 902 MHz to 928 MHz. A novel architecture for the transponder IC and a new low power on-off keying (OOK) demodulator are proposed in this paper. For realizing the system, a low power CMOS full-wave rectifier achieving a power conversion efficiency of 31.9% has been integrated in this transponder. Simulation results show that the global input power of front-end circuits is only about 21 muw in order to drive a load of 1.8 muA at the rectifier output and the power consumption of the proposed demodulator is less than 0.4 muw. The transponder is fabricated in a 0.18 mum mixed-mode CMOS technology and has the area of 0.70 mm2.
{"title":"A low-power RF front-end of passive UHF RFID transponders","authors":"Changming Ma, Xingjun Wu, Chun Zhang, Zhihua Wang","doi":"10.1109/APCCAS.2008.4745963","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4745963","url":null,"abstract":"This paper presents in details the architecture and most of RF front-end building blocks of a fully integrated passive radio frequency identification (RFID) transponder operating at UHF 902 MHz to 928 MHz. A novel architecture for the transponder IC and a new low power on-off keying (OOK) demodulator are proposed in this paper. For realizing the system, a low power CMOS full-wave rectifier achieving a power conversion efficiency of 31.9% has been integrated in this transponder. Simulation results show that the global input power of front-end circuits is only about 21 muw in order to drive a load of 1.8 muA at the rectifier output and the power consumption of the proposed demodulator is less than 0.4 muw. The transponder is fabricated in a 0.18 mum mixed-mode CMOS technology and has the area of 0.70 mm2.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124536549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4745987
Su-Hon Lin, M. Sheu, Chao-Hsiang Wang, Yuan-Ching Kuo
The moduli set M1=(2n,2n+1-1,2n-1) which is free of 2a+1 modulus is profitable to construct a high-speed residue number system (RNS). In this paper, we derive a reduced-complexity residue-to-binary conversion algorithm for M1 by using new Chinese remainder theorem (CRT). The resulting converter architecture mainly consists of carry-save adders (CSAs), modular adders and multiplexer (MUX) which is suitable for an efficient VLSI implementation. Under the same dynamic range (DR) requirement, the proposed converter design is significantly more efficient than the latest design for M1 with respect to area-time (AT), time-power (TP) and area-time-power (ATP) products. Based on UMC 0.18 um CMOS cell-based technology, the chip area for 16-bit residue-to-binary converter is only 931times931um2 and the working frequency is 135 MHz.
模集M1=(2n,2n+1-1,2n-1)不存在2a+1模，可用于构造高速剩数系统。本文利用新中国剩余定理，导出了一种简化的M1残数到二进制的转换算法。所得到的转换器架构主要由免进位加法器(csa)、模块化加法器和多路复用器(MUX)组成，适用于高效的VLSI实现。在相同的动态范围(DR)要求下，所提出的转换器设计在面积-时间(AT)、时间-功率(TP)和面积-时间-功率(ATP)产品方面明显优于M1的最新设计。基于UMC 0.18 um CMOS单元技术的16位残二进制转换器的芯片面积仅为931倍931um2，工作频率为135 MHz。
{"title":"Area-time-power efficient VLSI design for residue-to-binary converter based on moduli set (2n,2n+1−1,2n−1)","authors":"Su-Hon Lin, M. Sheu, Chao-Hsiang Wang, Yuan-Ching Kuo","doi":"10.1109/APCCAS.2008.4745987","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4745987","url":null,"abstract":"The moduli set M1=(2n,2n+1-1,2n-1) which is free of 2a+1 modulus is profitable to construct a high-speed residue number system (RNS). In this paper, we derive a reduced-complexity residue-to-binary conversion algorithm for M1 by using new Chinese remainder theorem (CRT). The resulting converter architecture mainly consists of carry-save adders (CSAs), modular adders and multiplexer (MUX) which is suitable for an efficient VLSI implementation. Under the same dynamic range (DR) requirement, the proposed converter design is significantly more efficient than the latest design for M1 with respect to area-time (AT), time-power (TP) and area-time-power (ATP) products. Based on UMC 0.18 um CMOS cell-based technology, the chip area for 16-bit residue-to-binary converter is only 931times931um2 and the working frequency is 135 MHz.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124563120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4745993
R. Punchalard, J. Koseeyaporn, P. Wardkein
Mean square error (MSE) analysis of adaptive IIR notch filter with constrained poles and zeros using the power spectral density (PSD) method is proposed in this paper. The lower bound of the MSE is derived in closed form. The proposed method is very simple as compared with the compared analysis method. Moreover, the simulated results are conducted to confirm the theoretical analysis. It is found that the proposed analysis provides more accurate results than the compared analysis method, especially when the signal frequency is in neighborhood of 0.5pi.
{"title":"Mean square error analysis of the PG algorithm for adaptive IIR notch filter with constrained poles and zeros using power spectral density method","authors":"R. Punchalard, J. Koseeyaporn, P. Wardkein","doi":"10.1109/APCCAS.2008.4745993","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4745993","url":null,"abstract":"Mean square error (MSE) analysis of adaptive IIR notch filter with constrained poles and zeros using the power spectral density (PSD) method is proposed in this paper. The lower bound of the MSE is derived in closed form. The proposed method is very simple as compared with the compared analysis method. Moreover, the simulated results are conducted to confirm the theoretical analysis. It is found that the proposed analysis provides more accurate results than the compared analysis method, especially when the signal frequency is in neighborhood of 0.5pi.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125366941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746017
Z. Su, Zhi-Ming Lin
This paper presents a high conversion gain folded mixer for a 2~11 GHz WiMAX system with 20 MHz IF output signal. The simulated conversion gain is ranged from 18.9 to 21.5 dB for the full bandwidth. The simulated NF is 13.5 to 17.6 dB with 0.2 to 4.4 dBm IIP3. The folded mixer is designed and fabricated in TSMC 0.18 mum RF CMOS technology with 1.8 V VDD and 1.5 V VRF supply voltage. The DC power consumption of the folded mixer core is 11.8 mW.
{"title":"A 18.9dB conversion gain folded mixer for WiMAX system","authors":"Z. Su, Zhi-Ming Lin","doi":"10.1109/APCCAS.2008.4746017","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746017","url":null,"abstract":"This paper presents a high conversion gain folded mixer for a 2~11 GHz WiMAX system with 20 MHz IF output signal. The simulated conversion gain is ranged from 18.9 to 21.5 dB for the full bandwidth. The simulated NF is 13.5 to 17.6 dB with 0.2 to 4.4 dBm IIP3. The folded mixer is designed and fabricated in TSMC 0.18 mum RF CMOS technology with 1.8 V VDD and 1.5 V VRF supply voltage. The DC power consumption of the folded mixer core is 11.8 mW.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134421335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746115
Chi-Shuang Oulee, Rong-Jyi Yang
This paper describes a 1.25-Gb/s all-digital clock and data recovery (ADCDR) circuit with binary frequency acquisition which is never achieved in reference-less ADCDR systems. The proposed configuration of digital loop filter without any adder can minimize to loop latency and the recovered clock jitter. The proposed ADCDR circuit occupies a chip area of 0.9times0.7 mm2 and consumes 80 mW from a single 1.8-V power supply. Simulation results show the binary frequency acquisition time is less than 500 ns and the total lock time is less than 800 ns while receiving a 1.25 Gb/s NRZ data. The recovered eye diagram exhibits 45 ps peak-peak jitter.
{"title":"A 1.25Gbps all-digital clock and data recovery circuit with binary frequency acquisition","authors":"Chi-Shuang Oulee, Rong-Jyi Yang","doi":"10.1109/APCCAS.2008.4746115","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746115","url":null,"abstract":"This paper describes a 1.25-Gb/s all-digital clock and data recovery (ADCDR) circuit with binary frequency acquisition which is never achieved in reference-less ADCDR systems. The proposed configuration of digital loop filter without any adder can minimize to loop latency and the recovered clock jitter. The proposed ADCDR circuit occupies a chip area of 0.9times0.7 mm2 and consumes 80 mW from a single 1.8-V power supply. Simulation results show the binary frequency acquisition time is less than 500 ns and the total lock time is less than 800 ns while receiving a 1.25 Gb/s NRZ data. The recovered eye diagram exhibits 45 ps peak-peak jitter.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134407439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746218
J. Semião, J. Varela, J. Freijedo, J. Rodríguez-Andina, C. Leong, João Paulo Teixeira, I. Teixeira
The purpose of this paper is to present a new robust methodology for synchronous communications in a BUS, connecting multi-clock domains. Traditionally, when robust solutions are needed, an asynchronous communication is used. However, the low transfer rates associated with asynchronous solutions make them inadequate for high performance digital systems. On the other hand, synchronous communications do not guarantee dependability for all data, especially when different clock domains are interconnected. In this paper we propose to take advantage of these approaches, by combining, the robustness of asynchronous communication and the speed and simplicity of synchronous communications. A structure has been developed to implement the proposed communication approach. A test chip has been designed to implement that structure and prove the concept. The usefulness of the methodology is demonstrated in a complex FPGA data acquisition system. Simulation results are presented.
{"title":"Robust solution for synchronous communication among multi clock domains","authors":"J. Semião, J. Varela, J. Freijedo, J. Rodríguez-Andina, C. Leong, João Paulo Teixeira, I. Teixeira","doi":"10.1109/APCCAS.2008.4746218","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746218","url":null,"abstract":"The purpose of this paper is to present a new robust methodology for synchronous communications in a BUS, connecting multi-clock domains. Traditionally, when robust solutions are needed, an asynchronous communication is used. However, the low transfer rates associated with asynchronous solutions make them inadequate for high performance digital systems. On the other hand, synchronous communications do not guarantee dependability for all data, especially when different clock domains are interconnected. In this paper we propose to take advantage of these approaches, by combining, the robustness of asynchronous communication and the speed and simplicity of synchronous communications. A structure has been developed to implement the proposed communication approach. A test chip has been designed to implement that structure and prove the concept. The usefulness of the methodology is demonstrated in a complex FPGA data acquisition system. Simulation results are presented.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132354737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746175
N. Chang, Y. Tseng, Tian-Sheuan Chang
The impact of color space and similarity measure on complexity, speed, and performance of stereo matching is especially important to applications adopting stereo vision. This work analyzed the complexity of several most commonly considered color space and similarity measure. In addition, the execution speed and performance of color space and similarity measure combination are also compared on the same basis. The comparison result suggests that the Y-only rank provides the best combination under speed and performance trade-off.
{"title":"Analysis of color space and similarity measure impact on stereo block matching","authors":"N. Chang, Y. Tseng, Tian-Sheuan Chang","doi":"10.1109/APCCAS.2008.4746175","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746175","url":null,"abstract":"The impact of color space and similarity measure on complexity, speed, and performance of stereo matching is especially important to applications adopting stereo vision. This work analyzed the complexity of several most commonly considered color space and similarity measure. In addition, the execution speed and performance of color space and similarity measure combination are also compared on the same basis. The comparison result suggests that the Y-only rank provides the best combination under speed and performance trade-off.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134006218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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