Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173319
W. Liu, Y. K. Lim, F. Zhang, W.Y. Zhang, C.Q. Chen, B.C. Zhang, J.B. Tan, D. Sohn, L. Hsia
The correlation of time-dependent dielectric breakdown (TDDB) reliability failure with scratches generated from chemical mechanical polishing (CMP) in 45nm backend-ofline (BEOL) process is investigated and established. The wafer map of early TDDB failure samples matches well with the defect wafer map from bright field scans. Electrical fault isolation using thermally induced voltage alteration (TIVA) analysis is employed to locate the hot spot where TDDB leakage occurs. Polish scratchinduced metal damage at the hot spot is further analyzed by topdown scanning electron microscopy (SEM) after de-processing. Also, the depth of the polish scratch is confirmed by using transmission electron microscopy (TEM) analysis. It clearly shows that the embedded particle on copper (Cu) surface and the liner damage resulted from polish scratch severely affect the TDDB reliability. In-situ CMP platen3 (P3) pad chemical preclean is found to reduce the polish scratch density effectively and significantly improve the V-ramp/TDDB reliability performance. However, inappropriate usage of chemical pre-clean would cause Cu corrosion and lead to EM degradation. Hence, a balance between polish scratch reduction and Cu corrosion associated with P3 pad pre-clean needs to be achieved.
{"title":"Effect of chemical mechanical polishing scratch on TDDB reliability and its reduction in 45nm BEOL process","authors":"W. Liu, Y. K. Lim, F. Zhang, W.Y. Zhang, C.Q. Chen, B.C. Zhang, J.B. Tan, D. Sohn, L. Hsia","doi":"10.1109/IRPS.2009.5173319","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173319","url":null,"abstract":"The correlation of time-dependent dielectric breakdown (TDDB) reliability failure with scratches generated from chemical mechanical polishing (CMP) in 45nm backend-ofline (BEOL) process is investigated and established. The wafer map of early TDDB failure samples matches well with the defect wafer map from bright field scans. Electrical fault isolation using thermally induced voltage alteration (TIVA) analysis is employed to locate the hot spot where TDDB leakage occurs. Polish scratchinduced metal damage at the hot spot is further analyzed by topdown scanning electron microscopy (SEM) after de-processing. Also, the depth of the polish scratch is confirmed by using transmission electron microscopy (TEM) analysis. It clearly shows that the embedded particle on copper (Cu) surface and the liner damage resulted from polish scratch severely affect the TDDB reliability. In-situ CMP platen3 (P3) pad chemical preclean is found to reduce the polish scratch density effectively and significantly improve the V-ramp/TDDB reliability performance. However, inappropriate usage of chemical pre-clean would cause Cu corrosion and lead to EM degradation. Hence, a balance between polish scratch reduction and Cu corrosion associated with P3 pad pre-clean needs to be achieved.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130322714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173348
J. Tseng, J. Hwu
The interface trap's characteristics in silicon dioxide induced by electrostatic discharge current impulse were studied using the transmission line pulsing technique and charge pumping method. It was observed that the electrostatic discharge stress induces far less amount of interface traps prior to breakdown and the interface traps distribution along the channel direction is more non-uniform and localized than dc stress. The possible mechanisms for interface trap generation and formation are suggested.
{"title":"Characterization of the electrostatic discharge induced interface traps in metal-oxide-semiconductor field-effect transistors","authors":"J. Tseng, J. Hwu","doi":"10.1109/IRPS.2009.5173348","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173348","url":null,"abstract":"The interface trap's characteristics in silicon dioxide induced by electrostatic discharge current impulse were studied using the transmission line pulsing technique and charge pumping method. It was observed that the electrostatic discharge stress induces far less amount of interface traps prior to breakdown and the interface traps distribution along the channel direction is more non-uniform and localized than dc stress. The possible mechanisms for interface trap generation and formation are suggested.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129214529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173270
S. Kudo, Y. Hirose, T. Futase, Y. Ogawa, T. Yamaguchi, K. Kihara, K. Kashihara, N. Murata, T. Katayama, K. Asayama, E. Murakami
We performed detailed analysis of Ni silicide discontinuities induced by agglomeration that causes the increasing electric resistance in high-performance CMOS devices by using advanced physical analysis techniques. We confirmed that the agglomeration of the Ni silicide is related to elongated-triangular- shaped-splits — which we call delta-shaped-splits — which cause discontinuities that occur at small-angle grain boundaries pinned by boron clusters even with small stress. We successfully determined the formation mechanism of the Ni silicide discontinuities in detail. It is essential to develop a highly reliable Ni salicide process, especially for 45 nm node high performance devices and beyond.
{"title":"Study of formation mechanism of nickel silicide discontinuities in high performance CMOS devices","authors":"S. Kudo, Y. Hirose, T. Futase, Y. Ogawa, T. Yamaguchi, K. Kihara, K. Kashihara, N. Murata, T. Katayama, K. Asayama, E. Murakami","doi":"10.1109/IRPS.2009.5173270","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173270","url":null,"abstract":"We performed detailed analysis of Ni silicide discontinuities induced by agglomeration that causes the increasing electric resistance in high-performance CMOS devices by using advanced physical analysis techniques. We confirmed that the agglomeration of the Ni silicide is related to elongated-triangular- shaped-splits — which we call delta-shaped-splits — which cause discontinuities that occur at small-angle grain boundaries pinned by boron clusters even with small stress. We successfully determined the formation mechanism of the Ni silicide discontinuities in detail. It is essential to develop a highly reliable Ni salicide process, especially for 45 nm node high performance devices and beyond.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123369630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173353
H. Lin, M. Wu, Tsui-hua Huang
A beam bounce technique in a conductive atomic force microscope (C-AFM) system is usually used to enable the probe head to measure extremely small movements of the cantilever as it is moved across the surface of the sample. However, the laser beam used for the beam bounce also gives rise to the photoelectric effect while we are measuring electrical characteristics of a device. The photoelectric effect occurring in NMOSFETs caused by a laser beam used in the C-AFM system has been reported [1]. In this study, the photoelectric effect occurring in PMOSFETs will be discussed. An example that an invisible implant defect in a PMOSFET was successfully identified using the C-AFM based on the measured electrical characteristics and the bipolar phototransistor action models will also be introduced.
{"title":"A study bipolar phototransistor action existing in CMOS process triggered by a laser beam used in a C-AFM system","authors":"H. Lin, M. Wu, Tsui-hua Huang","doi":"10.1109/IRPS.2009.5173353","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173353","url":null,"abstract":"A beam bounce technique in a conductive atomic force microscope (C-AFM) system is usually used to enable the probe head to measure extremely small movements of the cantilever as it is moved across the surface of the sample. However, the laser beam used for the beam bounce also gives rise to the photoelectric effect while we are measuring electrical characteristics of a device. The photoelectric effect occurring in NMOSFETs caused by a laser beam used in the C-AFM system has been reported [1]. In this study, the photoelectric effect occurring in PMOSFETs will be discussed. An example that an invisible implant defect in a PMOSFET was successfully identified using the C-AFM based on the measured electrical characteristics and the bipolar phototransistor action models will also be introduced.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114224930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173379
W. Kanert, R. Pufall
Chip-package interaction is a major concern for product reliability. Temperature cycling is a commonly used stress test to address this issue. The paper shows that temperature shock can substitute temperature cycling for certain failure mechanisms, thereby reducing stress times by a factor of 28 or even more.
{"title":"Investigation of chip-package interaction-looking for more acceleration in product qualification tests","authors":"W. Kanert, R. Pufall","doi":"10.1109/IRPS.2009.5173379","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173379","url":null,"abstract":"Chip-package interaction is a major concern for product reliability. Temperature cycling is a commonly used stress test to address this issue. The paper shows that temperature shock can substitute temperature cycling for certain failure mechanisms, thereby reducing stress times by a factor of 28 or even more.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114236190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173351
G. Torrens, B. Alorda, S. Bota, J. Segura
We analyze two complementary radiation-hardening techniques for 6T SRAM memories compatible with structured layouts. One approach relies on the individual selection of the threshold voltage of each of the four transistors forming the cross-coupled inverters of the SRAM cell. The other one is based on the modification of the widths of all pmos or all nmos transistors of the cell. The first technique does not affect the cell layout. The second one increases the minimum width of all pmos by a factor cp and the minimum width of all nmos by a factor cn. This prevents the formation of diffusion bends, allowing structured layouts. Both techniques provide an improvement in SEU robustness.
{"title":"Analysis of radiation-hardening techniques for 6T SRAMs with structured layouts","authors":"G. Torrens, B. Alorda, S. Bota, J. Segura","doi":"10.1109/IRPS.2009.5173351","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173351","url":null,"abstract":"We analyze two complementary radiation-hardening techniques for 6T SRAM memories compatible with structured layouts. One approach relies on the individual selection of the threshold voltage of each of the four transistors forming the cross-coupled inverters of the SRAM cell. The other one is based on the modification of the widths of all pmos or all nmos transistors of the cell. The first technique does not affect the cell layout. The second one increases the minimum width of all pmos by a factor cp and the minimum width of all nmos by a factor cn. This prevents the formation of diffusion bends, allowing structured layouts. Both techniques provide an improvement in SEU robustness.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114340572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173283
J.P. Campbell, J. Qin, K. Cheung, L.C. Yu, J. Suehle, A. Oates, K. Sheng
Recently, 1/f and random telegraph noise (RTN) studies have been used to infer information about bulk dielectric defects' spatial and energetic distributions. These analyses rely on a noise framework which involves charge exchange between the inversion layer and the bulk dielectric defects via elastic tunneling. In this study, we extracted the characteristic capture and emission time constants from RTN in highly scaled nMOSFETs and showed that they are inconsistent with the elastic tunneling picture dictated by the physical thickness of the gate dielectric (1.4 nm). Consequently, our results suggest that an alternative model is required and that a large body of the recent RTN and 1/ƒ noise defect profiling literature very likely needs to be re-interpreted.
{"title":"Random telegraph noise in highly scaled nMOSFETs","authors":"J.P. Campbell, J. Qin, K. Cheung, L.C. Yu, J. Suehle, A. Oates, K. Sheng","doi":"10.1109/IRPS.2009.5173283","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173283","url":null,"abstract":"Recently, 1/f and random telegraph noise (RTN) studies have been used to infer information about bulk dielectric defects' spatial and energetic distributions. These analyses rely on a noise framework which involves charge exchange between the inversion layer and the bulk dielectric defects via elastic tunneling. In this study, we extracted the characteristic capture and emission time constants from RTN in highly scaled nMOSFETs and showed that they are inconsistent with the elastic tunneling picture dictated by the physical thickness of the gate dielectric (1.4 nm). Consequently, our results suggest that an alternative model is required and that a large body of the recent RTN and 1/ƒ noise defect profiling literature very likely needs to be re-interpreted.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121460213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173259
C. Salling, Kevin Yang, Rajesh Gupta, D. Hayes, Janice Tamayo, V. Gopalakrishnan, S. Robins
This is the first published study of the reliability of Thyristor-based high-speed memories. The T-RAM (Thyristor-based Random Access Memory) was characterized using test structures and multi-megabit product die fabricated in a 130nm SOI logic technology. The reliability lifetime of a nominal bit was investigated by subjecting TCCT devices (Thin Capacitively Coupled Thyristor) to a DC current stress. The resulting acceleration model yields a lifetime of 1.0E+40 yrs for the Data-1 state and 1.0E+5 yrs for the Data-0 state. These long lifetimes are consistent with the 26 FIT long-term failure rate found for 9 Mb arrays, from dynamic lifetest on 9Mb & 18Mb T-RAM product die having full SRAM functionality. The susceptibility of T-RAM arrays to soft errors was assessed by accelerated neutron testing, and accelerated alpha testing, of 9Mb T-RAM product die as well as 9Mb SRAM product die from three suppliers. n-SER for the T-RAM is 610 FIT/Mb, better than the average of 700 FIT/Mb for 6T SRAM technology. Exposure of the T-RAM product die to X-rays showed that they tolerate doses of 450 rad or more (3–4x the dose for X-ray inspections) without degradation of nominal TCCT retention times, and without functional failure of memory cells. Taken together, the results of this study shows that T-RAM is a reliable memory technology.
{"title":"Reliability of thyristor-based memory cells","authors":"C. Salling, Kevin Yang, Rajesh Gupta, D. Hayes, Janice Tamayo, V. Gopalakrishnan, S. Robins","doi":"10.1109/IRPS.2009.5173259","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173259","url":null,"abstract":"This is the first published study of the reliability of Thyristor-based high-speed memories. The T-RAM (Thyristor-based Random Access Memory) was characterized using test structures and multi-megabit product die fabricated in a 130nm SOI logic technology. The reliability lifetime of a nominal bit was investigated by subjecting TCCT devices (Thin Capacitively Coupled Thyristor) to a DC current stress. The resulting acceleration model yields a lifetime of 1.0E+40 yrs for the Data-1 state and 1.0E+5 yrs for the Data-0 state. These long lifetimes are consistent with the 26 FIT long-term failure rate found for 9 Mb arrays, from dynamic lifetest on 9Mb & 18Mb T-RAM product die having full SRAM functionality. The susceptibility of T-RAM arrays to soft errors was assessed by accelerated neutron testing, and accelerated alpha testing, of 9Mb T-RAM product die as well as 9Mb SRAM product die from three suppliers. n-SER for the T-RAM is 610 FIT/Mb, better than the average of 700 FIT/Mb for 6T SRAM technology. Exposure of the T-RAM product die to X-rays showed that they tolerate doses of 450 rad or more (3–4x the dose for X-ray inspections) without degradation of nominal TCCT retention times, and without functional failure of memory cells. Taken together, the results of this study shows that T-RAM is a reliable memory technology.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124306920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173310
P. van der Wel, O. Wunnicke, F. de Bruijn, R. Strijbos
In this paper, the reliability requirements, thermal behaviour and failure mechanisms of solidly mounted Bulk Acoustic Wave (BAW) filters are studied. High power RF stress measurements are presented where the evolution of the surface damage of the BAW filters as a function of stress time is analysed by optical height profiling. Two different metal stacks were used. The main failure mechanism for BAW filters during high RF power stress is proposed to be acoustomigration. By comparing the stress measurements to the requirements, excellent reliability of NXP's BAW duplexers is proven.
{"title":"Thermal behaviour and reliability of solidly mounted Bulk Acoustic Wave Duplexers under high power RF loads","authors":"P. van der Wel, O. Wunnicke, F. de Bruijn, R. Strijbos","doi":"10.1109/IRPS.2009.5173310","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173310","url":null,"abstract":"In this paper, the reliability requirements, thermal behaviour and failure mechanisms of solidly mounted Bulk Acoustic Wave (BAW) filters are studied. High power RF stress measurements are presented where the evolution of the surface damage of the BAW filters as a function of stress time is analysed by optical height profiling. Two different metal stacks were used. The main failure mechanism for BAW filters during high RF power stress is proposed to be acoustomigration. By comparing the stress measurements to the requirements, excellent reliability of NXP's BAW duplexers is proven.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124341243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173263
C. M. Compagnoni, L. Chiavarone, M. Calabrese, R. Gusmeroli, M. Ghidotti, A. Lacaita, A. Spinelli, A. Visconti
This work investigates for the first time chargegranularity effects during channel hot-electron programming of NOR Flash memories, comparing the granular electron injection and the random telegraph noise limitations to the accuracy of the programming algorithm. The spread of the threshold voltage shift that is determined by the electron injection statistics is studied as a function of the channel hot-electron programming conditions, explaining the results by an analytical model accounting for the sub-poissonian nature of the electron transfer to the floating gate. The scaling trend of the injection statistical spread is then investigated on NOR technologies ranging from 180 to 45 nm and its contribution to the width of the threshold voltage distribution in presence of a program verify level is separated from that given by random telegraph noise.
{"title":"Granular electron injection and random telegraph noise impact on the programming accuracy of NOR Flash memories","authors":"C. M. Compagnoni, L. Chiavarone, M. Calabrese, R. Gusmeroli, M. Ghidotti, A. Lacaita, A. Spinelli, A. Visconti","doi":"10.1109/IRPS.2009.5173263","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173263","url":null,"abstract":"This work investigates for the first time chargegranularity effects during channel hot-electron programming of NOR Flash memories, comparing the granular electron injection and the random telegraph noise limitations to the accuracy of the programming algorithm. The spread of the threshold voltage shift that is determined by the electron injection statistics is studied as a function of the channel hot-electron programming conditions, explaining the results by an analytical model accounting for the sub-poissonian nature of the electron transfer to the floating gate. The scaling trend of the injection statistical spread is then investigated on NOR technologies ranging from 180 to 45 nm and its contribution to the width of the threshold voltage distribution in presence of a program verify level is separated from that given by random telegraph noise.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126534717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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