Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173265
Bio Kim, Seungjae Baik, Sunjung Kim, Joon-Gon Lee, B. Koo, Siyoung Choi, J. Moon
We investigated threshold voltage shifts after program pulse in charge trap flash memory by measuring drain current changes. We have found threshold voltage shifts can be characterized as a function of not only the materials of tunnel oxide, trap layer, blocking layer, but also physical parameters like device size and electrical measurement environment such as program voltage target and gate bias voltage. This approach can identify the root cause of initial threshold voltage shifts in charge trap flash memory devices.
{"title":"Characterization of threshold voltage instability after program in charge trap flash memory","authors":"Bio Kim, Seungjae Baik, Sunjung Kim, Joon-Gon Lee, B. Koo, Siyoung Choi, J. Moon","doi":"10.1109/IRPS.2009.5173265","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173265","url":null,"abstract":"We investigated threshold voltage shifts after program pulse in charge trap flash memory by measuring drain current changes. We have found threshold voltage shifts can be characterized as a function of not only the materials of tunnel oxide, trap layer, blocking layer, but also physical parameters like device size and electrical measurement environment such as program voltage target and gate bias voltage. This approach can identify the root cause of initial threshold voltage shifts in charge trap flash memory devices.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130062666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173219
M. Zahid, R. Degraeve, M. Cho, L. Pantisano, D. R. Aguado, J. van Houdt, G. Groeseneken, M. Jurczak
A Variable Tcharge-Tdischarge Amplitude Charge Pumping (VT2ACP) is used to profile defect in the SiO2 and Al2O3 separately in Flash Memory based devices. It is shown that by independently controlling the pulse low timing “discharging time” and high level timing “charging time”, the contribution of interface and bulk Al2O3 traps can be separated. By using the ellipsometry and the measured intersection time tcharge to trap in the high- k (∼60 μs), SiO2 thickness of 0.87 nm and scanning rate of 0.19nm/dec is found. Using a slanted wafer, the result shows that in the case of thin SiO2 (∼1nm) the trap density close to the substrate (short tcharge) is one order of magnitude higher compared to thick SiO2 (∼3nm). For tSiO2 = 1.7nm all traps are in the SiO2 or SiO2/Al2O3 transition layer. Only for the thickest SiO2 layers (2.7 and 3 nm) the trap density becomes low and constant. Additionally WKB-approximation is used to calculate the filling probability of the traps (fT), the modeled scanning rate nearly doubles to ∼0.29 nm/dec and 0.27 nm/dec for amorphous and crystalline, respectively. In summary, the method of trap energy/depth profiling by using VT2ACP allows scanning from ∼0.5nm up to 1.2nm in depth and 0.1 to 0.7eV in energy range above the EcSi band depending on sample used. The results show that there exist significant interaction between SiO2 and Al2O3 when processed with PDA 1000°C. For amorphous Al2O3 (PDA 700°C) the impact of the precursor is not reflected in the SiO2 trap density while for crystalline Al2O3 no increase in trap density at 0.3eV above the EcSi band is observed.
{"title":"Deffect profiling in the SiO2/ Al2O3 interface using Variable Tcharge-Tdischarge Amplitude Charge Pumping (VT2ACP)","authors":"M. Zahid, R. Degraeve, M. Cho, L. Pantisano, D. R. Aguado, J. van Houdt, G. Groeseneken, M. Jurczak","doi":"10.1109/IRPS.2009.5173219","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173219","url":null,"abstract":"A Variable T<inf>charge</inf>-T<inf>discharge</inf> Amplitude Charge Pumping (VT<sup>2</sup>ACP) is used to profile defect in the SiO<inf>2</inf> and Al<inf>2</inf>O<inf>3</inf> separately in Flash Memory based devices. It is shown that by independently controlling the pulse low timing “discharging time” and high level timing “charging time”, the contribution of interface and bulk Al<inf>2</inf>O<inf>3</inf> traps can be separated. By using the ellipsometry and the measured intersection time t<inf>charge</inf> to trap in the high- k (∼60 μs), SiO<inf>2</inf> thickness of 0.87 nm and scanning rate of 0.19nm/dec is found. Using a slanted wafer, the result shows that in the case of thin SiO<inf>2</inf> (∼1nm) the trap density close to the substrate (short t<inf>charge</inf>) is one order of magnitude higher compared to thick SiO<inf>2</inf> (∼3nm). For t<inf>SiO2</inf> = 1.7nm all traps are in the SiO<inf>2</inf> or SiO<inf>2</inf>/Al<inf>2</inf>O<inf>3</inf> transition layer. Only for the thickest SiO<inf>2</inf> layers (2.7 and 3 nm) the trap density becomes low and constant. Additionally WKB-approximation is used to calculate the filling probability of the traps (f<inf>T</inf>), the modeled scanning rate nearly doubles to ∼0.29 nm/dec and 0.27 nm/dec for amorphous and crystalline, respectively. In summary, the method of trap energy/depth profiling by using VT<sup>2</sup>ACP allows scanning from ∼0.5nm up to 1.2nm in depth and 0.1 to 0.7eV in energy range above the E<inf>c</inf><sup>Si</sup> band depending on sample used. The results show that there exist significant interaction between SiO<inf>2</inf> and Al<inf>2</inf>O<inf>3</inf> when processed with PDA 1000°C. For amorphous Al<inf>2</inf>O<inf>3</inf> (PDA 700°C) the impact of the precursor is not reflected in the SiO<inf>2</inf> trap density while for crystalline Al<inf>2</inf>O<inf>3</inf> no increase in trap density at 0.3eV above the E<inf>c</inf><sup>Si</sup> band is observed.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116026229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173244
S. Phillips, A. Sutton, A. Appaswamy, M. Bellini, J. Cressler, A. Grillo, G. Vizkelethy, P. Dodd, Mike McCurdy, R. Reed, P. Marshall
We investigate, for the first time, the impact of deep trench isolation on the total ionizing dose (TID) and single event upset (SEU) tolerance of advanced SiGe HBTs. We employ a combination of 63MeV protons, 10keV X-rays, and 36MeV oxygen ion microbeam irradiation and compare a 3rd generation, high-performance (HP), deep-trench isolated, SiGe BiCMOS platform with its cost-performance (CP) variant without deeptrenches. Although the CP SiGe HBTs are shown to be more susceptible to TID damage, the elevated damage is not attributed to variations in deep trench isolation (DTI), but to spacer oxide differences. CP SiGe HBTs are surprisingly found to offer a potential built-in self-mitigation mechanism for SEU, which is a direct result of the influence of the deep trench isolation on the charge collection dynamics associated with ion strikes. Calibrated, full 3D ion strike TCAD simulations are employed to explain the results, revealing substantial enhancement of radial charge diffusion for structures implemented with little to no deep trench. Mitigation of charge collection events are found to occur for emitter-center strikes for devices with limited/eliminated DTI with the caveat of larger collection for outside-DTI ion strikes.
{"title":"Impact of deep trench isolation on advanced SiGe HBT reliability in radiation environments","authors":"S. Phillips, A. Sutton, A. Appaswamy, M. Bellini, J. Cressler, A. Grillo, G. Vizkelethy, P. Dodd, Mike McCurdy, R. Reed, P. Marshall","doi":"10.1109/IRPS.2009.5173244","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173244","url":null,"abstract":"We investigate, for the first time, the impact of deep trench isolation on the total ionizing dose (TID) and single event upset (SEU) tolerance of advanced SiGe HBTs. We employ a combination of 63MeV protons, 10keV X-rays, and 36MeV oxygen ion microbeam irradiation and compare a 3rd generation, high-performance (HP), deep-trench isolated, SiGe BiCMOS platform with its cost-performance (CP) variant without deeptrenches. Although the CP SiGe HBTs are shown to be more susceptible to TID damage, the elevated damage is not attributed to variations in deep trench isolation (DTI), but to spacer oxide differences. CP SiGe HBTs are surprisingly found to offer a potential built-in self-mitigation mechanism for SEU, which is a direct result of the influence of the deep trench isolation on the charge collection dynamics associated with ion strikes. Calibrated, full 3D ion strike TCAD simulations are employed to explain the results, revealing substantial enhancement of radial charge diffusion for structures implemented with little to no deep trench. Mitigation of charge collection events are found to occur for emitter-center strikes for devices with limited/eliminated DTI with the caveat of larger collection for outside-DTI ion strikes.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127537519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173297
K. Croes, C. Wilson, M. Lofrano, Y. Travaly, D. de Roest, Z. Tokei, G. Beyer
The time and temperature dependence of Stress-Induced-Voiding below and in copper VIA's with a diameter of 80nm integrated in a k=2.5 material was studied. The focus was on the early phase of the voiding process. To accelerate the degradation, test structures with big metal plates below and/or above the VIA were used. We found two degradation mechanisms in which one dominated below and the other dominated above a certain temperature. The first mechanism has an activation energy of 0.9eV and is the result of interface-diffusion driven by a stress-gradient. This mechanism was more pronounced below the VIA, but was significant in the VIA as well. The second mechanism has an activation energy of 1.2eV, which is argued to be driven by grain boundary diffusion due to a vacancy gradient in and above the VIA. To explain both mechanisms, an addition to the traditional stress-creep model is proposed and fits our data well. Additionally, it is discussed that VIA's connected to the center of big metal plates above and below the VIA are less susceptible to SIV compared to VIA's connected to line ends either below or on top of the VIA. We support our argumentation and analytical modeling with Finite Element Modeling.
{"title":"Time and temperature dependence of early stage Stress-Induced-Voiding in Cu/low-k interconnects","authors":"K. Croes, C. Wilson, M. Lofrano, Y. Travaly, D. de Roest, Z. Tokei, G. Beyer","doi":"10.1109/IRPS.2009.5173297","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173297","url":null,"abstract":"The time and temperature dependence of Stress-Induced-Voiding below and in copper VIA's with a diameter of 80nm integrated in a k=2.5 material was studied. The focus was on the early phase of the voiding process. To accelerate the degradation, test structures with big metal plates below and/or above the VIA were used. We found two degradation mechanisms in which one dominated below and the other dominated above a certain temperature. The first mechanism has an activation energy of 0.9eV and is the result of interface-diffusion driven by a stress-gradient. This mechanism was more pronounced below the VIA, but was significant in the VIA as well. The second mechanism has an activation energy of 1.2eV, which is argued to be driven by grain boundary diffusion due to a vacancy gradient in and above the VIA. To explain both mechanisms, an addition to the traditional stress-creep model is proposed and fits our data well. Additionally, it is discussed that VIA's connected to the center of big metal plates above and below the VIA are less susceptible to SIV compared to VIA's connected to line ends either below or on top of the VIA. We support our argumentation and analytical modeling with Finite Element Modeling.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117193218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173304
A. Kerber, E. Cartier, B. Linder, S. Krishnan, T. Nigam
Extensive breakdown measurements with large statistic confirm that the TDDB failure distribution follows Poisson area scaling. However, towards larger areas and lower failure percentiles the distribution changes in ways similar to those reported for progressive breakdown in poly Si/SiON gate stacks. The change in failure distribution is found to be more pronounced for nFET than for pFET devices. In addition AC TDDB testing was explored, confirming the shape of the DC failure distributions but shows a significant reduction in TDDB lifetime for nFET devices.
{"title":"TDDB failure distribution of metal gate/high-k CMOS devices on SOI substrates","authors":"A. Kerber, E. Cartier, B. Linder, S. Krishnan, T. Nigam","doi":"10.1109/IRPS.2009.5173304","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173304","url":null,"abstract":"Extensive breakdown measurements with large statistic confirm that the TDDB failure distribution follows Poisson area scaling. However, towards larger areas and lower failure percentiles the distribution changes in ways similar to those reported for progressive breakdown in poly Si/SiON gate stacks. The change in failure distribution is found to be more pronounced for nFET than for pFET devices. In addition AC TDDB testing was explored, confirming the shape of the DC failure distributions but shows a significant reduction in TDDB lifetime for nFET devices.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132818751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173231
L. Trevisanello, F. de Zuani, M. Meneghini, N. Trivellin, E. Zanoni, G. Meneghesso
The results achieved in an accelerated life-time test on Phosphor-Converted Light Emitting Diodes (PC-LEDs) have been reported. Two different families of commercially available low-flux devices have been widely characterized and a comparative analysis on performances has been carried out. A wide set of devices has been submitted to a combined electrothermal accelerated stress under different aging conditions. The stress induced a luminous flux decay on LEDs from both series. In particular, the lumen decay was found to be thermally activated for one set of devices. The aged devices showed also a degradation of chromatic properties, in terms of a blue or yellow shift for the two different families. The failure modes found have been detected also in devices aged at constant temperature and no bias. The degradation mechanism responsible for lumen decay and chromatic shift was ascribed to the thermally activated package instabilities. A failure analysis has been carried out on failed devices, detecting different failure modes related to the package (chip detachment) and to the chip (generation of low impedance paths that shorted the junction).
{"title":"Thermally activated degradation and package instabilities of low flux LEDS","authors":"L. Trevisanello, F. de Zuani, M. Meneghini, N. Trivellin, E. Zanoni, G. Meneghesso","doi":"10.1109/IRPS.2009.5173231","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173231","url":null,"abstract":"The results achieved in an accelerated life-time test on Phosphor-Converted Light Emitting Diodes (PC-LEDs) have been reported. Two different families of commercially available low-flux devices have been widely characterized and a comparative analysis on performances has been carried out. A wide set of devices has been submitted to a combined electrothermal accelerated stress under different aging conditions. The stress induced a luminous flux decay on LEDs from both series. In particular, the lumen decay was found to be thermally activated for one set of devices. The aged devices showed also a degradation of chromatic properties, in terms of a blue or yellow shift for the two different families. The failure modes found have been detected also in devices aged at constant temperature and no bias. The degradation mechanism responsible for lumen decay and chromatic shift was ascribed to the thermally activated package instabilities. A failure analysis has been carried out on failed devices, detecting different failure modes related to the package (chip detachment) and to the chip (generation of low impedance paths that shorted the junction).","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"11 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133040828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173272
Magdalena Sienkiewcz, A. Firiti, O. Crépel, P. Perdu, K. Sanchez, D. Lewis
The soft defect localization on analog or mixed-mode ICs is becoming more and more challenging due to their increasing complexity and integration. New techniques based on dynamic laser stimulation are promising for analog and mixedmode ICs. Unfortunately, the considerable intrinsic sensitivity of this kind of devices under laser stimulation makes the defect localization results complex to analyze. As a matter of fact, the laser sensitivity mapping contains not only abnormal sensitive regions but also naturally sensitive ones. In order to overcome this issue by extracting the abnormal spots and therefore localize the defect, we propose in this paper a methodology that can improve the FA efficiency and accuracy. It consists on combining the mapping results with the electrical simulation of laser stimulation impact on the device. First, we will present the concept of the methodology. Then, we will show one case study on a mixed-mode IC illustrating the soft defect localization by using laser mapping technique & standard electrical simulations. Furthermore, we will argument the interest of a new methodology and we will show two simple examples from our experiments to validate it.
{"title":"Methodology to support laser-localized soft defects on analog and mixed-mode advanced ICs","authors":"Magdalena Sienkiewcz, A. Firiti, O. Crépel, P. Perdu, K. Sanchez, D. Lewis","doi":"10.1109/IRPS.2009.5173272","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173272","url":null,"abstract":"The soft defect localization on analog or mixed-mode ICs is becoming more and more challenging due to their increasing complexity and integration. New techniques based on dynamic laser stimulation are promising for analog and mixedmode ICs. Unfortunately, the considerable intrinsic sensitivity of this kind of devices under laser stimulation makes the defect localization results complex to analyze. As a matter of fact, the laser sensitivity mapping contains not only abnormal sensitive regions but also naturally sensitive ones. In order to overcome this issue by extracting the abnormal spots and therefore localize the defect, we propose in this paper a methodology that can improve the FA efficiency and accuracy. It consists on combining the mapping results with the electrical simulation of laser stimulation impact on the device. First, we will present the concept of the methodology. Then, we will show one case study on a mixed-mode IC illustrating the soft defect localization by using laser mapping technique & standard electrical simulations. Furthermore, we will argument the interest of a new methodology and we will show two simple examples from our experiments to validate it.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133259614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173255
S. Pai, J. Lee, K. Ng, R. Hsiao, K. Su, E.N. Chou
A collaborative framework is presented to address the reliability challenges faced in a fabless-foundry environment. Examples are given to show the effectiveness of this framework for both infant mortality and long-term reliability risk. Through design-for-reliability, optimum process standardization and selective customization, defect density reduction and electrical screening, reliability of the highest level has been achieved in FPGA devices suitable for enterprise, automotive and aerospace applications, all in a fabless-foundry environment.
{"title":"Reliability framework in a fabless-foundry environment","authors":"S. Pai, J. Lee, K. Ng, R. Hsiao, K. Su, E.N. Chou","doi":"10.1109/IRPS.2009.5173255","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173255","url":null,"abstract":"A collaborative framework is presented to address the reliability challenges faced in a fabless-foundry environment. Examples are given to show the effectiveness of this framework for both infant mortality and long-term reliability risk. Through design-for-reliability, optimum process standardization and selective customization, defect density reduction and electrical screening, reliability of the highest level has been achieved in FPGA devices suitable for enterprise, automotive and aerospace applications, all in a fabless-foundry environment.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133477326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173311
Stefan Hillebrecht, I. Polian, B. Becker, P. Ruther, S. Herwik, O. Paul
Integrated circuits are often subjected to mechanical stress resulting from external loads or intrinsic stress caused by the mismatch in thermal expansion coefficients of the applied materials. Interconnects and vias in these circuits are particularly jeopardized when applied in complementary metal-oxide semiconductor (CMOS)-based microelectromechanical systems (MEMS). In this paper, we characterize the reliability of interconnects using a heterogeneous CMOS/MEMS monitor chip manufactured using deep reactive ion etching. It comprises various daisy-chain structures with different combinations of interconnects integrated in a thin silicon membrane hinge subjected to tensile mechanical stress. The electro-mechanical testing is performed using a custom-made system that simultaneously applies mechanical stress and performs mechanical and electrical measurements. Experiments provide somewhat unexpected insight into patterns of failure of different types of interconnects.
{"title":"Reliability characterization of interconnects in CMOS integrated circuits under mechanical stress","authors":"Stefan Hillebrecht, I. Polian, B. Becker, P. Ruther, S. Herwik, O. Paul","doi":"10.1109/IRPS.2009.5173311","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173311","url":null,"abstract":"Integrated circuits are often subjected to mechanical stress resulting from external loads or intrinsic stress caused by the mismatch in thermal expansion coefficients of the applied materials. Interconnects and vias in these circuits are particularly jeopardized when applied in complementary metal-oxide semiconductor (CMOS)-based microelectromechanical systems (MEMS). In this paper, we characterize the reliability of interconnects using a heterogeneous CMOS/MEMS monitor chip manufactured using deep reactive ion etching. It comprises various daisy-chain structures with different combinations of interconnects integrated in a thin silicon membrane hinge subjected to tensile mechanical stress. The electro-mechanical testing is performed using a custom-made system that simultaneously applies mechanical stress and performs mechanical and electrical measurements. Experiments provide somewhat unexpected insight into patterns of failure of different types of interconnects.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129211576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173337
A. Nakajima, K. Itagaki, K. Horio
Two-dimensional transient analysis of field-plate AlGaN/GaN HEMTs and GaN MESFETs is performed, considering a deep donor and a deep acceptor in the semiinsulating GaN buffer layer. Quasi-pulsed I-V curves are derived from the transient characteristics. It is studied how the existence of a field plate affects buffer-related drain lag, gate lag and current collapse. It is shown that in both FETs, the drain lag is reduced by introducing a field plate, because electron injection into the buffer layer is weakened by it, and trapping effects are reduced. It is also shown that the buffer-related current collapse and gate lag are reduced in the field-plate structures. The dependence on SiN passivation layer thickness under the field plate is also studied, suggesting that there is an optimum thickness of the SiN layer to minimize buffer-related current collapse and drain lag in GaN HEMTs and MESFETs.
{"title":"Physical mechanism of buffer-related lag and current collapse in GaN-based FETs and their reduction by introducing a field plate","authors":"A. Nakajima, K. Itagaki, K. Horio","doi":"10.1109/IRPS.2009.5173337","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173337","url":null,"abstract":"Two-dimensional transient analysis of field-plate AlGaN/GaN HEMTs and GaN MESFETs is performed, considering a deep donor and a deep acceptor in the semiinsulating GaN buffer layer. Quasi-pulsed I-V curves are derived from the transient characteristics. It is studied how the existence of a field plate affects buffer-related drain lag, gate lag and current collapse. It is shown that in both FETs, the drain lag is reduced by introducing a field plate, because electron injection into the buffer layer is weakened by it, and trapping effects are reduced. It is also shown that the buffer-related current collapse and gate lag are reduced in the field-plate structures. The dependence on SiN passivation layer thickness under the field plate is also studied, suggesting that there is an optimum thickness of the SiN layer to minimize buffer-related current collapse and drain lag in GaN HEMTs and MESFETs.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116655826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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