Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173219
M. Zahid, R. Degraeve, M. Cho, L. Pantisano, D. R. Aguado, J. van Houdt, G. Groeseneken, M. Jurczak
A Variable Tcharge-Tdischarge Amplitude Charge Pumping (VT2ACP) is used to profile defect in the SiO2 and Al2O3 separately in Flash Memory based devices. It is shown that by independently controlling the pulse low timing “discharging time” and high level timing “charging time”, the contribution of interface and bulk Al2O3 traps can be separated. By using the ellipsometry and the measured intersection time tcharge to trap in the high- k (∼60 μs), SiO2 thickness of 0.87 nm and scanning rate of 0.19nm/dec is found. Using a slanted wafer, the result shows that in the case of thin SiO2 (∼1nm) the trap density close to the substrate (short tcharge) is one order of magnitude higher compared to thick SiO2 (∼3nm). For tSiO2 = 1.7nm all traps are in the SiO2 or SiO2/Al2O3 transition layer. Only for the thickest SiO2 layers (2.7 and 3 nm) the trap density becomes low and constant. Additionally WKB-approximation is used to calculate the filling probability of the traps (fT), the modeled scanning rate nearly doubles to ∼0.29 nm/dec and 0.27 nm/dec for amorphous and crystalline, respectively. In summary, the method of trap energy/depth profiling by using VT2ACP allows scanning from ∼0.5nm up to 1.2nm in depth and 0.1 to 0.7eV in energy range above the EcSi band depending on sample used. The results show that there exist significant interaction between SiO2 and Al2O3 when processed with PDA 1000°C. For amorphous Al2O3 (PDA 700°C) the impact of the precursor is not reflected in the SiO2 trap density while for crystalline Al2O3 no increase in trap density at 0.3eV above the EcSi band is observed.
{"title":"Deffect profiling in the SiO2/ Al2O3 interface using Variable Tcharge-Tdischarge Amplitude Charge Pumping (VT2ACP)","authors":"M. Zahid, R. Degraeve, M. Cho, L. Pantisano, D. R. Aguado, J. van Houdt, G. Groeseneken, M. Jurczak","doi":"10.1109/IRPS.2009.5173219","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173219","url":null,"abstract":"A Variable T<inf>charge</inf>-T<inf>discharge</inf> Amplitude Charge Pumping (VT<sup>2</sup>ACP) is used to profile defect in the SiO<inf>2</inf> and Al<inf>2</inf>O<inf>3</inf> separately in Flash Memory based devices. It is shown that by independently controlling the pulse low timing “discharging time” and high level timing “charging time”, the contribution of interface and bulk Al<inf>2</inf>O<inf>3</inf> traps can be separated. By using the ellipsometry and the measured intersection time t<inf>charge</inf> to trap in the high- k (∼60 μs), SiO<inf>2</inf> thickness of 0.87 nm and scanning rate of 0.19nm/dec is found. Using a slanted wafer, the result shows that in the case of thin SiO<inf>2</inf> (∼1nm) the trap density close to the substrate (short t<inf>charge</inf>) is one order of magnitude higher compared to thick SiO<inf>2</inf> (∼3nm). For t<inf>SiO2</inf> = 1.7nm all traps are in the SiO<inf>2</inf> or SiO<inf>2</inf>/Al<inf>2</inf>O<inf>3</inf> transition layer. Only for the thickest SiO<inf>2</inf> layers (2.7 and 3 nm) the trap density becomes low and constant. Additionally WKB-approximation is used to calculate the filling probability of the traps (f<inf>T</inf>), the modeled scanning rate nearly doubles to ∼0.29 nm/dec and 0.27 nm/dec for amorphous and crystalline, respectively. In summary, the method of trap energy/depth profiling by using VT<sup>2</sup>ACP allows scanning from ∼0.5nm up to 1.2nm in depth and 0.1 to 0.7eV in energy range above the E<inf>c</inf><sup>Si</sup> band depending on sample used. The results show that there exist significant interaction between SiO<inf>2</inf> and Al<inf>2</inf>O<inf>3</inf> when processed with PDA 1000°C. For amorphous Al<inf>2</inf>O<inf>3</inf> (PDA 700°C) the impact of the precursor is not reflected in the SiO<inf>2</inf> trap density while for crystalline Al<inf>2</inf>O<inf>3</inf> no increase in trap density at 0.3eV above the E<inf>c</inf><sup>Si</sup> band is observed.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116026229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173334
Y. C. Ong, D. Ang, K. Pey, S. O’Shea, K. Kakushima, T. Kawanago, H. Iwai, C. Tung
Evolution of electronic trap generation in the highdielectric constant (Hκ) layer and the interfacial layer (IL) of the Hκ gate stack and their interdependency is examined at nanoscopic resolution using scanning tunnelling microscopy (STM). We observed experimentally (i) trap generation in the dielectric layer next to the cathode is generally mismatched with pre-existing traps in the IL which exhibit stress induced leakage current (SILC) characteristics. (ii) Pre-existing SILC trap can evolve into a percolation path within the dielectric layer. (iii) pre-existing leakage path in the Hκ can accelerate trap generation in the IL due to electric field enhancement. Based on the experimental insight, a model on how BD of the Hκ gate stack is triggered by traps in the Hκ and IL layers is proposed.
{"title":"Real-time observation of trap generation by scanning tunneling microscopy and the correlation to high-κ gate stack breakdown","authors":"Y. C. Ong, D. Ang, K. Pey, S. O’Shea, K. Kakushima, T. Kawanago, H. Iwai, C. Tung","doi":"10.1109/IRPS.2009.5173334","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173334","url":null,"abstract":"Evolution of electronic trap generation in the highdielectric constant (Hκ) layer and the interfacial layer (IL) of the Hκ gate stack and their interdependency is examined at nanoscopic resolution using scanning tunnelling microscopy (STM). We observed experimentally (i) trap generation in the dielectric layer next to the cathode is generally mismatched with pre-existing traps in the IL which exhibit stress induced leakage current (SILC) characteristics. (ii) Pre-existing SILC trap can evolve into a percolation path within the dielectric layer. (iii) pre-existing leakage path in the Hκ can accelerate trap generation in the IL due to electric field enhancement. Based on the experimental insight, a model on how BD of the Hκ gate stack is triggered by traps in the Hκ and IL layers is proposed.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124806820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173225
T. Ohki, T. Kikkawa, Y. Inoue, M. Kanamura, N. Okamoto, K. Makiyama, K. Imanishi, H. Shigematsu, K. Joshin, N. Hara
In this paper, we describe highly reliable GaN high electron mobility transistors (HEMTs) for high-power and high-efficiency amplifiers. First, we present the reliability mechanisms and progress on the previously reported GaN HEMTs. Next, we introduce our specific device structure for GaN HEMTs for improving reliability. An n-GaN cap and optimized buffer layer are used to realize high efficiency and high reliability by suppressing current collapse and quiescent current (Idsq)-drift. Finally, we propose a new device process around the gate electrode for further improvement of reliability. Preventing gate edge silicidation leads to reduced gate leakage current and suppression of initial degradation in a DC-stress test under high-temperature and high-voltage conditions. Gate edge engineering plays a key role in reducing the gate leakage current and improving reliability.
{"title":"Reliability of GaN HEMTs: current status and future technology","authors":"T. Ohki, T. Kikkawa, Y. Inoue, M. Kanamura, N. Okamoto, K. Makiyama, K. Imanishi, H. Shigematsu, K. Joshin, N. Hara","doi":"10.1109/IRPS.2009.5173225","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173225","url":null,"abstract":"In this paper, we describe highly reliable GaN high electron mobility transistors (HEMTs) for high-power and high-efficiency amplifiers. First, we present the reliability mechanisms and progress on the previously reported GaN HEMTs. Next, we introduce our specific device structure for GaN HEMTs for improving reliability. An n-GaN cap and optimized buffer layer are used to realize high efficiency and high reliability by suppressing current collapse and quiescent current (Idsq)-drift. Finally, we propose a new device process around the gate electrode for further improvement of reliability. Preventing gate edge silicidation leads to reduced gate leakage current and suppression of initial degradation in a DC-stress test under high-temperature and high-voltage conditions. Gate edge engineering plays a key role in reducing the gate leakage current and improving reliability.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130039323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173395
R. Vollertsen, H. Reisinger, S. Aresu, C. Schlunder
This work demonstrates that NBTI assessment by fast wafer level reliability methods is possible in a quantitative manner. This involves excluding time periods from the stress time that are used for restoration of damage recovered during stress interruption and a calibrated back extrapolation of measured recovery traces to short delay times based on the universal recovery equation. The development of the methodology, the challenges and the verification of the implemented algorithm are presented.
{"title":"Applying the universal recovery equation for fast wafer level reliability monitoring NBTI assessment","authors":"R. Vollertsen, H. Reisinger, S. Aresu, C. Schlunder","doi":"10.1109/IRPS.2009.5173395","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173395","url":null,"abstract":"This work demonstrates that NBTI assessment by fast wafer level reliability methods is possible in a quantitative manner. This involves excluding time periods from the stress time that are used for restoration of damage recovered during stress interruption and a calibrated back extrapolation of measured recovery traces to short delay times based on the universal recovery equation. The development of the methodology, the challenges and the verification of the implemented algorithm are presented.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114513176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173265
Bio Kim, Seungjae Baik, Sunjung Kim, Joon-Gon Lee, B. Koo, Siyoung Choi, J. Moon
We investigated threshold voltage shifts after program pulse in charge trap flash memory by measuring drain current changes. We have found threshold voltage shifts can be characterized as a function of not only the materials of tunnel oxide, trap layer, blocking layer, but also physical parameters like device size and electrical measurement environment such as program voltage target and gate bias voltage. This approach can identify the root cause of initial threshold voltage shifts in charge trap flash memory devices.
{"title":"Characterization of threshold voltage instability after program in charge trap flash memory","authors":"Bio Kim, Seungjae Baik, Sunjung Kim, Joon-Gon Lee, B. Koo, Siyoung Choi, J. Moon","doi":"10.1109/IRPS.2009.5173265","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173265","url":null,"abstract":"We investigated threshold voltage shifts after program pulse in charge trap flash memory by measuring drain current changes. We have found threshold voltage shifts can be characterized as a function of not only the materials of tunnel oxide, trap layer, blocking layer, but also physical parameters like device size and electrical measurement environment such as program voltage target and gate bias voltage. This approach can identify the root cause of initial threshold voltage shifts in charge trap flash memory devices.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130062666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173244
S. Phillips, A. Sutton, A. Appaswamy, M. Bellini, J. Cressler, A. Grillo, G. Vizkelethy, P. Dodd, Mike McCurdy, R. Reed, P. Marshall
We investigate, for the first time, the impact of deep trench isolation on the total ionizing dose (TID) and single event upset (SEU) tolerance of advanced SiGe HBTs. We employ a combination of 63MeV protons, 10keV X-rays, and 36MeV oxygen ion microbeam irradiation and compare a 3rd generation, high-performance (HP), deep-trench isolated, SiGe BiCMOS platform with its cost-performance (CP) variant without deeptrenches. Although the CP SiGe HBTs are shown to be more susceptible to TID damage, the elevated damage is not attributed to variations in deep trench isolation (DTI), but to spacer oxide differences. CP SiGe HBTs are surprisingly found to offer a potential built-in self-mitigation mechanism for SEU, which is a direct result of the influence of the deep trench isolation on the charge collection dynamics associated with ion strikes. Calibrated, full 3D ion strike TCAD simulations are employed to explain the results, revealing substantial enhancement of radial charge diffusion for structures implemented with little to no deep trench. Mitigation of charge collection events are found to occur for emitter-center strikes for devices with limited/eliminated DTI with the caveat of larger collection for outside-DTI ion strikes.
{"title":"Impact of deep trench isolation on advanced SiGe HBT reliability in radiation environments","authors":"S. Phillips, A. Sutton, A. Appaswamy, M. Bellini, J. Cressler, A. Grillo, G. Vizkelethy, P. Dodd, Mike McCurdy, R. Reed, P. Marshall","doi":"10.1109/IRPS.2009.5173244","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173244","url":null,"abstract":"We investigate, for the first time, the impact of deep trench isolation on the total ionizing dose (TID) and single event upset (SEU) tolerance of advanced SiGe HBTs. We employ a combination of 63MeV protons, 10keV X-rays, and 36MeV oxygen ion microbeam irradiation and compare a 3rd generation, high-performance (HP), deep-trench isolated, SiGe BiCMOS platform with its cost-performance (CP) variant without deeptrenches. Although the CP SiGe HBTs are shown to be more susceptible to TID damage, the elevated damage is not attributed to variations in deep trench isolation (DTI), but to spacer oxide differences. CP SiGe HBTs are surprisingly found to offer a potential built-in self-mitigation mechanism for SEU, which is a direct result of the influence of the deep trench isolation on the charge collection dynamics associated with ion strikes. Calibrated, full 3D ion strike TCAD simulations are employed to explain the results, revealing substantial enhancement of radial charge diffusion for structures implemented with little to no deep trench. Mitigation of charge collection events are found to occur for emitter-center strikes for devices with limited/eliminated DTI with the caveat of larger collection for outside-DTI ion strikes.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127537519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173291
H. Enichlmair, J. M. Park, S. Carniello, B. Loeffler, R. Minixhofer, M. Levy
The hot carrier stress induced device degradation of a p-type LDMOS high voltage transistor is investigated at different stress conditions. The influence of shallow trench corner rounding and carbon ion implantation into the shallow trench region is discussed. Numerical device simulations, charge pumping measurements and electrical characterisations are used for these investigations.
{"title":"Hot carrier stress degradation modes in p-type high voltage LDMOS transistors","authors":"H. Enichlmair, J. M. Park, S. Carniello, B. Loeffler, R. Minixhofer, M. Levy","doi":"10.1109/IRPS.2009.5173291","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173291","url":null,"abstract":"The hot carrier stress induced device degradation of a p-type LDMOS high voltage transistor is investigated at different stress conditions. The influence of shallow trench corner rounding and carbon ion implantation into the shallow trench region is discussed. Numerical device simulations, charge pumping measurements and electrical characterisations are used for these investigations.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126508584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173330
E. Miranda, E. O'Connor, G. Hughes, P. Casey, K. Cherkaoui, S. Monaghan, R. Long, D. O'Connell, P. Hurley
In this work, we report on the occurrence of the soft breakdown (SBD) failure mode in 20nm-thick films of magnesium oxide (MgO) grown on Si substrates. To our knowledge, this is the first observation of this failure mechanism in a high-κ gate dielectric with such a large oxide thickness. We show that the I–V characteristics follow the power-law dependence typical of SBD conduction in a wider voltage range than that reported for SiO2. We pay special attention to the relationship between the magnitude of the current and the normalized differential conductance, and analyze the role played by the injection polarity and substrate type.
{"title":"Soft breakdown in MgO dielectric layers","authors":"E. Miranda, E. O'Connor, G. Hughes, P. Casey, K. Cherkaoui, S. Monaghan, R. Long, D. O'Connell, P. Hurley","doi":"10.1109/IRPS.2009.5173330","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173330","url":null,"abstract":"In this work, we report on the occurrence of the soft breakdown (SBD) failure mode in 20nm-thick films of magnesium oxide (MgO) grown on Si substrates. To our knowledge, this is the first observation of this failure mechanism in a high-κ gate dielectric with such a large oxide thickness. We show that the I–V characteristics follow the power-law dependence typical of SBD conduction in a wider voltage range than that reported for SiO2. We pay special attention to the relationship between the magnitude of the current and the normalized differential conductance, and analyze the role played by the injection polarity and substrate type.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131348171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173311
Stefan Hillebrecht, I. Polian, B. Becker, P. Ruther, S. Herwik, O. Paul
Integrated circuits are often subjected to mechanical stress resulting from external loads or intrinsic stress caused by the mismatch in thermal expansion coefficients of the applied materials. Interconnects and vias in these circuits are particularly jeopardized when applied in complementary metal-oxide semiconductor (CMOS)-based microelectromechanical systems (MEMS). In this paper, we characterize the reliability of interconnects using a heterogeneous CMOS/MEMS monitor chip manufactured using deep reactive ion etching. It comprises various daisy-chain structures with different combinations of interconnects integrated in a thin silicon membrane hinge subjected to tensile mechanical stress. The electro-mechanical testing is performed using a custom-made system that simultaneously applies mechanical stress and performs mechanical and electrical measurements. Experiments provide somewhat unexpected insight into patterns of failure of different types of interconnects.
{"title":"Reliability characterization of interconnects in CMOS integrated circuits under mechanical stress","authors":"Stefan Hillebrecht, I. Polian, B. Becker, P. Ruther, S. Herwik, O. Paul","doi":"10.1109/IRPS.2009.5173311","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173311","url":null,"abstract":"Integrated circuits are often subjected to mechanical stress resulting from external loads or intrinsic stress caused by the mismatch in thermal expansion coefficients of the applied materials. Interconnects and vias in these circuits are particularly jeopardized when applied in complementary metal-oxide semiconductor (CMOS)-based microelectromechanical systems (MEMS). In this paper, we characterize the reliability of interconnects using a heterogeneous CMOS/MEMS monitor chip manufactured using deep reactive ion etching. It comprises various daisy-chain structures with different combinations of interconnects integrated in a thin silicon membrane hinge subjected to tensile mechanical stress. The electro-mechanical testing is performed using a custom-made system that simultaneously applies mechanical stress and performs mechanical and electrical measurements. Experiments provide somewhat unexpected insight into patterns of failure of different types of interconnects.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129211576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173337
A. Nakajima, K. Itagaki, K. Horio
Two-dimensional transient analysis of field-plate AlGaN/GaN HEMTs and GaN MESFETs is performed, considering a deep donor and a deep acceptor in the semiinsulating GaN buffer layer. Quasi-pulsed I-V curves are derived from the transient characteristics. It is studied how the existence of a field plate affects buffer-related drain lag, gate lag and current collapse. It is shown that in both FETs, the drain lag is reduced by introducing a field plate, because electron injection into the buffer layer is weakened by it, and trapping effects are reduced. It is also shown that the buffer-related current collapse and gate lag are reduced in the field-plate structures. The dependence on SiN passivation layer thickness under the field plate is also studied, suggesting that there is an optimum thickness of the SiN layer to minimize buffer-related current collapse and drain lag in GaN HEMTs and MESFETs.
{"title":"Physical mechanism of buffer-related lag and current collapse in GaN-based FETs and their reduction by introducing a field plate","authors":"A. Nakajima, K. Itagaki, K. Horio","doi":"10.1109/IRPS.2009.5173337","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173337","url":null,"abstract":"Two-dimensional transient analysis of field-plate AlGaN/GaN HEMTs and GaN MESFETs is performed, considering a deep donor and a deep acceptor in the semiinsulating GaN buffer layer. Quasi-pulsed I-V curves are derived from the transient characteristics. It is studied how the existence of a field plate affects buffer-related drain lag, gate lag and current collapse. It is shown that in both FETs, the drain lag is reduced by introducing a field plate, because electron injection into the buffer layer is weakened by it, and trapping effects are reduced. It is also shown that the buffer-related current collapse and gate lag are reduced in the field-plate structures. The dependence on SiN passivation layer thickness under the field plate is also studied, suggesting that there is an optimum thickness of the SiN layer to minimize buffer-related current collapse and drain lag in GaN HEMTs and MESFETs.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116655826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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