Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173316
S. Cao, S. Beebe, A. Salman, M. Pelella, J. Chun, R. Dutton
In this paper, the improved field-effect diode (FED) has been characterized and modeled in 45 nm silicon-on-insulator (SOI) technology. It has been experimentally shown to be suitable for pad-based local clamping under normal supply voltage (Vdd) range (below 1 V) in high-speed integrated circuits. ESD protection capabilities are investigated using very fast transmission line pulse (VF-TLP) tests to predict the device's performance in charged device model (CDM) ESD events. The FED's advantages in improving transient turn-on behavior and reducing DC leakage current have been analyzed and compared with other Silicon-Controlled-Rectifier (SCR)-based SOI device variations. Technology CAD (TCAD) simulations are used to interpret the turn-on behavior and the physical effects. Process tradeoffs have been evaluated. The work prepares the device for being directly applied to high-speed Input/Output (I/O) circuit and it addresses the severe challenge in CDM ESD protection. The improved device enables the adoption of local clamping scheme that expands the ESD design window.
{"title":"Field effect diode for effective CDM ESD protection in 45 nm SOI technology","authors":"S. Cao, S. Beebe, A. Salman, M. Pelella, J. Chun, R. Dutton","doi":"10.1109/IRPS.2009.5173316","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173316","url":null,"abstract":"In this paper, the improved field-effect diode (FED) has been characterized and modeled in 45 nm silicon-on-insulator (SOI) technology. It has been experimentally shown to be suitable for pad-based local clamping under normal supply voltage (Vdd) range (below 1 V) in high-speed integrated circuits. ESD protection capabilities are investigated using very fast transmission line pulse (VF-TLP) tests to predict the device's performance in charged device model (CDM) ESD events. The FED's advantages in improving transient turn-on behavior and reducing DC leakage current have been analyzed and compared with other Silicon-Controlled-Rectifier (SCR)-based SOI device variations. Technology CAD (TCAD) simulations are used to interpret the turn-on behavior and the physical effects. Process tradeoffs have been evaluated. The work prepares the device for being directly applied to high-speed Input/Output (I/O) circuit and it addresses the severe challenge in CDM ESD protection. The improved device enables the adoption of local clamping scheme that expands the ESD design window.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114179472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173382
Yi-Pin Fang, B. Vaidyanathan, A. Oates
Embedded DRAM has been widely used in System on Chip (SOC) systems due to its higher density than SRAM. Embedded DRAM soft error rate (SER) has become an important subject since more embedded dynamic random access memories (DRAM) are now embedded on the chip as technology advances. Experiments show alpha-SER rapidly declines with embedded DRAM scaling while neutron-SER is less significantly impacted. We develop a simple and rapid method to predict neutron- and alpha-SER scaling trends for embedded DRAM without the use of complicated simulation procedures.
{"title":"Soft error rate cross-technology prediction on embedded DRAM","authors":"Yi-Pin Fang, B. Vaidyanathan, A. Oates","doi":"10.1109/IRPS.2009.5173382","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173382","url":null,"abstract":"Embedded DRAM has been widely used in System on Chip (SOC) systems due to its higher density than SRAM. Embedded DRAM soft error rate (SER) has become an important subject since more embedded dynamic random access memories (DRAM) are now embedded on the chip as technology advances. Experiments show alpha-SER rapidly declines with embedded DRAM scaling while neutron-SER is less significantly impacted. We develop a simple and rapid method to predict neutron- and alpha-SER scaling trends for embedded DRAM without the use of complicated simulation procedures.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123921627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173363
M. Lin, N. Jou, James W. Liang, K. Su
Downstream Electromigration (EM) was studied on different multiple via structures. Structures with more via gained better EM performance improvement. Failure analysis showed different EM failure modes on these structures. Finite element analysis is applied to find out the current density profiles and their variation between these structures. Resistance increases due to EM induced void are also simulated and found to be dependent on size and location of void. The different EM results of these multiple via structures are explained with the current density results and the different diffusion patterns found.
{"title":"Effect of multiple via layout on electromigration performance and current density distribution in copper interconnect","authors":"M. Lin, N. Jou, James W. Liang, K. Su","doi":"10.1109/IRPS.2009.5173363","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173363","url":null,"abstract":"Downstream Electromigration (EM) was studied on different multiple via structures. Structures with more via gained better EM performance improvement. Failure analysis showed different EM failure modes on these structures. Finite element analysis is applied to find out the current density profiles and their variation between these structures. Resistance increases due to EM induced void are also simulated and found to be dependent on size and location of void. The different EM results of these multiple via structures are explained with the current density results and the different diffusion patterns found.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"702 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122002973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173369
A. Broué, J. Dhennin, C. Seguineau, X. Lafontan, C. Dieppedale, J. Desmarres, P. Pons, R. Plana
This paper demonstrates the efficiency of a new methodology using a commercial nanoindenter coupling with electrical measurement on test vehicles specially designed to investigate the micro contact reliability. This study examines the response of gold contacts with 5 μm2 square bumps under various levels of current flowing through contact asperities. Contact temperature rising is observed leading to shifts of the mechanical properties of contact material, modifications of the contact topology and a diminution of the time dependence creep effect. The data provides a better understanding of micro-scale contact physics especially failure mechanisms due to the heating of the contact on MEMS switches.
{"title":"Methodology to analyze failure mechanisms of ohmic contacts on MEMS switches","authors":"A. Broué, J. Dhennin, C. Seguineau, X. Lafontan, C. Dieppedale, J. Desmarres, P. Pons, R. Plana","doi":"10.1109/IRPS.2009.5173369","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173369","url":null,"abstract":"This paper demonstrates the efficiency of a new methodology using a commercial nanoindenter coupling with electrical measurement on test vehicles specially designed to investigate the micro contact reliability. This study examines the response of gold contacts with 5 μm2 square bumps under various levels of current flowing through contact asperities. Contact temperature rising is observed leading to shifts of the mechanical properties of contact material, modifications of the contact topology and a diminution of the time dependence creep effect. The data provides a better understanding of micro-scale contact physics especially failure mechanisms due to the heating of the contact on MEMS switches.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116882753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173246
M. Gadlage, J. Ahlbin, B. Narasimham, V. Ramachandran, C. Dinkins, B. Bhuva, peixiong zhao, R. Shuler
Combinational logic soft errors are expected to be the dominant reliability issue for advanced technologies. One of the major factors affecting the soft-error rates is single-event transient (SET) pulse widths. The SET pulse widths, which are controlled by drift, diffusion, and parasitic bipolar transistor parameters, are a strong function of operating temperature. In this work, heavy-ion induced SET pulse widths are reported at temperatures ranging from 25° to 100° C with an autonomous SET capture circuit. Experimental and simulation results in a 90nm bulk CMOS technology indicate an increase as high as 37% in average SET pulse width with increasing operating temperature, with some pulses almost 2 ns long at higher temperatures. The increase in the SET pulse width can be explained by the dependence of bipolar amplification on temperature.
{"title":"The effect of elevated temperature on digital single event transient pulse widths in a bulk CMOS technology","authors":"M. Gadlage, J. Ahlbin, B. Narasimham, V. Ramachandran, C. Dinkins, B. Bhuva, peixiong zhao, R. Shuler","doi":"10.1109/IRPS.2009.5173246","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173246","url":null,"abstract":"Combinational logic soft errors are expected to be the dominant reliability issue for advanced technologies. One of the major factors affecting the soft-error rates is single-event transient (SET) pulse widths. The SET pulse widths, which are controlled by drift, diffusion, and parasitic bipolar transistor parameters, are a strong function of operating temperature. In this work, heavy-ion induced SET pulse widths are reported at temperatures ranging from 25° to 100° C with an autonomous SET capture circuit. Experimental and simulation results in a 90nm bulk CMOS technology indicate an increase as high as 37% in average SET pulse width with increasing operating temperature, with some pulses almost 2 ns long at higher temperatures. The increase in the SET pulse width can be explained by the dependence of bipolar amplification on temperature.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115185476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173324
T. Chen, Young Moon Kim, Kyunglok Kim, Y. Kameda, M. Mizuno, S. Mitra
Large-scale experimental data from 90nm test chips consisting of 49,152 transistors, and experiments on 90nm test chips containing inverter chains are used to establish: 1. A gate-oxide early-life failure (ELF, also called infant mortality) candidate transistor produces gradually degraded drive currents over time; 2. A digital circuit path consisting of a gate-oxide ELF candidate transistor experiences gradual delay shifts over time before the circuit produces functional failures. These results may be utilized to effectively overcome ELF challenges in scaled CMOS technologies.
{"title":"Experimental study of gate oxide early-life failures","authors":"T. Chen, Young Moon Kim, Kyunglok Kim, Y. Kameda, M. Mizuno, S. Mitra","doi":"10.1109/IRPS.2009.5173324","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173324","url":null,"abstract":"Large-scale experimental data from 90nm test chips consisting of 49,152 transistors, and experiments on 90nm test chips containing inverter chains are used to establish: 1. A gate-oxide early-life failure (ELF, also called infant mortality) candidate transistor produces gradually degraded drive currents over time; 2. A digital circuit path consisting of a gate-oxide ELF candidate transistor experiences gradual delay shifts over time before the circuit produces functional failures. These results may be utilized to effectively overcome ELF challenges in scaled CMOS technologies.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115362869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173234
N. Wrachien, A. Cester, A. Pinato, M. Meneghini, A. Tazzoli, G. Meneghesso, J. Kováč, J. Jakabovic, D. Donoval
We study the charge trapping/detrapping kinetics on pentacene-based organic thin-film-transistors featuring SiO2 and SiO2/parylene C stack gate insulators. The threshold voltage variation is correlated with the gate pulse width and amplitude, and it is due to charge trapping, rather than permanent degradation. The detrapping kinetics is thermally-activated and it is accelerated if the device is illuminated. The additional parylene layer brings benefits by strongly reducing the charge trapping/detrapping, and increasing the hole mobility and the drain current.
{"title":"Threshold voltage instability in organic TFT with SiO2 and SiO2/parylene-stack dielectrics","authors":"N. Wrachien, A. Cester, A. Pinato, M. Meneghini, A. Tazzoli, G. Meneghesso, J. Kováč, J. Jakabovic, D. Donoval","doi":"10.1109/IRPS.2009.5173234","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173234","url":null,"abstract":"We study the charge trapping/detrapping kinetics on pentacene-based organic thin-film-transistors featuring SiO2 and SiO2/parylene C stack gate insulators. The threshold voltage variation is correlated with the gate pulse width and amplitude, and it is due to charge trapping, rather than permanent degradation. The detrapping kinetics is thermally-activated and it is accelerated if the device is illuminated. The additional parylene layer brings benefits by strongly reducing the charge trapping/detrapping, and increasing the hole mobility and the drain current.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124927226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173341
A. Madan, T. Thrivikraman, J. Cressler
We investigate the reliability of RF switches for high-power, high dynamic range RF applications. Switches in two different CMOS technology platforms (180 nm and 130 nm) were observed to fail catastrophically beyond 33 dBm RF input power. The switches were single-pole double-throw with series-shunt topology. The reliability of a standalone switching series transistor from a single-pole double-throw switch was analyzed to investigate the failure mechanisms involved. Gate dielectric breakdown at high RF input power is demonstrated to lead to the failure of RF switches. Finally, the effect of transistor failure on switch operation is discussed.
{"title":"Failure mechanisms in CMOS-based RF switches subjected to RF stress","authors":"A. Madan, T. Thrivikraman, J. Cressler","doi":"10.1109/IRPS.2009.5173341","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173341","url":null,"abstract":"We investigate the reliability of RF switches for high-power, high dynamic range RF applications. Switches in two different CMOS technology platforms (180 nm and 130 nm) were observed to fail catastrophically beyond 33 dBm RF input power. The switches were single-pole double-throw with series-shunt topology. The reliability of a standalone switching series transistor from a single-pole double-throw switch was analyzed to investigate the failure mechanisms involved. Gate dielectric breakdown at high RF input power is demonstrated to lead to the failure of RF switches. Finally, the effect of transistor failure on switch operation is discussed.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124932723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173271
L. Scipioni, W. Thompson, S. Sijbrandij, S. Ogawa
The helium ion microscope, a new imaging technology, is being applied also to sample modification. The application opportunity exists due to the extreme high resolution and the ability to gather analytical data as well as images. Possible applications include inspection, elemental analysis, and dopant concentration measurements.
{"title":"Material analysis with a helium ion microscope","authors":"L. Scipioni, W. Thompson, S. Sijbrandij, S. Ogawa","doi":"10.1109/IRPS.2009.5173271","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173271","url":null,"abstract":"The helium ion microscope, a new imaging technology, is being applied also to sample modification. The application opportunity exists due to the extreme high resolution and the ability to gather analytical data as well as images. Possible applications include inspection, elemental analysis, and dopant concentration measurements.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129826253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173245
D. Kobayashi, T. Makino, K. Hirose
Radiation-induced pulse noises called single-event transients, SETs, are becoming a serious soft-error source for logic VLSIs. Analytical models explicitly expressing the relationship between the pulse width and radiation/device/circuit parameters are desired as guidelines to develop optimized countermeasures. A simple mathematical expression is devised for characterizing SET pulse widths in SOI CMOS technologies. It is based on the physical mechanisms of the SETs and on the idea of Moll's storage time. Device simulations demonstrate that the expression explains pulse-width trends properly for large radiation-induced noise charges.
{"title":"Analytical expression for temporal width characterization of radiation-induced pulse noises in SOI CMOS logic gates","authors":"D. Kobayashi, T. Makino, K. Hirose","doi":"10.1109/IRPS.2009.5173245","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173245","url":null,"abstract":"Radiation-induced pulse noises called single-event transients, SETs, are becoming a serious soft-error source for logic VLSIs. Analytical models explicitly expressing the relationship between the pulse width and radiation/device/circuit parameters are desired as guidelines to develop optimized countermeasures. A simple mathematical expression is devised for characterizing SET pulse widths in SOI CMOS technologies. It is based on the physical mechanisms of the SETs and on the idea of Moll's storage time. Device simulations demonstrate that the expression explains pulse-width trends properly for large radiation-induced noise charges.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121318071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：