Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173308
A. Bravaix, C. Guérin, Vincent Huard, David Roy, J. M. Roux, Emmanuel Vincent
Channel Hot-Carrier degradation presents a renewed interest in the last NMOS nodes where the device reliability of bulk silicon (core) 40nm and Input/Output (IO) device is difficult to achieve at high temperature as a function of supply voltage VDD and back bias VBS. A three mode interface trap generation is proposed based on the energy acquisition involved in distinct interactions in all the VGS, VDS (VBS) conditions as a single IDS lifetime dependence is observed with VGD > 0. This gives a new age(t) function useful for accurate DC to AC transfers. Positive temperature activation is explained by the rise of ionization rate with electron-electron scattering (medium IDS) and multi vibrational excitation (higher IDS) which increase the H desorption by thermal emission. The use of forward VBS has shown no gain under CHC for both device types. The main limitation occurs under reverse VBS = −VDD in IO where the smaller temperature activation partially compensates the larger damage. In that case a security margin can be established giving a limit of VBS = −VDD/2 for design reliability.
{"title":"Hot-Carrier acceleration factors for low power management in DC-AC stressed 40nm NMOS node at high temperature","authors":"A. Bravaix, C. Guérin, Vincent Huard, David Roy, J. M. Roux, Emmanuel Vincent","doi":"10.1109/IRPS.2009.5173308","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173308","url":null,"abstract":"Channel Hot-Carrier degradation presents a renewed interest in the last NMOS nodes where the device reliability of bulk silicon (core) 40nm and Input/Output (IO) device is difficult to achieve at high temperature as a function of supply voltage VDD and back bias V<inf>BS</inf>. A three mode interface trap generation is proposed based on the energy acquisition involved in distinct interactions in all the V<inf>GS</inf>, V<inf>DS</inf> (V<inf>BS</inf>) conditions as a single I<inf>DS</inf> lifetime dependence is observed with V<inf>GD</inf> > 0. This gives a new age(t) function useful for accurate DC to AC transfers. Positive temperature activation is explained by the rise of ionization rate with electron-electron scattering (medium I<inf>DS</inf>) and multi vibrational excitation (higher I<inf>DS</inf>) which increase the H desorption by thermal emission. The use of forward VBS has shown no gain under CHC for both device types. The main limitation occurs under reverse V<inf>BS</inf> = −V<inf>DD</inf> in IO where the smaller temperature activation partially compensates the larger damage. In that case a security margin can be established giving a limit of V<inf>BS</inf> = −V<inf>DD</inf>/2 for design reliability.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127314716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173238
M. Terai, S. Kotsuji, H. Hada, N. Iguchi, T. Ichihashi, S. Fujieda
We investigated the effect of ReRAM-stack asymmetry on read disturb immunity. Stacking stoichiometric Ta2O5 and ultrathin TiO2 led to bipolar switching property. Filament (conduction path) penetrated both Ta2O5 and TiO2 layer. Because single Ta2O5 film has no switching property, the resistance was not changed under positive bias on Ta2O5-side electrode. Under negative bias, the resistance of the filament near TiO2-side electrode increases because of anodic oxidation. A high read-disturb immunity were achieved by using the 1T1R ReRAM of this stack. These results can be attributed to the asymmetric switching behavior of the stoichiometric Ta2O5/ultrathin-TiO2 stack.
{"title":"Effect of ReRAM-stack asymmetry on read disturb immunity","authors":"M. Terai, S. Kotsuji, H. Hada, N. Iguchi, T. Ichihashi, S. Fujieda","doi":"10.1109/IRPS.2009.5173238","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173238","url":null,"abstract":"We investigated the effect of ReRAM-stack asymmetry on read disturb immunity. Stacking stoichiometric Ta<inf>2</inf>O<inf>5</inf> and ultrathin TiO<inf>2</inf> led to bipolar switching property. Filament (conduction path) penetrated both Ta<inf>2</inf>O<inf>5</inf> and TiO<inf>2</inf> layer. Because single Ta<inf>2</inf>O<inf>5</inf> film has no switching property, the resistance was not changed under positive bias on Ta<inf>2</inf>O<inf>5</inf>-side electrode. Under negative bias, the resistance of the filament near TiO<inf>2</inf>-side electrode increases because of anodic oxidation. A high read-disturb immunity were achieved by using the 1T1R ReRAM of this stack. These results can be attributed to the asymmetric switching behavior of the stoichiometric Ta<inf>2</inf>O<inf>5</inf>/ultrathin-TiO<inf>2</inf> stack.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127259990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173294
R. Dauskardt
Materials and interfaces in microelectronic device structures operate near the envelope of their mechanical and adhesive properties with remarkably high levels of film stress. Debonding and cohesive fracture are major challenges for device reliability at all levels of processing and packaging.
{"title":"Thermomechanical reliability for emerging device technologies: Implications for ULK integration, 3-D structures and packaging","authors":"R. Dauskardt","doi":"10.1109/IRPS.2009.5173294","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173294","url":null,"abstract":"Materials and interfaces in microelectronic device structures operate near the envelope of their mechanical and adhesive properties with remarkably high levels of film stress. Debonding and cohesive fracture are major challenges for device reliability at all levels of processing and packaging.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132479018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173401
D. Ioannou, D. Harmon, W. Abadeer
The impact of charging damage from plasma processes on device and gate dielectric reliability is investigated for MOSFETs fabricated in an SOI CMOS RF Switch technology. Although results from voltage breakdown measurements do not reveal any indication of plasma damage, detrimental antenna effects are observed on the negative bias temperature instability (NBTI) and hot carrier device performance. With regard to NBTI in P-channel SOI MOSFETs in particular, relaxation experiments are carried out under various bias conditions. Recovery effects which are well known for intrinsic NBTI are also observed for the antenna devices, but are found to be reduced relative to that of control devices.
{"title":"Investigation of Plasma Charging damage impact on device and gate dielectric reliability in 180nm SOI CMOS RF switch technology","authors":"D. Ioannou, D. Harmon, W. Abadeer","doi":"10.1109/IRPS.2009.5173401","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173401","url":null,"abstract":"The impact of charging damage from plasma processes on device and gate dielectric reliability is investigated for MOSFETs fabricated in an SOI CMOS RF Switch technology. Although results from voltage breakdown measurements do not reveal any indication of plasma damage, detrimental antenna effects are observed on the negative bias temperature instability (NBTI) and hot carrier device performance. With regard to NBTI in P-channel SOI MOSFETs in particular, relaxation experiments are carried out under various bias conditions. Recovery effects which are well known for intrinsic NBTI are also observed for the antenna devices, but are found to be reduced relative to that of control devices.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115647632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173390
W. J. Liu, D. Huang, Q. Sun, C. Liao, L. Zhang, Z. Gan, W. Wong, Ming-Fu Li
NBTI in pMOSFETs with plasma (PNO) and thermal (TNO) nitrided SiON gate oxides are re-investigated using our newly developed on-the-fly interface trap (OFIT) and fast pulse I–V measurement (FPM) methods. The threshold voltage shift ΔVTH is quantitatively decomposed into interface trap and oxide charge components. It is found that the interface trap generation under stress follows the power law with the same power index n and its temperature dependence, indicating the same interface degradation mechanism for both PNO and TNO devices. The NBTI degradation in TNO devices is larger than those in PNO devices, particularly the larger component of oxide charge. The result is explained by the different N profile of TNO from that of PNO devices, as supported by the first principle calculation.
{"title":"Studies of NBTI in pMOSFETs with thermal and plasma nitrided SiON gate oxides by OFIT and FPM methods","authors":"W. J. Liu, D. Huang, Q. Sun, C. Liao, L. Zhang, Z. Gan, W. Wong, Ming-Fu Li","doi":"10.1109/IRPS.2009.5173390","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173390","url":null,"abstract":"NBTI in pMOSFETs with plasma (PNO) and thermal (TNO) nitrided SiON gate oxides are re-investigated using our newly developed on-the-fly interface trap (OFIT) and fast pulse I–V measurement (FPM) methods. The threshold voltage shift ΔVTH is quantitatively decomposed into interface trap and oxide charge components. It is found that the interface trap generation under stress follows the power law with the same power index n and its temperature dependence, indicating the same interface degradation mechanism for both PNO and TNO devices. The NBTI degradation in TNO devices is larger than those in PNO devices, particularly the larger component of oxide charge. The result is explained by the different N profile of TNO from that of PNO devices, as supported by the first principle calculation.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115863822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173357
Hiroshi Miyazaki, D. Kodama
TDDB-lifetime distribution of asymmetric pattern (perpendicular-faced comb) was estimated using a 3-dimensional electrostatic model calculation and its statistical treatment based on the percolation theory. Nanometer-size small cells which represent the minimum unit of electric isolation are placed along the perimeter of an asymmetric pattern. In the model, a dielectric breakdown occurs when a series of defective cells form a path through the potential barrier. The local electric field near the cathode dictates the percolation-path length (tunneling distance). The model suggests that a negative bias at the pattern tips provides a shorter percolation path due to steep gradient of potential, resulting in a shorter lifetime. However, in contrast to the model predictions the experimental data do show only a small difference between positive and negative biases. Therefore, the theoretical estimation from the ideal electric field leads us too much shorter lifetime than the real case.
{"title":"TDDB lifetime of asymmetric patterns and its comprehension from percolation theory","authors":"Hiroshi Miyazaki, D. Kodama","doi":"10.1109/IRPS.2009.5173357","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173357","url":null,"abstract":"TDDB-lifetime distribution of asymmetric pattern (perpendicular-faced comb) was estimated using a 3-dimensional electrostatic model calculation and its statistical treatment based on the percolation theory. Nanometer-size small cells which represent the minimum unit of electric isolation are placed along the perimeter of an asymmetric pattern. In the model, a dielectric breakdown occurs when a series of defective cells form a path through the potential barrier. The local electric field near the cathode dictates the percolation-path length (tunneling distance). The model suggests that a negative bias at the pattern tips provides a shorter percolation path due to steep gradient of potential, resulting in a shorter lifetime. However, in contrast to the model predictions the experimental data do show only a small difference between positive and negative biases. Therefore, the theoretical estimation from the ideal electric field leads us too much shorter lifetime than the real case.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127596982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173287
E. Pop, S. Dutta, D. Estrada, A. Liao
We explore several aspects of reliability in carbon nanotube transistors, including their physical dependence on diameter. Avalanche behavior is found at high fields (5–10 V/μm), while Joule breakdown is reached at high current and heating, in the presence of oxygen. Finally, we describe a method for minimizing hysteresis effects via pulsed measurements.
{"title":"Avalanche, joule breakdown and hysteresis in carbon nanotube transistors","authors":"E. Pop, S. Dutta, D. Estrada, A. Liao","doi":"10.1109/IRPS.2009.5173287","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173287","url":null,"abstract":"We explore several aspects of reliability in carbon nanotube transistors, including their physical dependence on diameter. Avalanche behavior is found at high fields (5–10 V/μm), while Joule breakdown is reached at high current and heating, in the presence of oxygen. Finally, we describe a method for minimizing hysteresis effects via pulsed measurements.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132559383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173318
M. Vilmay, D. Roy, C. Monget, F. Volpi, J. Chaix
SiOCH low-k dielectrics introduction in copper interconnects associated to the critical dimensions reduction in sub 45nm technology nodes is a challenge for reliability engineers. Circuit wear-out linked to low-k dielectric breakdown is now becoming a major concern. With the reduction of the line to line spacing, the control of the copper line topology is becoming a first order parameter governing the low-k dielectric reliability. Improving the low-k reliability requires to discriminate each topological effect and quantify its impact on the lifetime at product level. This paper demonstrates the importance of the copper line shape, of the line edge roughness (LER) and of the median line to line spacing variation within the wafer on the low-k dielectrics reliability. Moreover, simple analytical models are described to quantify each effect on the Time-Dependant Dielectric Breakdown (TDDB) and particularly on the final product lifetime. Some advices are given to avoid erroneous lifetime projection.
{"title":"Copper line topology impact on the SiOCH low-k reliability in sub 45nm technology node. From the time-dependent dielectric breakdown to the product lifetime","authors":"M. Vilmay, D. Roy, C. Monget, F. Volpi, J. Chaix","doi":"10.1109/IRPS.2009.5173318","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173318","url":null,"abstract":"SiOCH low-k dielectrics introduction in copper interconnects associated to the critical dimensions reduction in sub 45nm technology nodes is a challenge for reliability engineers. Circuit wear-out linked to low-k dielectric breakdown is now becoming a major concern. With the reduction of the line to line spacing, the control of the copper line topology is becoming a first order parameter governing the low-k dielectric reliability. Improving the low-k reliability requires to discriminate each topological effect and quantify its impact on the lifetime at product level. This paper demonstrates the importance of the copper line shape, of the line edge roughness (LER) and of the median line to line spacing variation within the wafer on the low-k dielectrics reliability. Moreover, simple analytical models are described to quantify each effect on the Time-Dependant Dielectric Breakdown (TDDB) and particularly on the final product lifetime. Some advices are given to avoid erroneous lifetime projection.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131774310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173224
B. Kaczer, T. Grasser, J. Martín-Martínez, E. Simoen, M. Aoulaiche, P. Roussel, G. Groeseneken
Broad similarity between negative bias temperature instability (NBTI) relaxation and 1/ƒ noise is observed. Individual transitions in NBTI relaxation in small pFETs are observed and Poisson defect number statistics is inferred. Finally, it is argued that the wide distribution of defect times should be considered in addition to defect number variation in small devices.
{"title":"NBTI from the perspective of defect states with widely distributed time scales","authors":"B. Kaczer, T. Grasser, J. Martín-Martínez, E. Simoen, M. Aoulaiche, P. Roussel, G. Groeseneken","doi":"10.1109/IRPS.2009.5173224","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173224","url":null,"abstract":"Broad similarity between negative bias temperature instability (NBTI) relaxation and 1/ƒ noise is observed. Individual transitions in NBTI relaxation in small pFETs are observed and Poisson defect number statistics is inferred. Finally, it is argued that the wide distribution of defect times should be considered in addition to defect number variation in small devices.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132306890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173344
M. Shrivastava, J. Schneider, M. Baghini, H. Gossner, V. Rao
A novel DeMOS device with modified body and source region in grounded gate (gg) NMOS configuration for ESD protection is proposed. Detailed 3D simulations indicate a high failure threshold because of moving current filaments and self-protection from gate oxide breakdown, even for fast transients. A detailed physics of second basepushout and moving filaments is discussed.
{"title":"Highly resistive body STI NDeMOS: An optimized DeMOS device to achieve moving current filaments for robust ESD protection","authors":"M. Shrivastava, J. Schneider, M. Baghini, H. Gossner, V. Rao","doi":"10.1109/IRPS.2009.5173344","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173344","url":null,"abstract":"A novel DeMOS device with modified body and source region in grounded gate (gg) NMOS configuration for ESD protection is proposed. Detailed 3D simulations indicate a high failure threshold because of moving current filaments and self-protection from gate oxide breakdown, even for fast transients. A detailed physics of second basepushout and moving filaments is discussed.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134373374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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