Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173392
H. Jung, T. Park, Jeong Hwan Kim, Sang Young Lee, Joohwi Lee, Himchan Oh, Kwang Duck Na, Jung-min Park, Weon-hong Kim, Min-woo Song, N. Lee, C. Hwang
HfO2, HfZrxOy and ZrO2 gate dielectrics are systematically compared in terms of the nMOS PBTI and pMOS NBTI. Compared to HfO2, ZrO2 exhibits higher capacitance and superior nMOS mobility characteristics. In addition, as the ZrO2 content increases, Vth shift under the nMOS PBTI stress is dramatically reduced. This is mainly contributed to the lower density of pre-existing bulk traps related to the oxygen vacancies.
{"title":"Systematic study on bias temperature instability of various high-k gate dielectrics ; HfO2, HfZrxOy and ZrO2","authors":"H. Jung, T. Park, Jeong Hwan Kim, Sang Young Lee, Joohwi Lee, Himchan Oh, Kwang Duck Na, Jung-min Park, Weon-hong Kim, Min-woo Song, N. Lee, C. Hwang","doi":"10.1109/IRPS.2009.5173392","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173392","url":null,"abstract":"HfO<inf>2</inf>, HfZr<inf>x</inf>O<inf>y</inf> and ZrO<inf>2</inf> gate dielectrics are systematically compared in terms of the nMOS PBTI and pMOS NBTI. Compared to HfO<inf>2</inf>, ZrO<inf>2</inf> exhibits higher capacitance and superior nMOS mobility characteristics. In addition, as the ZrO<inf>2</inf> content increases, V<inf>th</inf> shift under the nMOS PBTI stress is dramatically reduced. This is mainly contributed to the lower density of pre-existing bulk traps related to the oxygen vacancies.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133388096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173383
A. Prokofiev, J. Blomgren, S. Platt, R. Nolte, S. Rottger, A. N. Smirnov
ANITA (Atmospheric-like Neutrons from thIck TArget), a new neutron facility for accelerated testing of electronic components and systems for neutron-induced single event effects, has been installed at The Svedberg Laboratory in Uppsala, Sweden. Results of characterization measurements are reported.
{"title":"ANITA — a new neutron facility for accelerated SEE testing at the svedberg laboratory","authors":"A. Prokofiev, J. Blomgren, S. Platt, R. Nolte, S. Rottger, A. N. Smirnov","doi":"10.1109/IRPS.2009.5173383","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173383","url":null,"abstract":"ANITA (Atmospheric-like Neutrons from thIck TArget), a new neutron facility for accelerated testing of electronic components and systems for neutron-induced single event effects, has been installed at The Svedberg Laboratory in Uppsala, Sweden. Results of characterization measurements are reported.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114490844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173272
Magdalena Sienkiewcz, A. Firiti, O. Crépel, P. Perdu, K. Sanchez, D. Lewis
The soft defect localization on analog or mixed-mode ICs is becoming more and more challenging due to their increasing complexity and integration. New techniques based on dynamic laser stimulation are promising for analog and mixedmode ICs. Unfortunately, the considerable intrinsic sensitivity of this kind of devices under laser stimulation makes the defect localization results complex to analyze. As a matter of fact, the laser sensitivity mapping contains not only abnormal sensitive regions but also naturally sensitive ones. In order to overcome this issue by extracting the abnormal spots and therefore localize the defect, we propose in this paper a methodology that can improve the FA efficiency and accuracy. It consists on combining the mapping results with the electrical simulation of laser stimulation impact on the device. First, we will present the concept of the methodology. Then, we will show one case study on a mixed-mode IC illustrating the soft defect localization by using laser mapping technique & standard electrical simulations. Furthermore, we will argument the interest of a new methodology and we will show two simple examples from our experiments to validate it.
{"title":"Methodology to support laser-localized soft defects on analog and mixed-mode advanced ICs","authors":"Magdalena Sienkiewcz, A. Firiti, O. Crépel, P. Perdu, K. Sanchez, D. Lewis","doi":"10.1109/IRPS.2009.5173272","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173272","url":null,"abstract":"The soft defect localization on analog or mixed-mode ICs is becoming more and more challenging due to their increasing complexity and integration. New techniques based on dynamic laser stimulation are promising for analog and mixedmode ICs. Unfortunately, the considerable intrinsic sensitivity of this kind of devices under laser stimulation makes the defect localization results complex to analyze. As a matter of fact, the laser sensitivity mapping contains not only abnormal sensitive regions but also naturally sensitive ones. In order to overcome this issue by extracting the abnormal spots and therefore localize the defect, we propose in this paper a methodology that can improve the FA efficiency and accuracy. It consists on combining the mapping results with the electrical simulation of laser stimulation impact on the device. First, we will present the concept of the methodology. Then, we will show one case study on a mixed-mode IC illustrating the soft defect localization by using laser mapping technique & standard electrical simulations. Furthermore, we will argument the interest of a new methodology and we will show two simple examples from our experiments to validate it.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133259614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173255
S. Pai, J. Lee, K. Ng, R. Hsiao, K. Su, E.N. Chou
A collaborative framework is presented to address the reliability challenges faced in a fabless-foundry environment. Examples are given to show the effectiveness of this framework for both infant mortality and long-term reliability risk. Through design-for-reliability, optimum process standardization and selective customization, defect density reduction and electrical screening, reliability of the highest level has been achieved in FPGA devices suitable for enterprise, automotive and aerospace applications, all in a fabless-foundry environment.
{"title":"Reliability framework in a fabless-foundry environment","authors":"S. Pai, J. Lee, K. Ng, R. Hsiao, K. Su, E.N. Chou","doi":"10.1109/IRPS.2009.5173255","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173255","url":null,"abstract":"A collaborative framework is presented to address the reliability challenges faced in a fabless-foundry environment. Examples are given to show the effectiveness of this framework for both infant mortality and long-term reliability risk. Through design-for-reliability, optimum process standardization and selective customization, defect density reduction and electrical screening, reliability of the highest level has been achieved in FPGA devices suitable for enterprise, automotive and aerospace applications, all in a fabless-foundry environment.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133477326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173304
A. Kerber, E. Cartier, B. Linder, S. Krishnan, T. Nigam
Extensive breakdown measurements with large statistic confirm that the TDDB failure distribution follows Poisson area scaling. However, towards larger areas and lower failure percentiles the distribution changes in ways similar to those reported for progressive breakdown in poly Si/SiON gate stacks. The change in failure distribution is found to be more pronounced for nFET than for pFET devices. In addition AC TDDB testing was explored, confirming the shape of the DC failure distributions but shows a significant reduction in TDDB lifetime for nFET devices.
{"title":"TDDB failure distribution of metal gate/high-k CMOS devices on SOI substrates","authors":"A. Kerber, E. Cartier, B. Linder, S. Krishnan, T. Nigam","doi":"10.1109/IRPS.2009.5173304","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173304","url":null,"abstract":"Extensive breakdown measurements with large statistic confirm that the TDDB failure distribution follows Poisson area scaling. However, towards larger areas and lower failure percentiles the distribution changes in ways similar to those reported for progressive breakdown in poly Si/SiON gate stacks. The change in failure distribution is found to be more pronounced for nFET than for pFET devices. In addition AC TDDB testing was explored, confirming the shape of the DC failure distributions but shows a significant reduction in TDDB lifetime for nFET devices.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132818751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173231
L. Trevisanello, F. de Zuani, M. Meneghini, N. Trivellin, E. Zanoni, G. Meneghesso
The results achieved in an accelerated life-time test on Phosphor-Converted Light Emitting Diodes (PC-LEDs) have been reported. Two different families of commercially available low-flux devices have been widely characterized and a comparative analysis on performances has been carried out. A wide set of devices has been submitted to a combined electrothermal accelerated stress under different aging conditions. The stress induced a luminous flux decay on LEDs from both series. In particular, the lumen decay was found to be thermally activated for one set of devices. The aged devices showed also a degradation of chromatic properties, in terms of a blue or yellow shift for the two different families. The failure modes found have been detected also in devices aged at constant temperature and no bias. The degradation mechanism responsible for lumen decay and chromatic shift was ascribed to the thermally activated package instabilities. A failure analysis has been carried out on failed devices, detecting different failure modes related to the package (chip detachment) and to the chip (generation of low impedance paths that shorted the junction).
{"title":"Thermally activated degradation and package instabilities of low flux LEDS","authors":"L. Trevisanello, F. de Zuani, M. Meneghini, N. Trivellin, E. Zanoni, G. Meneghesso","doi":"10.1109/IRPS.2009.5173231","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173231","url":null,"abstract":"The results achieved in an accelerated life-time test on Phosphor-Converted Light Emitting Diodes (PC-LEDs) have been reported. Two different families of commercially available low-flux devices have been widely characterized and a comparative analysis on performances has been carried out. A wide set of devices has been submitted to a combined electrothermal accelerated stress under different aging conditions. The stress induced a luminous flux decay on LEDs from both series. In particular, the lumen decay was found to be thermally activated for one set of devices. The aged devices showed also a degradation of chromatic properties, in terms of a blue or yellow shift for the two different families. The failure modes found have been detected also in devices aged at constant temperature and no bias. The degradation mechanism responsible for lumen decay and chromatic shift was ascribed to the thermally activated package instabilities. A failure analysis has been carried out on failed devices, detecting different failure modes related to the package (chip detachment) and to the chip (generation of low impedance paths that shorted the junction).","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"11 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133040828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173297
K. Croes, C. Wilson, M. Lofrano, Y. Travaly, D. de Roest, Z. Tokei, G. Beyer
The time and temperature dependence of Stress-Induced-Voiding below and in copper VIA's with a diameter of 80nm integrated in a k=2.5 material was studied. The focus was on the early phase of the voiding process. To accelerate the degradation, test structures with big metal plates below and/or above the VIA were used. We found two degradation mechanisms in which one dominated below and the other dominated above a certain temperature. The first mechanism has an activation energy of 0.9eV and is the result of interface-diffusion driven by a stress-gradient. This mechanism was more pronounced below the VIA, but was significant in the VIA as well. The second mechanism has an activation energy of 1.2eV, which is argued to be driven by grain boundary diffusion due to a vacancy gradient in and above the VIA. To explain both mechanisms, an addition to the traditional stress-creep model is proposed and fits our data well. Additionally, it is discussed that VIA's connected to the center of big metal plates above and below the VIA are less susceptible to SIV compared to VIA's connected to line ends either below or on top of the VIA. We support our argumentation and analytical modeling with Finite Element Modeling.
{"title":"Time and temperature dependence of early stage Stress-Induced-Voiding in Cu/low-k interconnects","authors":"K. Croes, C. Wilson, M. Lofrano, Y. Travaly, D. de Roest, Z. Tokei, G. Beyer","doi":"10.1109/IRPS.2009.5173297","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173297","url":null,"abstract":"The time and temperature dependence of Stress-Induced-Voiding below and in copper VIA's with a diameter of 80nm integrated in a k=2.5 material was studied. The focus was on the early phase of the voiding process. To accelerate the degradation, test structures with big metal plates below and/or above the VIA were used. We found two degradation mechanisms in which one dominated below and the other dominated above a certain temperature. The first mechanism has an activation energy of 0.9eV and is the result of interface-diffusion driven by a stress-gradient. This mechanism was more pronounced below the VIA, but was significant in the VIA as well. The second mechanism has an activation energy of 1.2eV, which is argued to be driven by grain boundary diffusion due to a vacancy gradient in and above the VIA. To explain both mechanisms, an addition to the traditional stress-creep model is proposed and fits our data well. Additionally, it is discussed that VIA's connected to the center of big metal plates above and below the VIA are less susceptible to SIV compared to VIA's connected to line ends either below or on top of the VIA. We support our argumentation and analytical modeling with Finite Element Modeling.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117193218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173278
I. Hirano, Y. Nakasaki, S. Fukatsu, Akiko Masada, Y. Mitani, M. Goto, K. Nagatomo, S. Inumiya, K. Sekine
The slope parameter of Weibull plot of Tbd, β, strongly depends on gate electrode material for metalgate/HfSiON gate stacks in n-FETs. Furthermore β of Tbd under bipolar stress is larger than that under DC stress. From these results, it is found that the balance of injected carriers is strongly related to β in terms of the origin of large β for metal-gate/high-k.
{"title":"Impact of metal gate electrode on Weibull distribution of TDDB in HfSiON gate dielectrics","authors":"I. Hirano, Y. Nakasaki, S. Fukatsu, Akiko Masada, Y. Mitani, M. Goto, K. Nagatomo, S. Inumiya, K. Sekine","doi":"10.1109/IRPS.2009.5173278","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173278","url":null,"abstract":"The slope parameter of Weibull plot of Tbd, β, strongly depends on gate electrode material for metalgate/HfSiON gate stacks in n-FETs. Furthermore β of Tbd under bipolar stress is larger than that under DC stress. From these results, it is found that the balance of injected carriers is strongly related to β in terms of the origin of large β for metal-gate/high-k.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114968994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173309
S. Pal, Huikai Xie
With their large scan range and low drive voltages, electrothermally-actuated micromirrors have great potential in optical biomedical imaging applications, but the repeatability and reliability of such micromirrors are not well understood. This paper reports the conditions for achieving repeatability of the embedded resistive heater and the mirror tilt angle of an electrothermal bimorph micromirror. The upper limit of the actuation voltage that does not degrade the embedded heater performance has been established.
{"title":"Repeatability study of an electrothermally actuated micromirror","authors":"S. Pal, Huikai Xie","doi":"10.1109/IRPS.2009.5173309","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173309","url":null,"abstract":"With their large scan range and low drive voltages, electrothermally-actuated micromirrors have great potential in optical biomedical imaging applications, but the repeatability and reliability of such micromirrors are not well understood. This paper reports the conditions for achieving repeatability of the embedded resistive heater and the mirror tilt angle of an electrothermal bimorph micromirror. The upper limit of the actuation voltage that does not degrade the embedded heater performance has been established.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115276075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173364
L. Zhao, Z. Tokei, Gianni Giai Gischia, M. Pantouvaki, K. Croes, G. Beyer
A novel test structure to study intrinsic reliability of barrier/low-k is proposed. The structure is based on a planar capacitor design where low-k film is deposited after the patterning of the capacitor, followed by metallization and Cu CMP. This so called low-k planar capacitor structure provides several unique capabilities to study various aspects of barrier/low-k TDDB compared with the conventional damascene structures. Two of the unique capabilities are presented in this paper. First, TDDB from a damage-free low-k material has been measured for the first time using the low-k planar capacitor structure. Second, the test structure is sensitive enough to quantify the impact of selected process conditions, such as barrier re-sputter and plasma treatments, on TDDB.
{"title":"A novel test structure to study intrinsic reliability of barrier/low-k","authors":"L. Zhao, Z. Tokei, Gianni Giai Gischia, M. Pantouvaki, K. Croes, G. Beyer","doi":"10.1109/IRPS.2009.5173364","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173364","url":null,"abstract":"A novel test structure to study intrinsic reliability of barrier/low-k is proposed. The structure is based on a planar capacitor design where low-k film is deposited after the patterning of the capacitor, followed by metallization and Cu CMP. This so called low-k planar capacitor structure provides several unique capabilities to study various aspects of barrier/low-k TDDB compared with the conventional damascene structures. Two of the unique capabilities are presented in this paper. First, TDDB from a damage-free low-k material has been measured for the first time using the low-k planar capacitor structure. Second, the test structure is sensitive enough to quantify the impact of selected process conditions, such as barrier re-sputter and plasma treatments, on TDDB.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116131395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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