Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173392
H. Jung, T. Park, Jeong Hwan Kim, Sang Young Lee, Joohwi Lee, Himchan Oh, Kwang Duck Na, Jung-min Park, Weon-hong Kim, Min-woo Song, N. Lee, C. Hwang
HfO2, HfZrxOy and ZrO2 gate dielectrics are systematically compared in terms of the nMOS PBTI and pMOS NBTI. Compared to HfO2, ZrO2 exhibits higher capacitance and superior nMOS mobility characteristics. In addition, as the ZrO2 content increases, Vth shift under the nMOS PBTI stress is dramatically reduced. This is mainly contributed to the lower density of pre-existing bulk traps related to the oxygen vacancies.
{"title":"Systematic study on bias temperature instability of various high-k gate dielectrics ; HfO2, HfZrxOy and ZrO2","authors":"H. Jung, T. Park, Jeong Hwan Kim, Sang Young Lee, Joohwi Lee, Himchan Oh, Kwang Duck Na, Jung-min Park, Weon-hong Kim, Min-woo Song, N. Lee, C. Hwang","doi":"10.1109/IRPS.2009.5173392","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173392","url":null,"abstract":"HfO<inf>2</inf>, HfZr<inf>x</inf>O<inf>y</inf> and ZrO<inf>2</inf> gate dielectrics are systematically compared in terms of the nMOS PBTI and pMOS NBTI. Compared to HfO<inf>2</inf>, ZrO<inf>2</inf> exhibits higher capacitance and superior nMOS mobility characteristics. In addition, as the ZrO<inf>2</inf> content increases, V<inf>th</inf> shift under the nMOS PBTI stress is dramatically reduced. This is mainly contributed to the lower density of pre-existing bulk traps related to the oxygen vacancies.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133388096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173383
A. Prokofiev, J. Blomgren, S. Platt, R. Nolte, S. Rottger, A. N. Smirnov
ANITA (Atmospheric-like Neutrons from thIck TArget), a new neutron facility for accelerated testing of electronic components and systems for neutron-induced single event effects, has been installed at The Svedberg Laboratory in Uppsala, Sweden. Results of characterization measurements are reported.
{"title":"ANITA — a new neutron facility for accelerated SEE testing at the svedberg laboratory","authors":"A. Prokofiev, J. Blomgren, S. Platt, R. Nolte, S. Rottger, A. N. Smirnov","doi":"10.1109/IRPS.2009.5173383","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173383","url":null,"abstract":"ANITA (Atmospheric-like Neutrons from thIck TArget), a new neutron facility for accelerated testing of electronic components and systems for neutron-induced single event effects, has been installed at The Svedberg Laboratory in Uppsala, Sweden. Results of characterization measurements are reported.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114490844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173395
R. Vollertsen, H. Reisinger, S. Aresu, C. Schlunder
This work demonstrates that NBTI assessment by fast wafer level reliability methods is possible in a quantitative manner. This involves excluding time periods from the stress time that are used for restoration of damage recovered during stress interruption and a calibrated back extrapolation of measured recovery traces to short delay times based on the universal recovery equation. The development of the methodology, the challenges and the verification of the implemented algorithm are presented.
{"title":"Applying the universal recovery equation for fast wafer level reliability monitoring NBTI assessment","authors":"R. Vollertsen, H. Reisinger, S. Aresu, C. Schlunder","doi":"10.1109/IRPS.2009.5173395","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173395","url":null,"abstract":"This work demonstrates that NBTI assessment by fast wafer level reliability methods is possible in a quantitative manner. This involves excluding time periods from the stress time that are used for restoration of damage recovered during stress interruption and a calibrated back extrapolation of measured recovery traces to short delay times based on the universal recovery equation. The development of the methodology, the challenges and the verification of the implemented algorithm are presented.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114513176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173364
L. Zhao, Z. Tokei, Gianni Giai Gischia, M. Pantouvaki, K. Croes, G. Beyer
A novel test structure to study intrinsic reliability of barrier/low-k is proposed. The structure is based on a planar capacitor design where low-k film is deposited after the patterning of the capacitor, followed by metallization and Cu CMP. This so called low-k planar capacitor structure provides several unique capabilities to study various aspects of barrier/low-k TDDB compared with the conventional damascene structures. Two of the unique capabilities are presented in this paper. First, TDDB from a damage-free low-k material has been measured for the first time using the low-k planar capacitor structure. Second, the test structure is sensitive enough to quantify the impact of selected process conditions, such as barrier re-sputter and plasma treatments, on TDDB.
{"title":"A novel test structure to study intrinsic reliability of barrier/low-k","authors":"L. Zhao, Z. Tokei, Gianni Giai Gischia, M. Pantouvaki, K. Croes, G. Beyer","doi":"10.1109/IRPS.2009.5173364","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173364","url":null,"abstract":"A novel test structure to study intrinsic reliability of barrier/low-k is proposed. The structure is based on a planar capacitor design where low-k film is deposited after the patterning of the capacitor, followed by metallization and Cu CMP. This so called low-k planar capacitor structure provides several unique capabilities to study various aspects of barrier/low-k TDDB compared with the conventional damascene structures. Two of the unique capabilities are presented in this paper. First, TDDB from a damage-free low-k material has been measured for the first time using the low-k planar capacitor structure. Second, the test structure is sensitive enough to quantify the impact of selected process conditions, such as barrier re-sputter and plasma treatments, on TDDB.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116131395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173309
S. Pal, Huikai Xie
With their large scan range and low drive voltages, electrothermally-actuated micromirrors have great potential in optical biomedical imaging applications, but the repeatability and reliability of such micromirrors are not well understood. This paper reports the conditions for achieving repeatability of the embedded resistive heater and the mirror tilt angle of an electrothermal bimorph micromirror. The upper limit of the actuation voltage that does not degrade the embedded heater performance has been established.
{"title":"Repeatability study of an electrothermally actuated micromirror","authors":"S. Pal, Huikai Xie","doi":"10.1109/IRPS.2009.5173309","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173309","url":null,"abstract":"With their large scan range and low drive voltages, electrothermally-actuated micromirrors have great potential in optical biomedical imaging applications, but the repeatability and reliability of such micromirrors are not well understood. This paper reports the conditions for achieving repeatability of the embedded resistive heater and the mirror tilt angle of an electrothermal bimorph micromirror. The upper limit of the actuation voltage that does not degrade the embedded heater performance has been established.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115276075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173334
Y. C. Ong, D. Ang, K. Pey, S. O’Shea, K. Kakushima, T. Kawanago, H. Iwai, C. Tung
Evolution of electronic trap generation in the highdielectric constant (Hκ) layer and the interfacial layer (IL) of the Hκ gate stack and their interdependency is examined at nanoscopic resolution using scanning tunnelling microscopy (STM). We observed experimentally (i) trap generation in the dielectric layer next to the cathode is generally mismatched with pre-existing traps in the IL which exhibit stress induced leakage current (SILC) characteristics. (ii) Pre-existing SILC trap can evolve into a percolation path within the dielectric layer. (iii) pre-existing leakage path in the Hκ can accelerate trap generation in the IL due to electric field enhancement. Based on the experimental insight, a model on how BD of the Hκ gate stack is triggered by traps in the Hκ and IL layers is proposed.
{"title":"Real-time observation of trap generation by scanning tunneling microscopy and the correlation to high-κ gate stack breakdown","authors":"Y. C. Ong, D. Ang, K. Pey, S. O’Shea, K. Kakushima, T. Kawanago, H. Iwai, C. Tung","doi":"10.1109/IRPS.2009.5173334","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173334","url":null,"abstract":"Evolution of electronic trap generation in the highdielectric constant (Hκ) layer and the interfacial layer (IL) of the Hκ gate stack and their interdependency is examined at nanoscopic resolution using scanning tunnelling microscopy (STM). We observed experimentally (i) trap generation in the dielectric layer next to the cathode is generally mismatched with pre-existing traps in the IL which exhibit stress induced leakage current (SILC) characteristics. (ii) Pre-existing SILC trap can evolve into a percolation path within the dielectric layer. (iii) pre-existing leakage path in the Hκ can accelerate trap generation in the IL due to electric field enhancement. Based on the experimental insight, a model on how BD of the Hκ gate stack is triggered by traps in the Hκ and IL layers is proposed.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124806820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173278
I. Hirano, Y. Nakasaki, S. Fukatsu, Akiko Masada, Y. Mitani, M. Goto, K. Nagatomo, S. Inumiya, K. Sekine
The slope parameter of Weibull plot of Tbd, β, strongly depends on gate electrode material for metalgate/HfSiON gate stacks in n-FETs. Furthermore β of Tbd under bipolar stress is larger than that under DC stress. From these results, it is found that the balance of injected carriers is strongly related to β in terms of the origin of large β for metal-gate/high-k.
{"title":"Impact of metal gate electrode on Weibull distribution of TDDB in HfSiON gate dielectrics","authors":"I. Hirano, Y. Nakasaki, S. Fukatsu, Akiko Masada, Y. Mitani, M. Goto, K. Nagatomo, S. Inumiya, K. Sekine","doi":"10.1109/IRPS.2009.5173278","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173278","url":null,"abstract":"The slope parameter of Weibull plot of Tbd, β, strongly depends on gate electrode material for metalgate/HfSiON gate stacks in n-FETs. Furthermore β of Tbd under bipolar stress is larger than that under DC stress. From these results, it is found that the balance of injected carriers is strongly related to β in terms of the origin of large β for metal-gate/high-k.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114968994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173291
H. Enichlmair, J. M. Park, S. Carniello, B. Loeffler, R. Minixhofer, M. Levy
The hot carrier stress induced device degradation of a p-type LDMOS high voltage transistor is investigated at different stress conditions. The influence of shallow trench corner rounding and carbon ion implantation into the shallow trench region is discussed. Numerical device simulations, charge pumping measurements and electrical characterisations are used for these investigations.
{"title":"Hot carrier stress degradation modes in p-type high voltage LDMOS transistors","authors":"H. Enichlmair, J. M. Park, S. Carniello, B. Loeffler, R. Minixhofer, M. Levy","doi":"10.1109/IRPS.2009.5173291","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173291","url":null,"abstract":"The hot carrier stress induced device degradation of a p-type LDMOS high voltage transistor is investigated at different stress conditions. The influence of shallow trench corner rounding and carbon ion implantation into the shallow trench region is discussed. Numerical device simulations, charge pumping measurements and electrical characterisations are used for these investigations.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126508584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173225
T. Ohki, T. Kikkawa, Y. Inoue, M. Kanamura, N. Okamoto, K. Makiyama, K. Imanishi, H. Shigematsu, K. Joshin, N. Hara
In this paper, we describe highly reliable GaN high electron mobility transistors (HEMTs) for high-power and high-efficiency amplifiers. First, we present the reliability mechanisms and progress on the previously reported GaN HEMTs. Next, we introduce our specific device structure for GaN HEMTs for improving reliability. An n-GaN cap and optimized buffer layer are used to realize high efficiency and high reliability by suppressing current collapse and quiescent current (Idsq)-drift. Finally, we propose a new device process around the gate electrode for further improvement of reliability. Preventing gate edge silicidation leads to reduced gate leakage current and suppression of initial degradation in a DC-stress test under high-temperature and high-voltage conditions. Gate edge engineering plays a key role in reducing the gate leakage current and improving reliability.
{"title":"Reliability of GaN HEMTs: current status and future technology","authors":"T. Ohki, T. Kikkawa, Y. Inoue, M. Kanamura, N. Okamoto, K. Makiyama, K. Imanishi, H. Shigematsu, K. Joshin, N. Hara","doi":"10.1109/IRPS.2009.5173225","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173225","url":null,"abstract":"In this paper, we describe highly reliable GaN high electron mobility transistors (HEMTs) for high-power and high-efficiency amplifiers. First, we present the reliability mechanisms and progress on the previously reported GaN HEMTs. Next, we introduce our specific device structure for GaN HEMTs for improving reliability. An n-GaN cap and optimized buffer layer are used to realize high efficiency and high reliability by suppressing current collapse and quiescent current (Idsq)-drift. Finally, we propose a new device process around the gate electrode for further improvement of reliability. Preventing gate edge silicidation leads to reduced gate leakage current and suppression of initial degradation in a DC-stress test under high-temperature and high-voltage conditions. Gate edge engineering plays a key role in reducing the gate leakage current and improving reliability.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130039323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173330
E. Miranda, E. O'Connor, G. Hughes, P. Casey, K. Cherkaoui, S. Monaghan, R. Long, D. O'Connell, P. Hurley
In this work, we report on the occurrence of the soft breakdown (SBD) failure mode in 20nm-thick films of magnesium oxide (MgO) grown on Si substrates. To our knowledge, this is the first observation of this failure mechanism in a high-κ gate dielectric with such a large oxide thickness. We show that the I–V characteristics follow the power-law dependence typical of SBD conduction in a wider voltage range than that reported for SiO2. We pay special attention to the relationship between the magnitude of the current and the normalized differential conductance, and analyze the role played by the injection polarity and substrate type.
{"title":"Soft breakdown in MgO dielectric layers","authors":"E. Miranda, E. O'Connor, G. Hughes, P. Casey, K. Cherkaoui, S. Monaghan, R. Long, D. O'Connell, P. Hurley","doi":"10.1109/IRPS.2009.5173330","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173330","url":null,"abstract":"In this work, we report on the occurrence of the soft breakdown (SBD) failure mode in 20nm-thick films of magnesium oxide (MgO) grown on Si substrates. To our knowledge, this is the first observation of this failure mechanism in a high-κ gate dielectric with such a large oxide thickness. We show that the I–V characteristics follow the power-law dependence typical of SBD conduction in a wider voltage range than that reported for SiO2. We pay special attention to the relationship between the magnitude of the current and the normalized differential conductance, and analyze the role played by the injection polarity and substrate type.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131348171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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