Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173300
Shou-Chung Lee, A. Oates, Kow-Ming Chang
We investigate the impact of porosity on the reliability of low-k dielectrics. We show that electric field enhancement around pores occurs and is significantly increased by Cu interaction, suggesting a new potential mechanism for breakdown of dielectrics at stress conditions. We develop of an analytic model to predict failure distribution parameters as a function of porosity and show that the model is in good agreement with measurements for porosity in the range of 5% to 40%. We explain why the field acceleration factor γ is a constant for all silica-based material according to percolation theory. We propose that the percolation path difference between high field and low field would make the field dependence on failure time become non-linear.
{"title":"Fundamental understanding of porous low-k dielectric breakdown","authors":"Shou-Chung Lee, A. Oates, Kow-Ming Chang","doi":"10.1109/IRPS.2009.5173300","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173300","url":null,"abstract":"We investigate the impact of porosity on the reliability of low-k dielectrics. We show that electric field enhancement around pores occurs and is significantly increased by Cu interaction, suggesting a new potential mechanism for breakdown of dielectrics at stress conditions. We develop of an analytic model to predict failure distribution parameters as a function of porosity and show that the model is in good agreement with measurements for porosity in the range of 5% to 40%. We explain why the field acceleration factor γ is a constant for all silica-based material according to percolation theory. We propose that the percolation path difference between high field and low field would make the field dependence on failure time become non-linear.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116863122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173286
Y. Yeoh, S. Suk, Ming Li, K. Yeo, Dong-Won Kim, G. Jin, Kyoungsuk Oh
Hot carrier (HC) reliability of Gate-All-Around Twin Si Nanowire Field Effect Transistor (GAA TSNWFET) is reported and discussed with respect to size and shape of nanowire channel, gate length, thickness and kind of gate dielectric in detail. Smaller nanowire channel size, shorter gate length and thinner gate oxide down to 2nm thickness show worse hot carrier reliability. The worst VD for 10 years guaranty, 1.31V, satisfies requirement of ITRS roadmap.
{"title":"Investigation on hot carrier reliability of Gate-All-Around Twin Si Nanowire Field Effect Transistor","authors":"Y. Yeoh, S. Suk, Ming Li, K. Yeo, Dong-Won Kim, G. Jin, Kyoungsuk Oh","doi":"10.1109/IRPS.2009.5173286","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173286","url":null,"abstract":"Hot carrier (HC) reliability of Gate-All-Around Twin Si Nanowire Field Effect Transistor (GAA TSNWFET) is reported and discussed with respect to size and shape of nanowire channel, gate length, thickness and kind of gate dielectric in detail. Smaller nanowire channel size, shorter gate length and thinner gate oxide down to 2nm thickness show worse hot carrier reliability. The worst VD for 10 years guaranty, 1.31V, satisfies requirement of ITRS roadmap.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"os-3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128076782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173329
A. Karmarkar, Xiaopeng Xu, V. Moroz
Large thermal mismatch stress can be introduced in 3D-Integration structures employing Through-Silicon-Via (TSV). The stress distribution in silicon and interconnect is affected by the via diameter and layout geometry. The TSV induced stress changes silicon mobility and ultimately alters device performance. The mobility and performance change differs in nand p- silicon and is a function of the distance to the TSV. In addition, the TSV induced stress acts on the barrier layer, the landing pad, the interconnects, and the dielectrics. The interactions with defects may lead to crack nucleation and growth, and compromise the structure reliability. Furthermore, the material choice that reduces silicon stress for less impact on performance may increase stresses in other regions where reliability is of concern. This paper studies these effects and their dependence on various integration configurations.
{"title":"Performanace and reliability analysis of 3D-integration structures employing Through Silicon Via (TSV)","authors":"A. Karmarkar, Xiaopeng Xu, V. Moroz","doi":"10.1109/IRPS.2009.5173329","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173329","url":null,"abstract":"Large thermal mismatch stress can be introduced in 3D-Integration structures employing Through-Silicon-Via (TSV). The stress distribution in silicon and interconnect is affected by the via diameter and layout geometry. The TSV induced stress changes silicon mobility and ultimately alters device performance. The mobility and performance change differs in nand p- silicon and is a function of the distance to the TSV. In addition, the TSV induced stress acts on the barrier layer, the landing pad, the interconnects, and the dielectrics. The interactions with defects may lead to crack nucleation and growth, and compromise the structure reliability. Furthermore, the material choice that reduces silicon stress for less impact on performance may increase stresses in other regions where reliability is of concern. This paper studies these effects and their dependence on various integration configurations.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126573210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173306
S. Tyaginov, W. Gos, T. Grasser, V. Sverdlov, P. Schwaha, R. Heinzl, F. S. timpfl
We extend the McPherson model in a manner to capture the effect of the whole surrounding lattice on the siliconoxygen bond-breakage energetics. It is shown that the Mie- Grüneisen potential with the constants used in the original version of the model is not suitable under the consideration of the whole crystal. Other empirical pair-wise interatomic potentials, namely TTAM and BKS have been tested for the analysis of the bond rupture energetics. It is shown that the secondary minimum corresponding to the transition of the Si atom from the 4-fold to the 3-fold coordinated position occurs in a different direction with a rather high activation energy (~ 6 eV). The tunneling of the Si ion between the primary and the secondary minima has been treated within the WKB approximation. We demonstrate that the contribution of neighboring SiO4 tetrahedrons substantially decreases the breakage rate, making bond rupture by means of an electric field alone practically impossible. Therefore, the common action of an electric field and another contribution (bond weakening by hole capture, structural disorder and energy deposited by particles) is essential for Si-O bond-breakage.
{"title":"Description of Si-O bond breakage using pair-wise interatomic potentials under consideration of the whole crystal","authors":"S. Tyaginov, W. Gos, T. Grasser, V. Sverdlov, P. Schwaha, R. Heinzl, F. S. timpfl","doi":"10.1109/IRPS.2009.5173306","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173306","url":null,"abstract":"We extend the McPherson model in a manner to capture the effect of the whole surrounding lattice on the siliconoxygen bond-breakage energetics. It is shown that the Mie- Grüneisen potential with the constants used in the original version of the model is not suitable under the consideration of the whole crystal. Other empirical pair-wise interatomic potentials, namely TTAM and BKS have been tested for the analysis of the bond rupture energetics. It is shown that the secondary minimum corresponding to the transition of the Si atom from the 4-fold to the 3-fold coordinated position occurs in a different direction with a rather high activation energy (~ 6 eV). The tunneling of the Si ion between the primary and the secondary minima has been treated within the WKB approximation. We demonstrate that the contribution of neighboring SiO4 tetrahedrons substantially decreases the breakage rate, making bond rupture by means of an electric field alone practically impossible. Therefore, the common action of an electric field and another contribution (bond weakening by hole capture, structural disorder and energy deposited by particles) is essential for Si-O bond-breakage.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122040087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173229
Asif Khan, Seongmo Hwang, J. Lowder, V. Adivarahan, Q. Fareed
AlGaN based deep ultraviolet light emitting diodes (DUV LEDs) are key components in systems for air, water, and food purification and germicidal applications. Because of the heteroepitaxial growth of the DUV LED epilayers on sapphire, they have a large number of dislocations that invariably leads to a reduction of quantum efficiency and lifetime degradation. In this paper, we present our recent work at developing DUV LEDs with different device geometries, which includes a new micro-pixel electrode arrangement. This arrangement was used to study mechanisms responsible for their degradation. The micro-pixel device geometry with some new packaging schemes led to DUV LEDs with emission at 280 nm and lifetimes well in excess of 3000 hours. In this paper experimental details and the results of our study are presented.
{"title":"Reliability issues in AlGaN based deep ultraviolet light emitting diodes","authors":"Asif Khan, Seongmo Hwang, J. Lowder, V. Adivarahan, Q. Fareed","doi":"10.1109/IRPS.2009.5173229","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173229","url":null,"abstract":"AlGaN based deep ultraviolet light emitting diodes (DUV LEDs) are key components in systems for air, water, and food purification and germicidal applications. Because of the heteroepitaxial growth of the DUV LED epilayers on sapphire, they have a large number of dislocations that invariably leads to a reduction of quantum efficiency and lifetime degradation. In this paper, we present our recent work at developing DUV LEDs with different device geometries, which includes a new micro-pixel electrode arrangement. This arrangement was used to study mechanisms responsible for their degradation. The micro-pixel device geometry with some new packaging schemes led to DUV LEDs with emission at 280 nm and lifetimes well in excess of 3000 hours. In this paper experimental details and the results of our study are presented.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"250 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122080247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173275
L. Endrinal, E. Coyne
This paper introduces a new failure analysis procedure to distinguish Surface Electro-Static Discharge (ESD) from mechanically induced metal-to-metal shorts. The procedure utilizes two common techniques, Transmission Electron Microscopy (TEM) material analysis and Focused Ion Beam (FIB) cross sectioning. TEM analysis of the failure mechanism enables the material structure to be studied in order to distinguish the thermal from mechanical processes. Once a mechanical process has been confirmed, the formation of the failure mechanism is imaged through a new methodology for package analysis by means of backside cross-section using the Dual Beam FIB to show the molding compound interaction with the die surface for the first time.
{"title":"Surface Electro-Static Discharge or mechanical damage: Solving the mystery of metal-to-metal shorts using an innovative failure analysis approach","authors":"L. Endrinal, E. Coyne","doi":"10.1109/IRPS.2009.5173275","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173275","url":null,"abstract":"This paper introduces a new failure analysis procedure to distinguish Surface Electro-Static Discharge (ESD) from mechanically induced metal-to-metal shorts. The procedure utilizes two common techniques, Transmission Electron Microscopy (TEM) material analysis and Focused Ion Beam (FIB) cross sectioning. TEM analysis of the failure mechanism enables the material structure to be studied in order to distinguish the thermal from mechanical processes. Once a mechanical process has been confirmed, the formation of the failure mechanism is imaged through a new methodology for package analysis by means of backside cross-section using the Dual Beam FIB to show the molding compound interaction with the die surface for the first time.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131818122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173299
K. Yiang, H. Yao, A. Marathe, O. Aubel
An alternative method of analyzing time-dependent dielectric breakdown (TDDB) data for low-k dielectrics is presented. The analysis shows that time to breakdown is well correlated to the Poole-Frenkel emission equation, and therefore the √E-model is a more accurate model in describing the TDDB physics for low-k BEOL dielectrics.
{"title":"New perspectives of dielectric breakdown in low-k interconnects","authors":"K. Yiang, H. Yao, A. Marathe, O. Aubel","doi":"10.1109/IRPS.2009.5173299","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173299","url":null,"abstract":"An alternative method of analyzing time-dependent dielectric breakdown (TDDB) data for low-k dielectrics is presented. The analysis shows that time to breakdown is well correlated to the Poole-Frenkel emission equation, and therefore the √E-model is a more accurate model in describing the TDDB physics for low-k BEOL dielectrics.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131818189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173285
N. Banno, T. Sakamoto, H. Hada, N. Kasai, N. Iguchi, H. Imai, S. Fujieda, T. Ichihashi, T. Hasegawa, M. Aono
For stability against the thermal budget of the CMOS BEOL process, we developed a new solid-electrolyte switch that uses a SiO2−Ta2O5 composite as the electrolyte. This switch has high thermal stability because thermal diffusion of Cu+ ions is suppressed in the composite. Moreover, its switching characteristics after thermal annealing are similar to those of a Ta2O5 switch without annealing. The switch with the SiO2−Ta2O5 composite electrolyte has good ON-state durability against DC current stress; its durability is comparable to that of a single via in interconnects. The switch can be implemented in the local interconnection layers of LSIs.
{"title":"Cu-ion diffusivity in SiO2-Ta2O5 solid electrolyte and its impact on the yield of resistance switching after BEOL processes","authors":"N. Banno, T. Sakamoto, H. Hada, N. Kasai, N. Iguchi, H. Imai, S. Fujieda, T. Ichihashi, T. Hasegawa, M. Aono","doi":"10.1109/IRPS.2009.5173285","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173285","url":null,"abstract":"For stability against the thermal budget of the CMOS BEOL process, we developed a new solid-electrolyte switch that uses a SiO<inf>2</inf>−Ta<inf>2</inf>O<inf>5</inf> composite as the electrolyte. This switch has high thermal stability because thermal diffusion of Cu<sup>+</sup> ions is suppressed in the composite. Moreover, its switching characteristics after thermal annealing are similar to those of a Ta<inf>2</inf>O<inf>5</inf> switch without annealing. The switch with the SiO<inf>2</inf>−Ta<inf>2</inf>O<inf>5</inf> composite electrolyte has good ON-state durability against DC current stress; its durability is comparable to that of a single via in interconnects. The switch can be implemented in the local interconnection layers of LSIs.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130607267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173360
Z.-S. Choi, Byung-lyul Park, Jong Myeong Lee, G. Choi, Hyeon-deok Lee, J. Moon
Electromigration in a hybrid interconnect which consists of copper metallization in via below, aluminum metallization in via above, and tungsten via in between has been investigated. Fatal failures are found to occur in copper segments of the hybrid structures we tested. Two distinct failure mechanisms in copper segments are observed. One type of failure occurs due to void nucleation at the interface between barrier metal of tungsten via and copper. Time to failure is highly dependent on types of barrier metals applied. Critical stresses for void nucleation at the interface for 3 types of barrier metals are obtained using a simulation tool, and the average stress ranges from 61MPa to 246MPa. Second type of failure, which occurs less frequently than the first type, is by void growth and spanning through width and thickness of the line. Failures by void growth occur at a specific time range and failures are independent of barrier metal variation, which suggests that the failure is initiated by a pre-existing void or a defect. Thus, in order to effectively enhance the EM resistance in this hybrid interconnect structure, one should not only optimize the barrier metal, but also minimize pre-existing voids or defects in the line.
{"title":"Electromigration tests for critical stress and failure mechanism evaluation in Cu/W via/Al hybrid interconnect","authors":"Z.-S. Choi, Byung-lyul Park, Jong Myeong Lee, G. Choi, Hyeon-deok Lee, J. Moon","doi":"10.1109/IRPS.2009.5173360","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173360","url":null,"abstract":"Electromigration in a hybrid interconnect which consists of copper metallization in via below, aluminum metallization in via above, and tungsten via in between has been investigated. Fatal failures are found to occur in copper segments of the hybrid structures we tested. Two distinct failure mechanisms in copper segments are observed. One type of failure occurs due to void nucleation at the interface between barrier metal of tungsten via and copper. Time to failure is highly dependent on types of barrier metals applied. Critical stresses for void nucleation at the interface for 3 types of barrier metals are obtained using a simulation tool, and the average stress ranges from 61MPa to 246MPa. Second type of failure, which occurs less frequently than the first type, is by void growth and spanning through width and thickness of the line. Failures by void growth occur at a specific time range and failures are independent of barrier metal variation, which suggests that the failure is initiated by a pre-existing void or a defect. Thus, in order to effectively enhance the EM resistance in this hybrid interconnect structure, one should not only optimize the barrier metal, but also minimize pre-existing voids or defects in the line.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129546989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173313
V. Malandruccolo, M. Ciappa, H. Rothleitner, W. Fichtner
Efficient screening procedures for the control of the gate oxide defectivity are vital to limit early failures especially in critical automotive applications. Traditional strategies based on burn-in and in-line tests are able to provide the required level of reliability but they are expensive and time consuming. This paper presents a novel approach to the gate stress test of Lateral Diffused MOS transistors based on an embedded circuitry that includes logic control, high voltage generation, and leakage current monitoring. The concept, advantages and the circuit for the proposed built-in gate stress test procedure are described in very detail and illustrated by circuit simulation.
{"title":"New on-chip screening of gate oxides smart power devices for automotive applications","authors":"V. Malandruccolo, M. Ciappa, H. Rothleitner, W. Fichtner","doi":"10.1109/IRPS.2009.5173313","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173313","url":null,"abstract":"Efficient screening procedures for the control of the gate oxide defectivity are vital to limit early failures especially in critical automotive applications. Traditional strategies based on burn-in and in-line tests are able to provide the required level of reliability but they are expensive and time consuming. This paper presents a novel approach to the gate stress test of Lateral Diffused MOS transistors based on an embedded circuitry that includes logic control, high voltage generation, and leakage current monitoring. The concept, advantages and the circuit for the proposed built-in gate stress test procedure are described in very detail and illustrated by circuit simulation.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128292034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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