Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173380
J. Kim, Kyong-Taek Lee, Seung-Hyun Song, Min-Sang Park, S. Hong, G. Choi, Hyun-Sik Choi, R. Baek, H. Sagong, Y. Jeong, Sung-Woo Jung, C. Kang
We have investigated reliability characteristics for a high-k/metal gate MOSFET with strain engineering under constant voltage stress (CVS). Using contact edge stop layer (CESL), tensile and compressive strains are applied to the channel region. Since the compressive MOSFET has more hydrogen in the CESL, the MOSFET has lower reliability characteristics than others. Though the hydrogen can passivate dangling bonds in the high-k dielectric, the passivated bonds are easily broken by voltage stress, which cause degradation of high-k layer.
{"title":"Reliability of HFO2/SIO2 dielectric with strain engineering using CESL stressor","authors":"J. Kim, Kyong-Taek Lee, Seung-Hyun Song, Min-Sang Park, S. Hong, G. Choi, Hyun-Sik Choi, R. Baek, H. Sagong, Y. Jeong, Sung-Woo Jung, C. Kang","doi":"10.1109/IRPS.2009.5173380","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173380","url":null,"abstract":"We have investigated reliability characteristics for a high-k/metal gate MOSFET with strain engineering under constant voltage stress (CVS). Using contact edge stop layer (CESL), tensile and compressive strains are applied to the channel region. Since the compressive MOSFET has more hydrogen in the CESL, the MOSFET has lower reliability characteristics than others. Though the hydrogen can passivate dangling bonds in the high-k dielectric, the passivated bonds are easily broken by voltage stress, which cause degradation of high-k layer.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121148716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173346
H. Ichikawa, S. Matsukawa, K. Hamada, A. Yamaguchi, T. Nakabayashi
We clarified the mechanism of forward-biased electrostatic-discharge-induced degradation of InP-based laser diodes. This degradation was caused by melting of the active layer as a result of light absorption. We observed a reduction in tolerance on aging in uncoated laser diodes. This reduction was suppressed by facet coating.
{"title":"Analysis on forward-biased electrostatic-discharge-induced degradation of InP-based buried heterostructure laser diodes","authors":"H. Ichikawa, S. Matsukawa, K. Hamada, A. Yamaguchi, T. Nakabayashi","doi":"10.1109/IRPS.2009.5173346","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173346","url":null,"abstract":"We clarified the mechanism of forward-biased electrostatic-discharge-induced degradation of InP-based laser diodes. This degradation was caused by melting of the active layer as a result of light absorption. We observed a reduction in tolerance on aging in uncoated laser diodes. This reduction was suppressed by facet coating.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121189466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173381
R. O'Connor, M. Aoulaiche, L. Pantisano, A. Shickova, R. Degraeve, B. Kaczer, G. Groeseneken
In this work we examine the effect of nitrogen incorporation on the defect generation behavior in HfSiON gate dielectric layers. We show that nitrogen effectively passivates pre-existing defects in the HfSiO, but the effect is quickly reversed during stress leading to high levels of SILC and NBTI
{"title":"The role of nitrogen in HfSiON defect passivation","authors":"R. O'Connor, M. Aoulaiche, L. Pantisano, A. Shickova, R. Degraeve, B. Kaczer, G. Groeseneken","doi":"10.1109/IRPS.2009.5173381","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173381","url":null,"abstract":"In this work we examine the effect of nitrogen incorporation on the defect generation behavior in HfSiON gate dielectric layers. We show that nitrogen effectively passivates pre-existing defects in the HfSiO, but the effect is quickly reversed during stress leading to high levels of SILC and NBTI","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121349084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173361
O. Aubel, J. Hohage, F. Feustel, C. Hennesthal, U. Mayer, A. Preusse, M. Nopper, M. Lehr, J. Boemmels, S. Wehner
In this paper we present process options to close the gap between electromigration performance needs by design and process performance. We are going to present reliability data for metal capping and advanced copper surface cleaning processes. These processes are showing very good performance and extendibility to 32nm technology nodes and beyond.
{"title":"Process options for improving electromigration performance in 32nm technology and beyond","authors":"O. Aubel, J. Hohage, F. Feustel, C. Hennesthal, U. Mayer, A. Preusse, M. Nopper, M. Lehr, J. Boemmels, S. Wehner","doi":"10.1109/IRPS.2009.5173361","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173361","url":null,"abstract":"In this paper we present process options to close the gap between electromigration performance needs by design and process performance. We are going to present reliability data for metal capping and advanced copper surface cleaning processes. These processes are showing very good performance and extendibility to 32nm technology nodes and beyond.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123254834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173303
S. Pae, T. Ghani, M. Hattendorf, J. Hicks, J. Jopling, J. Maiz, K. Mistry, J. O'Donnell, C. Prasad, J. Wiedemer, J. Xu
Stress Induced Leakage Current (SILC) has been observed on non-optimized high-K (HK) and metal-gate (MG) transistors. Large NMOS PBTI degradation and correlation to SILC increase on such gate stack is a result of large trap generations in the bulk-HK. This poses a long term reliability concern on product standby power and can limit the operating voltage if not suppressed. On an optimized HK+MG process, we demonstrate that SILC has been suppressed. The transistor level SILC data, model and Product burn-in stress data support this. With optimized process, SILC has no impact on products made of 45nm HK+MG transistors.
{"title":"Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology","authors":"S. Pae, T. Ghani, M. Hattendorf, J. Hicks, J. Jopling, J. Maiz, K. Mistry, J. O'Donnell, C. Prasad, J. Wiedemer, J. Xu","doi":"10.1109/IRPS.2009.5173303","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173303","url":null,"abstract":"Stress Induced Leakage Current (SILC) has been observed on non-optimized high-K (HK) and metal-gate (MG) transistors. Large NMOS PBTI degradation and correlation to SILC increase on such gate stack is a result of large trap generations in the bulk-HK. This poses a long term reliability concern on product standby power and can limit the operating voltage if not suppressed. On an optimized HK+MG process, we demonstrate that SILC has been suppressed. The transistor level SILC data, model and Product burn-in stress data support this. With optimized process, SILC has no impact on products made of 45nm HK+MG transistors.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"242 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115255882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173252
Hajime Kobayashi, N. Kawamoto, J. Kase, Ken Shiraish
We performed underground real-time tests to obtain alpha particle-induced soft error rates (α-SER) with high accuracies for SRAMs with 180 nm – 90 nm technologies and studied the scaling trend of α-SERs. In order to estimate the maximum permissive rate of alpha emission from package resin, the α-SER was compared to the neutron-induced soft error rate (n-SER) obtained from accelerated tests. We found that as devices are scaled down, the α-SER increased while the n-SER slightly decreased, and that the α-SER could be greater than the n-SER in 90 nm technology even when the ultra-low-alpha (ULA) grade, with the alpha emission rate ≫ 1 × 10−3 cm−2h−1, was used for package resin. We also performed computer simulations to estimate scaling trends of both α-SER and n-SER up to 45 nm technologies, and noticed that the α-SER decreased from 65 nm technology while the n-SER increased from 45 nm technology due to direct ionization from the protons generated in the n + Si nuclear reaction.
{"title":"Alpha particle and neutron-induced soft error rates and scaling trends in SRAM","authors":"Hajime Kobayashi, N. Kawamoto, J. Kase, Ken Shiraish","doi":"10.1109/IRPS.2009.5173252","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173252","url":null,"abstract":"We performed underground real-time tests to obtain alpha particle-induced soft error rates (α-SER) with high accuracies for SRAMs with 180 nm – 90 nm technologies and studied the scaling trend of α-SERs. In order to estimate the maximum permissive rate of alpha emission from package resin, the α-SER was compared to the neutron-induced soft error rate (n-SER) obtained from accelerated tests. We found that as devices are scaled down, the α-SER increased while the n-SER slightly decreased, and that the α-SER could be greater than the n-SER in 90 nm technology even when the ultra-low-alpha (ULA) grade, with the alpha emission rate ≫ 1 × 10<sup>−3</sup> cm<sup>−2</sup>h<sup>−1</sup>, was used for package resin. We also performed computer simulations to estimate scaling trends of both α-SER and n-SER up to 45 nm technologies, and noticed that the α-SER decreased from 65 nm technology while the n-SER increased from 45 nm technology due to direct ionization from the protons generated in the n + Si nuclear reaction.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115289723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173230
C. Moe, M. Reed, G. Garrett, G. Metcalfe, T. Alexander, H. Shen, M. Wraback, A. Lunev, Y. Bilenko, Xuhong Hu, A. Sattu, Jianyu Deng, M. Shatalov, R. Gaska
Lifetime measurements on single, packaged UV LEDs were performed under constant current injection at 20 and 75 mA (60 and 226 A/cm2). The junction temperature at operation was found by micro-Raman spectroscopy to be 57 and 184 °C, respectively. Unbiased LEDs of similar characteristics placed in an oven baked at the equivalent operating junction temperatures showed a degradation in output power similar to that in the current injection devices during the initial 24 hours, but did not continue to degrade beyond that time. These studies imply that device heating, is correlated with the initial drop in output power during burn-in, but is not directly linked to the total degradation over the lifetime of the device. Time-resolved PL studies on the device active region as well as further electro-optic measurements indicate that the degradation is not due primarily to that of the active region, but may be associated with generation of point defects such as N-vacancies near the p-n junction.
{"title":"Degradation mechanisms beyond device self-heating in deep ultraviolet light emitting diodes","authors":"C. Moe, M. Reed, G. Garrett, G. Metcalfe, T. Alexander, H. Shen, M. Wraback, A. Lunev, Y. Bilenko, Xuhong Hu, A. Sattu, Jianyu Deng, M. Shatalov, R. Gaska","doi":"10.1109/IRPS.2009.5173230","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173230","url":null,"abstract":"Lifetime measurements on single, packaged UV LEDs were performed under constant current injection at 20 and 75 mA (60 and 226 A/cm2). The junction temperature at operation was found by micro-Raman spectroscopy to be 57 and 184 °C, respectively. Unbiased LEDs of similar characteristics placed in an oven baked at the equivalent operating junction temperatures showed a degradation in output power similar to that in the current injection devices during the initial 24 hours, but did not continue to degrade beyond that time. These studies imply that device heating, is correlated with the initial drop in output power during burn-in, but is not directly linked to the total degradation over the lifetime of the device. Time-resolved PL studies on the device active region as well as further electro-optic measurements indicate that the degradation is not due primarily to that of the active region, but may be associated with generation of point defects such as N-vacancies near the p-n junction.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130797405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173377
Wook H. Lee, Chang-Hyun Hur, Hyun-Min Lee, H. Yoo, Sang-eun Lee, B. Lee, Chan-Kwang Park, Kijoon H. P. Kim
Post-cycling data retention characteristics of a multilevel NOR flash memory with nitrided tunnel-oxide is presented. Results show that retention behavior is strongly related to the amount of interface trap generation rather than that of oxide trap, indicating detrapping from near interface trap is a major factor for threshold voltage shift. Process conditions including nitrogen concentration at the interface and subsequent annealing of nitrided tunnel-oxide by O2 are found to be related to the generation of interface trap and resultant postcycling retention.
{"title":"Post-cycling data retention failure in multilevel nor flash memory with nitrided tunnel-oxide","authors":"Wook H. Lee, Chang-Hyun Hur, Hyun-Min Lee, H. Yoo, Sang-eun Lee, B. Lee, Chan-Kwang Park, Kijoon H. P. Kim","doi":"10.1109/IRPS.2009.5173377","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173377","url":null,"abstract":"Post-cycling data retention characteristics of a multilevel NOR flash memory with nitrided tunnel-oxide is presented. Results show that retention behavior is strongly related to the amount of interface trap generation rather than that of oxide trap, indicating detrapping from near interface trap is a major factor for threshold voltage shift. Process conditions including nitrogen concentration at the interface and subsequent annealing of nitrided tunnel-oxide by O2 are found to be related to the generation of interface trap and resultant postcycling retention.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125356096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173254
D. Sunderland
Increasing satellite performance within size, weight and power constraints demands access to advanced semiconductors, yet environmental, reliability and schedule requirements remain. Successful technology insertion requires knowledge of failure mechanisms, design limitations and screening flow. We review Boeing's approach, critical issues and potential pitfalls, illustrated by experience with IBM ASICs.
{"title":"Qualification issues and pitfalls for advanced semiconductor devices in space","authors":"D. Sunderland","doi":"10.1109/IRPS.2009.5173254","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173254","url":null,"abstract":"Increasing satellite performance within size, weight and power constraints demands access to advanced semiconductors, yet environmental, reliability and schedule requirements remain. Successful technology insertion requires knowledge of failure mechanisms, design limitations and screening flow. We review Boeing's approach, critical issues and potential pitfalls, illustrated by experience with IBM ASICs.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123390015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-26DOI: 10.1109/IRPS.2009.5173289
P. Moens, J. Roig, B. Desoete, F. Bauwens, M. Tack
This paper reports for the first time on anomalous hot carrier effects observed in vertically integrated trench-based (TB-MOS) power transistors. The avalanche current reaches a maximum at intermediate drain voltage, and decreases for increasing drain voltage. The hot carrier lifetime of the transistors yields a minimum at intermediate drain voltage, and not at the maximum drain voltage. Charge pumping experiments enable to locate the degradation in the TB-MOS. A degradation model is proposed.
{"title":"Hot carrier effects in trench-based integrated power transistors","authors":"P. Moens, J. Roig, B. Desoete, F. Bauwens, M. Tack","doi":"10.1109/IRPS.2009.5173289","DOIUrl":"https://doi.org/10.1109/IRPS.2009.5173289","url":null,"abstract":"This paper reports for the first time on anomalous hot carrier effects observed in vertically integrated trench-based (TB-MOS) power transistors. The avalanche current reaches a maximum at intermediate drain voltage, and decreases for increasing drain voltage. The hot carrier lifetime of the transistors yields a minimum at intermediate drain voltage, and not at the maximum drain voltage. Charge pumping experiments enable to locate the degradation in the TB-MOS. A degradation model is proposed.","PeriodicalId":345860,"journal":{"name":"2009 IEEE International Reliability Physics Symposium","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123394576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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