We present the analysis and design of a 60 GHz LC QVCO in a 90 nm RF CMOS process based on the disconnected-source parallel coupled QVCO topology. We introduce a first order linear model of an LC QVCO at millimeter wave frequencies and derive the oscillator steady-state parameters. Varactor size optimization for maximum quality factor at millimeter wave frequencies is thoroughly analyzed. To overcome the classical tradeoff between the varactor quality factor and tuning range, we suggest an alternative wide-band linear frequency tuning technique based on the fundamental operation of LC QVCOs. By changing the bias of the coupling transistors (GMc-tuning), a wide frequency tuning range of 5 GHz (57.5 GHz rarr 62.5 GHz) can be achieved with very linear characteristics. The GMc-tuning technique exhibits 4 dBc/Hz lower phase noise than a varactor solution. The circuit draws a maximum of 17.6 mA (excluding buffer circuits) from a 1 V supply.
{"title":"Design of CMOS Millimeter-Wave Cross-Coupled LC Quadrature VCOs with Varactorless Frequency Tuning","authors":"I.R. Chamas, S. Raman","doi":"10.1109/SMIC.2008.16","DOIUrl":"https://doi.org/10.1109/SMIC.2008.16","url":null,"abstract":"We present the analysis and design of a 60 GHz LC QVCO in a 90 nm RF CMOS process based on the disconnected-source parallel coupled QVCO topology. We introduce a first order linear model of an LC QVCO at millimeter wave frequencies and derive the oscillator steady-state parameters. Varactor size optimization for maximum quality factor at millimeter wave frequencies is thoroughly analyzed. To overcome the classical tradeoff between the varactor quality factor and tuning range, we suggest an alternative wide-band linear frequency tuning technique based on the fundamental operation of LC QVCOs. By changing the bias of the coupling transistors (GMc-tuning), a wide frequency tuning range of 5 GHz (57.5 GHz rarr 62.5 GHz) can be achieved with very linear characteristics. The GMc-tuning technique exhibits 4 dBc/Hz lower phase noise than a varactor solution. The circuit draws a maximum of 17.6 mA (excluding buffer circuits) from a 1 V supply.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132546172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. The anticipated presentation will cover the current status and future trends of millimeter-wave MMICs, including those using III-V compound (GaAs, InP, GaN, etc.) and Si-based (CMOS, SiGe HBT and BiCMOS) MMIC technologies. Millimeter-wave MMICs used to be applied to military and astronomy systems for long time and started to be utilized for civil applications in the decade, such as communications and automotive radars. The evolution of IC technologies has enabled the performance of Si-based MMICs over 100 GHz, even in standard bulk CMOS processes. This is believed to have a major impact in the future development of millimeter-wave systems. Since low-cost mass-production potential pushes forward the technology, a very high integration of circuit functions on a chip, such as RF, base-band circuitry, automatic-control for a steady operation, and maybe even the antenna, etc. should be included, and thus the system on chip (SOC) issues should be addressed, especially in MMW regime. Moreover, millimeter-wave packaging cost always dominated in the module development In order to simplify the assembly and reduced cost, the concept of system in package (SIP) has been proposed. This presentation will also survey the current technologies for SOC and SIP and discuss related issues and challenges.
{"title":"Current Status and Future Trends for Si and Compound MMICs in Millimeter-Wave Regime and Related Issues for System on Chip (SOC) and/or System in Package (SIP) Applications","authors":"Huei Wang","doi":"10.1109/SMIC.2008.12","DOIUrl":"https://doi.org/10.1109/SMIC.2008.12","url":null,"abstract":"Summary form only given. The anticipated presentation will cover the current status and future trends of millimeter-wave MMICs, including those using III-V compound (GaAs, InP, GaN, etc.) and Si-based (CMOS, SiGe HBT and BiCMOS) MMIC technologies. Millimeter-wave MMICs used to be applied to military and astronomy systems for long time and started to be utilized for civil applications in the decade, such as communications and automotive radars. The evolution of IC technologies has enabled the performance of Si-based MMICs over 100 GHz, even in standard bulk CMOS processes. This is believed to have a major impact in the future development of millimeter-wave systems. Since low-cost mass-production potential pushes forward the technology, a very high integration of circuit functions on a chip, such as RF, base-band circuitry, automatic-control for a steady operation, and maybe even the antenna, etc. should be included, and thus the system on chip (SOC) issues should be addressed, especially in MMW regime. Moreover, millimeter-wave packaging cost always dominated in the module development In order to simplify the assembly and reduced cost, the concept of system in package (SIP) has been proposed. This presentation will also survey the current technologies for SOC and SIP and discuss related issues and challenges.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114760528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Coudron, F. Casset, C. Durand, P. Renaux, E. Oilier, D. Bloch, P. Vairac
The small sizes of the MEMS or NEMS electromechanical resonators and their single wafer, multi frequencies possibilities has focused tremendous interest in the development of demonstrators using standard CMOS process. But sizes reduction induces output signal detection challenge. This paper deals with the dynamic characterization of NEMS. Heterodyne interferometric measurements are performed on beam and plate resonators obtained using the silicon-on-nothing (SoN) process. We obtained respectively 6.6 and 10.5 MHz resonant frequency for these devices, in correlation with ANSYS simulation predictions. Dynamic optical characterization seems to be a promising method to study nanoelectromechanical devices in the aim to enhance their performances.
{"title":"Dynamic Optical Characterization of NEMS Resonators","authors":"L. Coudron, F. Casset, C. Durand, P. Renaux, E. Oilier, D. Bloch, P. Vairac","doi":"10.1109/SMIC.2008.33","DOIUrl":"https://doi.org/10.1109/SMIC.2008.33","url":null,"abstract":"The small sizes of the MEMS or NEMS electromechanical resonators and their single wafer, multi frequencies possibilities has focused tremendous interest in the development of demonstrators using standard CMOS process. But sizes reduction induces output signal detection challenge. This paper deals with the dynamic characterization of NEMS. Heterodyne interferometric measurements are performed on beam and plate resonators obtained using the silicon-on-nothing (SoN) process. We obtained respectively 6.6 and 10.5 MHz resonant frequency for these devices, in correlation with ANSYS simulation predictions. Dynamic optical characterization seems to be a promising method to study nanoelectromechanical devices in the aim to enhance their performances.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"428 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122824932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Perumana, J. Zhan, S. S. Taylor, B. Carlton, J. Laskar
A 9.2 mW resistive feedback CMOS low-noise amplifier with a 3-dB bandwidth of 3.94 GHz (4.04 -7.98 GHz) is presented. At 5.5 GHz, the fully integrated LNA achieves a measured gain above 24 dB, a noise figure of 2 dB, and an output IP3 of 21.5 dBm. The LNA draws 7.7 mA from the 1.2 V supply and utilizes a single compact low-Q on-chip inductor. The LNA is implemented in a 90-nm CMOS process and occupies a die area of only 0.022 mm2.
{"title":"A 9.2 mW, 4-8 GHz Resistive Feedback CMOS LNA with 24.4 dB Gain, 2 dB Noise Figure, and 21.5 dBm Output IP3","authors":"B. Perumana, J. Zhan, S. S. Taylor, B. Carlton, J. Laskar","doi":"10.1109/SMIC.2008.15","DOIUrl":"https://doi.org/10.1109/SMIC.2008.15","url":null,"abstract":"A 9.2 mW resistive feedback CMOS low-noise amplifier with a 3-dB bandwidth of 3.94 GHz (4.04 -7.98 GHz) is presented. At 5.5 GHz, the fully integrated LNA achieves a measured gain above 24 dB, a noise figure of 2 dB, and an output IP3 of 21.5 dBm. The LNA draws 7.7 mA from the 1.2 V supply and utilizes a single compact low-Q on-chip inductor. The LNA is implemented in a 90-nm CMOS process and occupies a die area of only 0.022 mm2.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125635152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a dual channel satellite TV receiver using an alternative partition into a front-end RF-todigital tuner that includes the baseband ADC converters and a digital-only demodulator-on-host, resulting in a low cost and a good isolation between the analog front-end and the digital backend. The die area was significantly reduced by replacing the multi-oscillator solution used at present with a single high frequency Colpitts oscillator, followed by a ratiometric frequency divider that generates the local oscillator signals for the entire satellite TV L-band. VCO pulling was reduced by having a larger frequency offset between the two PLLs, while the ADC spurs were avoided by performing a dynamic clock frequency management. The DC offset cancellation loop capacitors were integrated onchip by combining a multiple loop architecture with Miller capacitance multiplication. Tuner specifications include: -85dBm sensitivity, <7dB noise figure, +26dBm IIP3 at minimum gain,<0.7° total integrated phase noise, 24mm2 die area and 2W power from a 3.3V supply in dual channel reception mode.
{"title":"Notice of Violation of IEEE Publication PrinciplesA Dual Channel DVB-S/S2 Direct-Conversion Satellite TV Tuner with On-Chip ADCs and Multiple DC Offset Cancellation Loops","authors":"A. Maxim, C. Turinici, M. Gheorge","doi":"10.1109/SMIC.2008.8","DOIUrl":"https://doi.org/10.1109/SMIC.2008.8","url":null,"abstract":"This paper proposes a dual channel satellite TV receiver using an alternative partition into a front-end RF-todigital tuner that includes the baseband ADC converters and a digital-only demodulator-on-host, resulting in a low cost and a good isolation between the analog front-end and the digital backend. The die area was significantly reduced by replacing the multi-oscillator solution used at present with a single high frequency Colpitts oscillator, followed by a ratiometric frequency divider that generates the local oscillator signals for the entire satellite TV L-band. VCO pulling was reduced by having a larger frequency offset between the two PLLs, while the ADC spurs were avoided by performing a dynamic clock frequency management. The DC offset cancellation loop capacitors were integrated onchip by combining a multiple loop architecture with Miller capacitance multiplication. Tuner specifications include: -85dBm sensitivity, <7dB noise figure, +26dBm IIP3 at minimum gain,<0.7° total integrated phase noise, 24mm2 die area and 2W power from a 3.3V supply in dual channel reception mode.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127757893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the impact of important geometrical parameters such as source and drain thickness, fin spacing, spacer width, etc. on the parasitic fringing capacitance component of multiple-gate field-effect transistors (MuGFET) is deeply analyzed using finite element simulations. Several architectures such as single gate, FinFETs (double gate), triple-gate represented by Pi-gate MOSFETs are simulated and compared in terms of channel and fringing capacitances for the same occupied die area. Simulations highlight the great impact of diminishing the spacing between fins for MuGFETs and the trade-off between the reduction of parasitic source and drain resistances and the increase of fringing capacitances when selective epitaxial growth (SEG) technology is introduced. The impact of these technological solutions on the transistor cut-off frequencies is also discussed.
{"title":"Finite Element Simulations of Parasitic Capacitances Related to Multiple-Gate Field-Effect Transistors Architectures","authors":"O. Moldovan, D. Lederer, B. Iñíguez, J. Raskin","doi":"10.1109/SMIC.2008.52","DOIUrl":"https://doi.org/10.1109/SMIC.2008.52","url":null,"abstract":"In this paper, the impact of important geometrical parameters such as source and drain thickness, fin spacing, spacer width, etc. on the parasitic fringing capacitance component of multiple-gate field-effect transistors (MuGFET) is deeply analyzed using finite element simulations. Several architectures such as single gate, FinFETs (double gate), triple-gate represented by Pi-gate MOSFETs are simulated and compared in terms of channel and fringing capacitances for the same occupied die area. Simulations highlight the great impact of diminishing the spacing between fins for MuGFETs and the trade-off between the reduction of parasitic source and drain resistances and the increase of fringing capacitances when selective epitaxial growth (SEG) technology is introduced. The impact of these technological solutions on the transistor cut-off frequencies is also discussed.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127420522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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