A novel microstrip dual-band bandpass filter (BPF) is proposed in this paper. The designed BPF consists of an open-loop resonator on the top layer and defected ground structure (DGS) with a pair of U-shape stepped impedance resonator (SIR) on the bottom layer. The first passband at 2.4 GHz is determined by the SIR-DGS, and the second passband at 5.2 GHz is performed by the open-loop geometry structure. The measured results of the insertion losses are -1.83 dB and -2.4 dB at 2.4 GHz and 5.2 GHz, respectively. The return losses are -38.5 dB at 2.4 GHz and -20.8 dB at 5.2 GHz. The substrate material for fabrication is FR4 with permittivity of 4.4 and the thickness of 1 mm. The total area is 36.9 mm x 11.2 mm.
{"title":"A Miniaturized Dual-Band Bandpass Filter Using Open-Loop and SIR-DGS Resonators","authors":"Pai‐Yi Hsiao, R. Weng, Yin-Hsin Chang","doi":"10.1109/SMIC.2008.54","DOIUrl":"https://doi.org/10.1109/SMIC.2008.54","url":null,"abstract":"A novel microstrip dual-band bandpass filter (BPF) is proposed in this paper. The designed BPF consists of an open-loop resonator on the top layer and defected ground structure (DGS) with a pair of U-shape stepped impedance resonator (SIR) on the bottom layer. The first passband at 2.4 GHz is determined by the SIR-DGS, and the second passband at 5.2 GHz is performed by the open-loop geometry structure. The measured results of the insertion losses are -1.83 dB and -2.4 dB at 2.4 GHz and 5.2 GHz, respectively. The return losses are -38.5 dB at 2.4 GHz and -20.8 dB at 5.2 GHz. The substrate material for fabrication is FR4 with permittivity of 4.4 and the thickness of 1 mm. The total area is 36.9 mm x 11.2 mm.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116148702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The first complementary thin-film transistor (TFTs) and complementary inverter employing single-crystal Si (100) nanomembranes are demonstrated on a low-temperature flexible plastic substrate. Combined high-temperate and low-temperature processes are employed to enable the integration of both n-and p-channel TFTs (N-TFT and P-TFT) on the same piece of single-crystal Si nanomembrane and to enable the compatibility of the device fabrication with the low-temperature plastic substrate. Under a bias voltage (VDD) of 5 V, the inverters exhibit a gain of 5.88 and switching threshold voltage VM of 2.5 V. The high and low noise margins of the inverter are 2.05 V and 2 V, respectively. These demonstrations may eventually lead to low-power digital switching applications using transferable Si nanomembrane on flexible substrates.
{"title":"Complementary TFTs and Inverters on Flexible Plastic Substrates Using Si(100) Nanomembranes","authors":"H. Pang, Hao-Chih Yuan, Z. Ma, G. Celler","doi":"10.1109/SMIC.2008.38","DOIUrl":"https://doi.org/10.1109/SMIC.2008.38","url":null,"abstract":"The first complementary thin-film transistor (TFTs) and complementary inverter employing single-crystal Si (100) nanomembranes are demonstrated on a low-temperature flexible plastic substrate. Combined high-temperate and low-temperature processes are employed to enable the integration of both n-and p-channel TFTs (N-TFT and P-TFT) on the same piece of single-crystal Si nanomembrane and to enable the compatibility of the device fabrication with the low-temperature plastic substrate. Under a bias voltage (VDD) of 5 V, the inverters exhibit a gain of 5.88 and switching threshold voltage VM of 2.5 V. The high and low noise margins of the inverter are 2.05 V and 2 V, respectively. These demonstrations may eventually lead to low-power digital switching applications using transferable Si nanomembrane on flexible substrates.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124690067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High speed SiGe-HBTs provide only a small VCE voltage variation between the saturation region (low VCE) and the breakdown at also rather low values. For high speed circuits it is unavailable to drive the SiGe HBT near the breakdown limits. In compact models used for circuit design the breakdown is described by the week avalanche approximation which is unsufficient for modern HBTs with short collector regions. We propose a more refined approximation which is based on the deed space concept for electrons to be accelerated up to the impact ionization energy. The model is implemented in the VBIC compact model.
{"title":"Improved Compact Model for High Speed SiGe HBT Breakdown","authors":"H. Xu, E. Kasper","doi":"10.1109/SMIC.2008.57","DOIUrl":"https://doi.org/10.1109/SMIC.2008.57","url":null,"abstract":"High speed SiGe-HBTs provide only a small VCE voltage variation between the saturation region (low VCE) and the breakdown at also rather low values. For high speed circuits it is unavailable to drive the SiGe HBT near the breakdown limits. In compact models used for circuit design the breakdown is described by the week avalanche approximation which is unsufficient for modern HBTs with short collector regions. We propose a more refined approximation which is based on the deed space concept for electrons to be accelerated up to the impact ionization energy. The model is implemented in the VBIC compact model.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130447849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Silicon MOS devices are seeing increased use in highly integrated RFICs. This paper shows the results of an investigation of the impact of the external gate bias resistance as well as the distributed RC gate effect on switching speed in these devices. A model is presented with both simulations and measured data used to verify the model. The model also shows that the optimal number of gate fingers in the 10 to 20 range.
{"title":"Transient Switching Behavior in Silicon MOSFET RF Switches","authors":"R. Caverly, J.J. Manosca","doi":"10.1109/SMIC.2008.51","DOIUrl":"https://doi.org/10.1109/SMIC.2008.51","url":null,"abstract":"Silicon MOS devices are seeing increased use in highly integrated RFICs. This paper shows the results of an investigation of the impact of the external gate bias resistance as well as the distributed RC gate effect on switching speed in these devices. A model is presented with both simulations and measured data used to verify the model. The model also shows that the optimal number of gate fingers in the 10 to 20 range.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121305402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Kerr, J. Gering, T. Mckay, M. Carroll, C. Roda Neve, J. Raskin
Harmonic distortion (HD) is measured arising from coplanar waveguide structures on various substrates at 900 MHz, and significant distortion for silicon substrates is demonstrated for the first time. For an input power of +35 dBm, 2nd harmonic power of -47 dBm and 3rd of -57 dBm are measured for a thru calibration structure on oxidized high-resistivity silicon (HRS) substrates, and 2nd harmonic of -23 and 3rd of -20 dBm for a longer line on a thinner oxide. These levels are high compared to a full cellular transmit switch product specification of -45 and -40 dBm for 2nd and 3rd harmonics, respectively, at similar power levels. The contribution of the silicon substrate to high harmonic levels is investigated experimentally, and an efficient technological solution based on the introduction of a trap-rich layer is demonstrated.
{"title":"Identification of RF Harmonic Distortion on Si Substrates and its Reduction Using a Trap-Rich Layer","authors":"D. Kerr, J. Gering, T. Mckay, M. Carroll, C. Roda Neve, J. Raskin","doi":"10.1109/SMIC.2008.44","DOIUrl":"https://doi.org/10.1109/SMIC.2008.44","url":null,"abstract":"Harmonic distortion (HD) is measured arising from coplanar waveguide structures on various substrates at 900 MHz, and significant distortion for silicon substrates is demonstrated for the first time. For an input power of +35 dBm, 2nd harmonic power of -47 dBm and 3rd of -57 dBm are measured for a thru calibration structure on oxidized high-resistivity silicon (HRS) substrates, and 2nd harmonic of -23 and 3rd of -20 dBm for a longer line on a thinner oxide. These levels are high compared to a full cellular transmit switch product specification of -45 and -40 dBm for 2nd and 3rd harmonics, respectively, at similar power levels. The contribution of the silicon substrate to high harmonic levels is investigated experimentally, and an efficient technological solution based on the introduction of a trap-rich layer is demonstrated.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"31 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132625250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In device simulation, fT is typically extracted at a single low frequency, e.g. 1 MHz, using gm/2piC. This is generally believed to give the same fT as traditional -20 dB/decade slope extrapolation of |h21| at high frequencies. A large discrepancy between the two fT extraction methods is observed, and the degree of discrepancy is found to depend on BGN and temperature. We explain the discrepancy as a consequence of output NQS effect and develop a new fT equation including output NQS effect. The BGN model dependence can then be understood through ac current gain betaac. New methods of simulating fT are developed, which maintain the simplicity of gm/2piC extraction while giving the same results as -20 dB/decade extrapolation.
{"title":"Impact of Output Non-Quasi-Static Effect on Consistency Between Two Cutoff Frequency Extraction Methods in Bipolar Transistor Simulation","authors":"Lan Luo, G. Niu","doi":"10.1109/SMIC.2008.37","DOIUrl":"https://doi.org/10.1109/SMIC.2008.37","url":null,"abstract":"In device simulation, f<sub>T</sub> is typically extracted at a single low frequency, e.g. 1 MHz, using g<sub>m</sub>/2piC. This is generally believed to give the same f<sub>T</sub> as traditional -20 dB/decade slope extrapolation of |h<sub>21</sub>| at high frequencies. A large discrepancy between the two f<sub>T</sub> extraction methods is observed, and the degree of discrepancy is found to depend on BGN and temperature. We explain the discrepancy as a consequence of output NQS effect and develop a new f<sub>T</sub> equation including output NQS effect. The BGN model dependence can then be understood through ac current gain beta<sub>ac</sub>. New methods of simulating f<sub>T</sub> are developed, which maintain the simplicity of g<sub>m</sub>/2piC extraction while giving the same results as -20 dB/decade extrapolation.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126628509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present here experimental measurement and modeling of drain current thermal noise in a 90 nm CMOS technology, with a focus on its current dependence. For the first time we show experimental evidence that drain current noise in weak inversion is indeed shot-like (2ql). In saturation, drain current noise is mainly determined by the drain current, and only weakly dependent on the drain voltage. A simple model of noise is derived and compared with data. The model enables noise estimation from only DC I-V curves, and yields excellent agreement with measurement for PMOS, and acceptable agreement for NMOS.
{"title":"Measurement and Modeling of Drain Current Thermal Noise to Shot Noise Ratio in 90nm CMOS","authors":"Yan Cui, G. Niu, A. Rezvani, S. S. Taylor","doi":"10.1109/SMIC.2008.36","DOIUrl":"https://doi.org/10.1109/SMIC.2008.36","url":null,"abstract":"We present here experimental measurement and modeling of drain current thermal noise in a 90 nm CMOS technology, with a focus on its current dependence. For the first time we show experimental evidence that drain current noise in weak inversion is indeed shot-like (2ql). In saturation, drain current noise is mainly determined by the drain current, and only weakly dependent on the drain voltage. A simple model of noise is derived and compared with data. The model enables noise estimation from only DC I-V curves, and yields excellent agreement with measurement for PMOS, and acceptable agreement for NMOS.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121599856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Geynet, P. Chevalier, S. Chouteau, G. Avenier, T. Schwartzmann, D. Gloria, G. Dambrine, F. Danneville, A. Chantre
This paper describes the integration of high-voltage HBTs in a high-speed SiGe BiCMOS technology. HBTs with BVCEO from 2 V to 5 V featuring an all-implanted collector and fully compatible with a 230-GHz fT BiCMOS technology have been fabricated using only one additional mask.
本文介绍了高压HBTs在高速SiGe BiCMOS技术中的集成。BVCEO范围从2v到5v的hbt具有全植入集电极，完全兼容230 ghz fT BiCMOS技术，仅使用一个额外的掩模就可以制造出来。
{"title":"High-Voltage HBTs Compatible with High-Speed SiGe BiCMOS Technology","authors":"B. Geynet, P. Chevalier, S. Chouteau, G. Avenier, T. Schwartzmann, D. Gloria, G. Dambrine, F. Danneville, A. Chantre","doi":"10.1109/SMIC.2008.59","DOIUrl":"https://doi.org/10.1109/SMIC.2008.59","url":null,"abstract":"This paper describes the integration of high-voltage HBTs in a high-speed SiGe BiCMOS technology. HBTs with BVCEO from 2 V to 5 V featuring an all-implanted collector and fully compatible with a 230-GHz fT BiCMOS technology have been fabricated using only one additional mask.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115369663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A distributed waveform generator (DWG) with DAC-assisted pulse generators is presented for the ultrafast waveform generation. It time-interleaves multiple pulse generators, and uses an on-chip transmission line for wideband pulse combining. Each unit pulse generator adopts a new current-steering topology which incorporates the edge combiner into the conventional current-steering structure for high-speed pulse generation. The transversal structure of the DWG enables a fully reconfigurable waveform generation. A 64-tap, 10.9 GS/S prototype was implemented in 0.18 mum standard digital CMOS technology. The average rise time of basis pulses generated from all 64 taps is 70 ps. The average tap delay is 91.8 ps. Characterization results and some example waveforms are shown in detail.
{"title":"A 10.9GS/s, 64 Taps Distributed Waveform Generator with DAC-Assisted Current-Steering Pulse Generators in 0.18μm Digital CMOS","authors":"Yunliang Zhu, J. Zuegel, J. Marciante, Hui Wu","doi":"10.1109/SMIC.2008.10","DOIUrl":"https://doi.org/10.1109/SMIC.2008.10","url":null,"abstract":"A distributed waveform generator (DWG) with DAC-assisted pulse generators is presented for the ultrafast waveform generation. It time-interleaves multiple pulse generators, and uses an on-chip transmission line for wideband pulse combining. Each unit pulse generator adopts a new current-steering topology which incorporates the edge combiner into the conventional current-steering structure for high-speed pulse generation. The transversal structure of the DWG enables a fully reconfigurable waveform generation. A 64-tap, 10.9 GS/S prototype was implemented in 0.18 mum standard digital CMOS technology. The average rise time of basis pulses generated from all 64 taps is 70 ps. The average tap delay is 91.8 ps. Characterization results and some example waveforms are shown in detail.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129833667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We review three examples (two PLLs [Crowley, 1979; Woo et al.] and one on-chip transmission-line resonator [Andress and Ham, 2005] ) of design tradeoffs which can in fact be circumvented; the key in each case is that the parameters that seem to trade off with each other are actually separated in time or space. This paper is an attempt to present these designs in such a way that this common approach can hopefully be applied to other circuits.
{"title":"Surpassing Tradeoffs by Separation: Examples in Frequency Generation Circuits","authors":"W. Andress, K. Woo, D. Ham","doi":"10.1109/SMIC.2008.39","DOIUrl":"https://doi.org/10.1109/SMIC.2008.39","url":null,"abstract":"We review three examples (two PLLs [Crowley, 1979; Woo et al.] and one on-chip transmission-line resonator [Andress and Ham, 2005] ) of design tradeoffs which can in fact be circumvented; the key in each case is that the parameters that seem to trade off with each other are actually separated in time or space. This paper is an attempt to present these designs in such a way that this common approach can hopefully be applied to other circuits.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127768810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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