Monolithic integrated IMPATT diodes are combined with coplanar waveguide resonator on unthinned silicon wafers to form simple oscillators for mm-wave operation (around 90 GHz). This paper describes properties of planar IMPATTs, their integration into SIMMWICs and proves their basics functionality as mW power sources for simple cost effective and flexible mm-wave systems.
{"title":"Monolithic Integrated Coplanar W-Band Impatt Oscillator","authors":"E. Kasper, H. Xu, E. Dorner, J. Werner","doi":"10.1109/SMIC.2008.62","DOIUrl":"https://doi.org/10.1109/SMIC.2008.62","url":null,"abstract":"Monolithic integrated IMPATT diodes are combined with coplanar waveguide resonator on unthinned silicon wafers to form simple oscillators for mm-wave operation (around 90 GHz). This paper describes properties of planar IMPATTs, their integration into SIMMWICs and proves their basics functionality as mW power sources for simple cost effective and flexible mm-wave systems.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127194062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. van der Heijden, H. Veenstra, D. Hartskeerl, M. Notten, D. van Goor
This paper discusses the design, simulation and measurement results of a single-ended to differential Low Noise Amplifier (LNA) for 24 GHz short range car radar applications in a production 0.25 mum SiGe:C-BiCMOS technology [1]. The input and two single-ended outputs are designed for 50 Omega impedance. The LNA achieves a measured 13.2 dB gain and 4.2dB noise figure at 24 GHz. Simulations and measurements are in close agreement. The achieved gain and noise figure are as good as for an earlier reported fully single-ended LNA [2]. No balun is required. The 0.55 x 0.60 mm IC dissipates 40 mW from a 3.3 V supply.
本文讨论了一种用于24 GHz短距离车载雷达的单端差分低噪声放大器(LNA)的设计、仿真和测量结果，该放大器应用于生产0.25 μ m SiGe:C-BiCMOS技术[1]。输入和两个单端输出设计为50 ω阻抗。LNA在24 GHz时可获得13.2 dB增益和4.2dB噪声系数。模拟和测量结果非常吻合。获得的增益和噪声系数与先前报道的全单端LNA一样好[2]。不需要平衡。0.55 x 0.60 mm IC从3.3 V电源消耗40 mW。
{"title":"Low Noise Amplifier with Integrated Balun for 24GHz Car Radar","authors":"E. van der Heijden, H. Veenstra, D. Hartskeerl, M. Notten, D. van Goor","doi":"10.1109/SMIC.2008.26","DOIUrl":"https://doi.org/10.1109/SMIC.2008.26","url":null,"abstract":"This paper discusses the design, simulation and measurement results of a single-ended to differential Low Noise Amplifier (LNA) for 24 GHz short range car radar applications in a production 0.25 mum SiGe:C-BiCMOS technology [1]. The input and two single-ended outputs are designed for 50 Omega impedance. The LNA achieves a measured 13.2 dB gain and 4.2dB noise figure at 24 GHz. Simulations and measurements are in close agreement. The achieved gain and noise figure are as good as for an earlier reported fully single-ended LNA [2]. No balun is required. The 0.55 x 0.60 mm IC dissipates 40 mW from a 3.3 V supply.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116827013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. El Kaamouchi, G. Dambrine, M. Si Moussa, M. Emam, D. Vanhoenacker-Janvier, J. Raskin
This work investigates the possibility to tune the zero-temperature-coefficient (ZTC) points in partially depleted (PD) SOI nMOSFET technology by controlling the body-source forward bias (VBS). Measured transconductance and drain current in the saturation region at temperatures between 25 and 200degC were observed for various body-source forward bias conditions. It is found that the variation of threshold voltage (VTH) with body bias has an influence on ZTC points. The measurement results show wide voltage-range of gate-voltage giving either the transconductance ZTC point (VGS,ZTC9m) or the drain-current ZTC point (VGS,ZTC1DS) opening important opportunities in RF circuits design for nigh temperature applications.
本研究探讨了通过控制体源正向偏置(VBS)来调整部分耗尽(PD) SOI nMOSFET技术中零温度系数(ZTC)点的可能性。在温度介于25℃至200℃之间的饱和区测量了不同体源正向偏置条件下的跨导和漏极电流。发现阈值电压(VTH)随体偏置的变化对ZTC点有影响。测量结果显示，栅极电压的宽电压范围提供了跨导ZTC点(VGS,ZTC9m)或漏极电流ZTC点(VGS,ZTC1DS)，为夜间温度应用的射频电路设计开辟了重要的机会。
{"title":"Body-Biasing Control on Zero-Temperature-Coefficient in Partially Depleted SOI MOSFET","authors":"M. El Kaamouchi, G. Dambrine, M. Si Moussa, M. Emam, D. Vanhoenacker-Janvier, J. Raskin","doi":"10.1109/SMIC.2008.35","DOIUrl":"https://doi.org/10.1109/SMIC.2008.35","url":null,"abstract":"This work investigates the possibility to tune the zero-temperature-coefficient (ZTC) points in partially depleted (PD) SOI nMOSFET technology by controlling the body-source forward bias (VBS). Measured transconductance and drain current in the saturation region at temperatures between 25 and 200degC were observed for various body-source forward bias conditions. It is found that the variation of threshold voltage (VTH) with body bias has an influence on ZTC points. The measurement results show wide voltage-range of gate-voltage giving either the transconductance ZTC point (VGS,ZTC9m) or the drain-current ZTC point (VGS,ZTC1DS) opening important opportunities in RF circuits design for nigh temperature applications.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115812318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Daeik D. Kim, Jonghae Kim, Choongyeun Cho, J. Plouchart, R. Trzcinski
An RF and mm-wave platform developed in 65 nm SOI CMOS technology is presented. The SOI FET performance in a wired cell is measured up to fT=300 GHz and 200 GHz for NFET and PFET. Ring oscillator records 3.6 psec minimum inverter stage delay. Back-end-of-line vertical native capacitor (VNCAP) and on-chip inductor performances are reported. The performance scaling trends of mmWave PLL front-end components are presented.
提出了一种基于65nm SOI CMOS技术的射频和毫米波平台。在有线单元中测量的SOI FET性能最高可达fT=300 GHz和200 GHz，用于FET和FET。环形振荡器记录3.6 psec最小逆变级延迟。报告了后端垂直原生电容(VNCAP)和片上电感的性能。介绍了毫米波锁相环前端器件的性能扩展趋势。
{"title":"65nm SOI CMOS SoC Technology for Low-Power mmWave and RF Platform","authors":"Daeik D. Kim, Jonghae Kim, Choongyeun Cho, J. Plouchart, R. Trzcinski","doi":"10.1109/SMIC.2008.18","DOIUrl":"https://doi.org/10.1109/SMIC.2008.18","url":null,"abstract":"An RF and mm-wave platform developed in 65 nm SOI CMOS technology is presented. The SOI FET performance in a wired cell is measured up to fT=300 GHz and 200 GHz for NFET and PFET. Ring oscillator records 3.6 psec minimum inverter stage delay. Back-end-of-line vertical native capacitor (VNCAP) and on-chip inductor performances are reported. The performance scaling trends of mmWave PLL front-end components are presented.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116471488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The influence of ballasting resistor implementations on the RF performance (both small-signal and large-signal) and on the linearity of common-base (CB) SiGe power HBTs is experimentally investigated. It is demonstrated that higher RF performance and better linearity can be achieved from CB SiGe HBTs by using emitter ballasting scheme than using base ballasting scheme.
{"title":"Impact of Ballast Resistor Implementations on Linearity and RF Performance of Common-Base SiGe Power HBTs","authors":"Hui Li, Guoxuan Qin, Z. Ma, P. Ma, M. Racanelli","doi":"10.1109/SMIC.2008.24","DOIUrl":"https://doi.org/10.1109/SMIC.2008.24","url":null,"abstract":"The influence of ballasting resistor implementations on the RF performance (both small-signal and large-signal) and on the linearity of common-base (CB) SiGe power HBTs is experimentally investigated. It is demonstrated that higher RF performance and better linearity can be achieved from CB SiGe HBTs by using emitter ballasting scheme than using base ballasting scheme.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128929625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A dual channel satellite radio receiver that solves the deep fading effect specific to the automotive mobile environment by using antenna diversity was realized in a 0.18μm SiGe BiCMOS technology. The tuner power dissipation was reduced by using a second-zero-IF dual conversion architecture that requires a lower ADC sampling frequency and resolution. A single PLL drives the RF and IF mixers of both signal paths, resulting in a smaller die area and lower power dissipation. Providing a digital baseband I/Q output allows the implementation of the channel decode IC in a standard digital CMOS process, reducing the overall receiver cost. SDARS tuner performance includes: 5dB noise figure, 55dB image rejection, -100dBm input sensitivity, +15dBm IIP3 at min gain, 40/60dB RF/IF AGC range, 200mA current consumption from a 3.3V supply in dual channel operation and 26mm2 die area.
{"title":"Notice of Violation of IEEE Publication PrinciplesAntenna Diversity Zero-Second-IF SiGe BiCMOS Satellite Radio Tuner for Deep Fading Automotive Mobile Reception","authors":"A. Maxim, C. Turinici, M. Gheorge","doi":"10.1109/SMIC.2008.7","DOIUrl":"https://doi.org/10.1109/SMIC.2008.7","url":null,"abstract":"A dual channel satellite radio receiver that solves the deep fading effect specific to the automotive mobile environment by using antenna diversity was realized in a 0.18μm SiGe BiCMOS technology. The tuner power dissipation was reduced by using a second-zero-IF dual conversion architecture that requires a lower ADC sampling frequency and resolution. A single PLL drives the RF and IF mixers of both signal paths, resulting in a smaller die area and lower power dissipation. Providing a digital baseband I/Q output allows the implementation of the channel decode IC in a standard digital CMOS process, reducing the overall receiver cost. SDARS tuner performance includes: 5dB noise figure, 55dB image rejection, -100dBm input sensitivity, +15dBm IIP3 at min gain, 40/60dB RF/IF AGC range, 200mA current consumption from a 3.3V supply in dual channel operation and 26mm2 die area.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123082414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Use of sub-design-rule (SDR) thick-gate-oxide MOS structures can significantly improve RF performance. Utilizing 3-stack 3.3-V MOSFET's with an SDR channel length, a 31.3-dBm 900-MHz Bulk CMOS T/R switch with transmit (TX) and receive (RX) insertion losses of 0.5 and 1.0 dB is realized. A 28-dBm 2.4-GHz T/R switch with TX and RX insertion losses of 0.8 and 1.2 dB is also demonstrated. SDR MOS varactors achieve Qmin of ~ 80 at 24 GHz with a tuning range of ~ 40%.
{"title":"Thick-Gate-Oxide MOS Structures with Sub-Design-Rule (SDR) Polysilicon Lengths for RF Circuit Applications","authors":"H. Xu, K. O","doi":"10.1109/SMIC.2008.53","DOIUrl":"https://doi.org/10.1109/SMIC.2008.53","url":null,"abstract":"Use of sub-design-rule (SDR) thick-gate-oxide MOS structures can significantly improve RF performance. Utilizing 3-stack 3.3-V MOSFET's with an SDR channel length, a 31.3-dBm 900-MHz Bulk CMOS T/R switch with transmit (TX) and receive (RX) insertion losses of 0.5 and 1.0 dB is realized. A 28-dBm 2.4-GHz T/R switch with TX and RX insertion losses of 0.8 and 1.2 dB is also demonstrated. SDR MOS varactors achieve Qmin of ~ 80 at 24 GHz with a tuning range of ~ 40%.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114388061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Quach, C. Bryant, G. Creech, K. Groves, T. James, A. Mattamana, P. Orlando, V. Patel, R. Drangmeister, L. Johnson, B. Kormanyos, R. Bonebright
This paper reports a demonstration of X-band receiver RF front-end components and the integrated chipset implemented in 0.18 mum silicon germanium (SiGe) technology. The system architecture consists of a single down conversion from X-band at the input to S-band at the intermediate frequency (IF) output. The microwave monolithic integrated circuit (MMIC) includes an X-band low noise amplifier, lead-lag splitter, balanced amplifiers, double balanced mixer, absorptive filter, and an IF amplifier. The integrated chip achieved greater than 30 dB of gain and less than 6 dB of noise figure.
{"title":"X-Band Receiver Front-End Chip in Silicon Germanium Technology","authors":"T. Quach, C. Bryant, G. Creech, K. Groves, T. James, A. Mattamana, P. Orlando, V. Patel, R. Drangmeister, L. Johnson, B. Kormanyos, R. Bonebright","doi":"10.1109/SMIC.2008.11","DOIUrl":"https://doi.org/10.1109/SMIC.2008.11","url":null,"abstract":"This paper reports a demonstration of X-band receiver RF front-end components and the integrated chipset implemented in 0.18 mum silicon germanium (SiGe) technology. The system architecture consists of a single down conversion from X-band at the input to S-band at the intermediate frequency (IF) output. The microwave monolithic integrated circuit (MMIC) includes an X-band low noise amplifier, lead-lag splitter, balanced amplifiers, double balanced mixer, absorptive filter, and an IF amplifier. The integrated chip achieved greater than 30 dB of gain and less than 6 dB of noise figure.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127124335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents a CMOS RF power amplifier (PA) for 1.9 GHz, which has been realized in a standard 0.13 mum CMOS technology. The PA has a two-stage balanced push-pull structure. The stages are coupled by an LC matching network. It is a prestudy for an integrated PA in a single-chip DECT phone. Due to low breakdown voltages of the CMOS transistors in modern technologies, reliability aspects were paid special attention to for the PA design and layout. The PA can be operated with supply voltages of more than 3.6 V. An off-chip microstrip balun is used for transformation of the load impedance and differential-to-single-ended conversion. The fabricated amplifier has an output power of 540 mW (27.3 dBm) at 2.5 V supply and a power added efficiency (PAE) of 37% and meets the requirements for DECT.
本文提出了一种1.9 GHz的CMOS射频功率放大器(PA)，该放大器采用标准的0.13 μ m CMOS技术实现。PA采用两级平衡推拉结构。各级通过LC匹配网络进行耦合。这是在单片DECT电话中集成PA的预研究。由于现代技术中CMOS晶体管的击穿电压较低，可靠性问题在放大器的设计和布局中尤为重要。PA可以在3.6 V以上的电源电压下工作。片外微带平衡器用于负载阻抗转换和差分到单端转换。该放大器在2.5 V电源下的输出功率为540mw (27.3 dBm)，功率附加效率(PAE)为37%，满足DECT要求。
{"title":"A 27.3dBm DECT Power Amplifier for 2.5V Supply in 0.13μm CMOS","authors":"N. Zimmermann, T. Johansson, S. Heinen","doi":"10.1109/SMIC.2008.14","DOIUrl":"https://doi.org/10.1109/SMIC.2008.14","url":null,"abstract":"This work presents a CMOS RF power amplifier (PA) for 1.9 GHz, which has been realized in a standard 0.13 mum CMOS technology. The PA has a two-stage balanced push-pull structure. The stages are coupled by an LC matching network. It is a prestudy for an integrated PA in a single-chip DECT phone. Due to low breakdown voltages of the CMOS transistors in modern technologies, reliability aspects were paid special attention to for the PA design and layout. The PA can be operated with supply voltages of more than 3.6 V. An off-chip microstrip balun is used for transformation of the load impedance and differential-to-single-ended conversion. The fabricated amplifier has an output power of 540 mW (27.3 dBm) at 2.5 V supply and a power added efficiency (PAE) of 37% and meets the requirements for DECT.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129035717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose a modeling methodology to determine the optimum dimensions of slots in ground shield metal of slow-wave transmission lines. We induce a mutual inductance between a signal conductor and return ground current paths to express an equivalent inductance of the transmission line. The model's accuracy is confirmed by characterization of a fabricated transmission line TEG.
{"title":"Characterization and Modeling of Microstrip Transmission Lines with Slow-Wave Effect","authors":"T. Masuda, N. Shiramizu, T. Nakamura, K. Washio","doi":"10.1109/SMIC.2008.45","DOIUrl":"https://doi.org/10.1109/SMIC.2008.45","url":null,"abstract":"We propose a modeling methodology to determine the optimum dimensions of slots in ground shield metal of slow-wave transmission lines. We induce a mutual inductance between a signal conductor and return ground current paths to express an equivalent inductance of the transmission line. The model's accuracy is confirmed by characterization of a fabricated transmission line TEG.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115273887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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