We present a wideband resistive feedback CMOS low-noise amplifier (LNA) with noise cancellation technique for ultra-wideband applications. The LNA achieves a 3-dB bandwidth of 0.7-6.5 GHz, power gain of 12.5 dB, and noise figure of 3.5-4.2 dB within the 3-dB bandwidth. The input matching is better than -11 dB from 0.7 to 12 GHz. The IIP3 is measured -5 dBm at 5 GHz. It is implemented in a 0.18 mum standard digital CMOS technology, occupies an area of 0.78 mmtimes0.68 mm, and consumes 11.1 mW from a 1.8 V supply.
{"title":"An Ultra-Wideband Resistive-Feedback Low-Noise Amplifier with Noise Cancellation in 0.18μm Digital CMOS","authors":"Jianyun Hu, Yunliang Zhu, Hui Wu","doi":"10.1109/SMIC.2008.61","DOIUrl":"https://doi.org/10.1109/SMIC.2008.61","url":null,"abstract":"We present a wideband resistive feedback CMOS low-noise amplifier (LNA) with noise cancellation technique for ultra-wideband applications. The LNA achieves a 3-dB bandwidth of 0.7-6.5 GHz, power gain of 12.5 dB, and noise figure of 3.5-4.2 dB within the 3-dB bandwidth. The input matching is better than -11 dB from 0.7 to 12 GHz. The IIP3 is measured -5 dBm at 5 GHz. It is implemented in a 0.18 mum standard digital CMOS technology, occupies an area of 0.78 mmtimes0.68 mm, and consumes 11.1 mW from a 1.8 V supply.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"01 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129672706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Millimeter-wave commercial communication systems are getting a lot of attention in the recent years, and therefore there is a need of implementing miniaturized high-quality passive components at these frequencies. In this paper, we demonstrate the integration of ultra-miniaturized cavities on the thin-film multi-chip module technology (MCM-D) by using through-substrate vias on 100 mum thick high-resistivity silicon (HRSi) wafers. Having HRSi as filling material, the proposed cavities are 3.4 times smaller than air filled cavities. Being integrated cavities, no assembly step is needed, which is an advantage as compared to air filled cavities where wafer stacking is required. The influence of leakage through the via fences is studied in detail showing that having a via diameter of 100 mum, and a pitch of 220 mum, one via row is enough to eliminate radiation at 29 GHz, but at 60 GHz 2 via rows are necessary. Additionally, this study shows that the probe feeding mechanism used in this work is very effective and does not lead to any leakage. Second-order filters using integrated cavities are demonstrated at 29 GHz and 60 GHz yielding low losses and a highly accurate center frequency prediction the first time that the filters were manufactured. Being able to implement small and high-quality components, the proposed technology is a viable platform for the implementation of commercial millimeter-wave components.
{"title":"Ultra-Miniaturized Integrated Cavities on High-Resistivity Silicon Thin-Film MCM-D Technology","authors":"G. Posada, G. Carchon, B. Nauwelaers, W. De Raedt","doi":"10.1109/SMIC.2008.41","DOIUrl":"https://doi.org/10.1109/SMIC.2008.41","url":null,"abstract":"Millimeter-wave commercial communication systems are getting a lot of attention in the recent years, and therefore there is a need of implementing miniaturized high-quality passive components at these frequencies. In this paper, we demonstrate the integration of ultra-miniaturized cavities on the thin-film multi-chip module technology (MCM-D) by using through-substrate vias on 100 mum thick high-resistivity silicon (HRSi) wafers. Having HRSi as filling material, the proposed cavities are 3.4 times smaller than air filled cavities. Being integrated cavities, no assembly step is needed, which is an advantage as compared to air filled cavities where wafer stacking is required. The influence of leakage through the via fences is studied in detail showing that having a via diameter of 100 mum, and a pitch of 220 mum, one via row is enough to eliminate radiation at 29 GHz, but at 60 GHz 2 via rows are necessary. Additionally, this study shows that the probe feeding mechanism used in this work is very effective and does not lead to any leakage. Second-order filters using integrated cavities are demonstrated at 29 GHz and 60 GHz yielding low losses and a highly accurate center frequency prediction the first time that the filters were manufactured. Being able to implement small and high-quality components, the proposed technology is a viable platform for the implementation of commercial millimeter-wave components.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129688356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Herzel, S. Glisic, S. Osmany, J. Scheytt, K. Schmalz, W. Winkler, M. Engels
We present a dual-loop PLL architecture for low-noise frequency synthesizers. The approach is experimentally verified for a 48 GHz PLL in 0.25 mum SiGe BiCMOS technology intended for a 60 GHz wireless transceiver. The design employs two parallel charge pumps one of which dominates the loop dynamics and is biased at optimum output voltage. This equalizes the loop bandwidth and reduces charge pump mismatch.
{"title":"A Fully Integrated 48-GHz Low-Noise PLL with a Constant Loop Bandwidth","authors":"F. Herzel, S. Glisic, S. Osmany, J. Scheytt, K. Schmalz, W. Winkler, M. Engels","doi":"10.1109/SMIC.2008.27","DOIUrl":"https://doi.org/10.1109/SMIC.2008.27","url":null,"abstract":"We present a dual-loop PLL architecture for low-noise frequency synthesizers. The approach is experimentally verified for a 48 GHz PLL in 0.25 mum SiGe BiCMOS technology intended for a 60 GHz wireless transceiver. The design employs two parallel charge pumps one of which dominates the loop dynamics and is biased at optimum output voltage. This equalizes the loop bandwidth and reduces charge pump mismatch.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"418 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126704257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The thermal resistance of SiGe HBTs for high power applications reduces significantly when the bias current increases. This phenomenon is explained by both measurements and simulations for the first time.
{"title":"Kirk Effect Induced Bias Dependency of Thermal Resistance in SiGe HBTs","authors":"Hao Jiang, Jieyin Zheng, M. Recanelli","doi":"10.1109/SMIC.2008.25","DOIUrl":"https://doi.org/10.1109/SMIC.2008.25","url":null,"abstract":"The thermal resistance of SiGe HBTs for high power applications reduces significantly when the bias current increases. This phenomenon is explained by both measurements and simulations for the first time.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121411503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The optimizations of the growth of barium strontium titanate (BST) on silicon substrate requires very accurate characterization method of its intrinsic losses. The total losses in the structure are computed from its measured tuned RF performance for different applied bias and then a full deembedding of the ohmic losses is carried out by the substruction of the total losses at zero bias, enabling the intrinsic-loss of the BST thin film to be extracted. The losses of the BST material is both frequency and voltage dependent. The losses of the BST found to be frequency dependent up to 10 GHz.
{"title":"Losses Characterization of Tunable Barium Strontium Titanate Materials Integrated on Silicon Substrate","authors":"M. Al Ahmad, R. Plana","doi":"10.1109/SMIC.2008.46","DOIUrl":"https://doi.org/10.1109/SMIC.2008.46","url":null,"abstract":"The optimizations of the growth of barium strontium titanate (BST) on silicon substrate requires very accurate characterization method of its intrinsic losses. The total losses in the structure are computed from its measured tuned RF performance for different applied bias and then a full deembedding of the ohmic losses is carried out by the substruction of the total losses at zero bias, enabling the intrinsic-loss of the BST thin film to be extracted. The losses of the BST material is both frequency and voltage dependent. The losses of the BST found to be frequency dependent up to 10 GHz.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121844772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The realization of SIMMWICs (silicon millimeter-wave integrated circuits) for frequencies above 100 GHz is presented. Epitaxial layers grown with molecular beam epitaxy and low-loss microstrip lines allow the implementation of a variety of devices required for basic system-on-chip building blocks. The applied silicon technology using Al/AlNiSi contacts offers excellent integration possibilities. Schottky diodes are designed for Mott mode operation and feature cutoff-frequencies of more than 700 GHz. Substrate membranes with a thickness of 50 mum are created by applying a selective etching process using silicon on insulator (SOI) wafers. Different microstrip circuit designs demonstrate the integration potential. Finally, two singly balanced mixer designs with low LO-power drive demands and low conversion loss characteristics are exposed. We choose the 122 GHz ISM band as an example for the demonstration of the potential of this cost-effective integration approach.
{"title":"SIMMWICs on Micromachined Silicon on Insulator Substrates Beyond 100 GHz","authors":"A. Muller, E. Kasper","doi":"10.1109/SMIC.2008.13","DOIUrl":"https://doi.org/10.1109/SMIC.2008.13","url":null,"abstract":"The realization of SIMMWICs (silicon millimeter-wave integrated circuits) for frequencies above 100 GHz is presented. Epitaxial layers grown with molecular beam epitaxy and low-loss microstrip lines allow the implementation of a variety of devices required for basic system-on-chip building blocks. The applied silicon technology using Al/AlNiSi contacts offers excellent integration possibilities. Schottky diodes are designed for Mott mode operation and feature cutoff-frequencies of more than 700 GHz. Substrate membranes with a thickness of 50 mum are created by applying a selective etching process using silicon on insulator (SOI) wafers. Different microstrip circuit designs demonstrate the integration potential. Finally, two singly balanced mixer designs with low LO-power drive demands and low conversion loss characteristics are exposed. We choose the 122 GHz ISM band as an example for the demonstration of the potential of this cost-effective integration approach.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116584464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Large-signal power performance of SiGe power HBTs are compared between common-emitter (CE) and common-base (CB) configurations with different layout structures and different unit subcells. Experiment results show that at high frequency (6 GHz), CB SiGe power HBTs have both higher small-signal and large-signal power gain values than the CE configuration. With optimization of layout and unit subcells, the power performance of both CE and CB SiGe power HBTs is significantly improved. The CB SiGe HBTs maintain the superior power gain characteristics over the CE SiGe HBTs in high frequency range, while CE SiGe HBTs become superior to CB SiGe HBTs in the low frequency range. The reasons for the device performance improvement and rules of optimizing power cell layout are discussed.
{"title":"Impact of Power Cell Design on RF Performance of CE and CB SiGe Power HBTs","authors":"Guoxuan Qin, Z. Ma, J. Lopez, D. Lie","doi":"10.1109/SMIC.2008.23","DOIUrl":"https://doi.org/10.1109/SMIC.2008.23","url":null,"abstract":"Large-signal power performance of SiGe power HBTs are compared between common-emitter (CE) and common-base (CB) configurations with different layout structures and different unit subcells. Experiment results show that at high frequency (6 GHz), CB SiGe power HBTs have both higher small-signal and large-signal power gain values than the CE configuration. With optimization of layout and unit subcells, the power performance of both CE and CB SiGe power HBTs is significantly improved. The CB SiGe HBTs maintain the superior power gain characteristics over the CE SiGe HBTs in high frequency range, while CE SiGe HBTs become superior to CB SiGe HBTs in the low frequency range. The reasons for the device performance improvement and rules of optimizing power cell layout are discussed.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129990661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Mourot, P. Bar, C. Arnaud, G. Parat, J. Carpentier
This work presents the design and the measured performances of a duplexer based on bulk acoustic wave coupled resonator filter (BAW CRF) for W-CDMA application. This device is dedicated to be integrated in a RF module for cellular phone. A co-simulation methodology between a 1D acoustic model (Mason-type) and an electromagnetic solver is developed to allow a good prediction of the filter response on a large frequency range. The minimum insertion loss for the Tx and Rx filter is better than -3 dB and the isolation between Tx and Rx ports is greater than 60 dB. The rejection of the Tx filter is better than -50 dB in the Rx frequency range and is up to -67 dB in the Tx frequency range. The CRFs handle up to 27 dBm at Tx center frequency.
{"title":"Coupled Resonator Filters for W-CDMA Duplexer Application","authors":"L. Mourot, P. Bar, C. Arnaud, G. Parat, J. Carpentier","doi":"10.1109/SMIC.2008.60","DOIUrl":"https://doi.org/10.1109/SMIC.2008.60","url":null,"abstract":"This work presents the design and the measured performances of a duplexer based on bulk acoustic wave coupled resonator filter (BAW CRF) for W-CDMA application. This device is dedicated to be integrated in a RF module for cellular phone. A co-simulation methodology between a 1D acoustic model (Mason-type) and an electromagnetic solver is developed to allow a good prediction of the filter response on a large frequency range. The minimum insertion loss for the Tx and Rx filter is better than -3 dB and the isolation between Tx and Rx ports is greater than 60 dB. The rejection of the Tx filter is better than -50 dB in the Rx frequency range and is up to -67 dB in the Tx frequency range. The CRFs handle up to 27 dBm at Tx center frequency.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134209109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A broadband low-noise amplifier (LNA) in a 0.13 mum CMOS is presented. The LNA consists of two cascaded gain stages. The first stage is a resistive feedback amplifier for an input impedance matching, and the second stage is an inductive peaking amplifier for gain compensation. Measurement results exhibit a voltage gain of 14 dB and a gain variation less than 1.7 dB over the frequency range of 0.1 to 6.0 GHz. Its input return loss is below -8.3 dB and the noise figure is 4.0 to 4.7 dB across the bandwidth. The LNA consumes 16 mW from a 1.2 V supply and occupies 0.13 mm2.
{"title":"A 1.2V, 0.1-6.0 GHz, Two-Stage Differential LNA Using Gain Compensation Scheme","authors":"J. Wadatsumi, S. Kousai, D. Miyashita, M. Hamada","doi":"10.1109/SMIC.2008.50","DOIUrl":"https://doi.org/10.1109/SMIC.2008.50","url":null,"abstract":"A broadband low-noise amplifier (LNA) in a 0.13 mum CMOS is presented. The LNA consists of two cascaded gain stages. The first stage is a resistive feedback amplifier for an input impedance matching, and the second stage is an inductive peaking amplifier for gain compensation. Measurement results exhibit a voltage gain of 14 dB and a gain variation less than 1.7 dB over the frequency range of 0.1 to 6.0 GHz. Its input return loss is below -8.3 dB and the noise figure is 4.0 to 4.7 dB across the bandwidth. The LNA consumes 16 mW from a 1.2 V supply and occupies 0.13 mm2.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132960073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A peak fT of 325 GHz is achieved, for the first time, in a 130 nm, 200 GHz, 3rd-generation SiGe HBT technology at 300 K, by utilizing fT-doubler techniques. This speed enhancement is equivalent to gaining an additional generational node (from 3rd to 4th), with no underlying change to the transistor profile or lithography. The fT-doubler can be treated as a single transistor unit cell during circuit design, which is verified by the investigation of its small-signal equivalent circuit. Reduced Cpi is demonstrated to be the root origin of the fT-enhancement. The impact of emitter geometry on performance is investigated. A record fT of 438 GHz is achieved at 93 K.
{"title":"Enhancing the Speed of SiGe HBTs Using fT-Doubler Techniques","authors":"Jiahui Yuan, J. Cressler","doi":"10.1109/SMIC.2008.19","DOIUrl":"https://doi.org/10.1109/SMIC.2008.19","url":null,"abstract":"A peak f<sub>T</sub> of 325 GHz is achieved, for the first time, in a 130 nm, 200 GHz, 3<sup>rd</sup>-generation SiGe HBT technology at 300 K, by utilizing f<sub>T</sub>-doubler techniques. This speed enhancement is equivalent to gaining an additional generational node (from 3<sup>rd</sup> to 4<sup>th</sup>), with no underlying change to the transistor profile or lithography. The f<sub>T</sub>-doubler can be treated as a single transistor unit cell during circuit design, which is verified by the investigation of its small-signal equivalent circuit. Reduced C<sub>pi</sub> is demonstrated to be the root origin of the f<sub>T</sub>-enhancement. The impact of emitter geometry on performance is investigated. A record f<sub>T</sub> of 438 GHz is achieved at 93 K.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130514607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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