Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193352
H. Nomura, R. Suzuki, T. Kutsuki, T. Saraya, T. Hiramoto
The mechanism of high mobility in <;110>;-directed nanowire pMOSFETs with height of 10nm on (100) SOI substrate is investigated. The 9nm-wide nanowire pFET has higher mobility than the (100) universal mobility at 300K The temperature dependence measurements of hole mobility show that the high mobility in nanowire pFET originates from the effect of (110) side surface of the nanowire. On the other hand, it is shown that the degraded mobility in 4nm-wide nanowire pFET is caused by the increase in surface roughness scattering.
{"title":"Mechanisms of high hole mobility in (100) nanowire pMOSFETs with width of less than 10nm","authors":"H. Nomura, R. Suzuki, T. Kutsuki, T. Saraya, T. Hiramoto","doi":"10.1109/ULIS.2012.6193352","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193352","url":null,"abstract":"The mechanism of high mobility in <;110>;-directed nanowire pMOSFETs with height of 10nm on (100) SOI substrate is investigated. The 9nm-wide nanowire pFET has higher mobility than the (100) universal mobility at 300K The temperature dependence measurements of hole mobility show that the high mobility in nanowire pFET originates from the effect of (110) side surface of the nanowire. On the other hand, it is shown that the degraded mobility in 4nm-wide nanowire pFET is caused by the increase in surface roughness scattering.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114132144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193381
M. Bounouar, A. Beaumont, F. Calmon, D. Drouin
Single Electron Transistors have the potential to be a very promising candidate for future computing architectures due to their low voltage operation and low power consumption. In this paper, for the first time, logic cells based on metallic SET operating at room temperature and up to 125 °C were designed. An evaluation of the energy consumption and a comparison with their equivalents in CMOS technology has been made. Based on results using accurate SET model, SET-based logic cells provide a significant consumption reduction as compared with their CMOS counterparts.
{"title":"On the use of nanoelectronic logic cells based on metallic Single Electron Transistors","authors":"M. Bounouar, A. Beaumont, F. Calmon, D. Drouin","doi":"10.1109/ULIS.2012.6193381","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193381","url":null,"abstract":"Single Electron Transistors have the potential to be a very promising candidate for future computing architectures due to their low voltage operation and low power consumption. In this paper, for the first time, logic cells based on metallic SET operating at room temperature and up to 125 °C were designed. An evaluation of the energy consumption and a comparison with their equivalents in CMOS technology has been made. Based on results using accurate SET model, SET-based logic cells provide a significant consumption reduction as compared with their CMOS counterparts.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116348443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193368
E. Dentoni Litta, P. Hellstrom, C. Henkel, M. Ostling
This work addresses the issue of interfacial layer formation in scaled high-k/metal gate stacks: the possibility of growing a thin SiOx interfacial layer in situ in a commercial ALD reactor has been evaluated, employing ozone-based Si oxidation. Three techniques (O3, O3/H2O and Pulsed) have been developed to grow scaled sub-nm interfacial layers and have been integrated in MOS capacitors and MOSFETs. A comparison based on electrical characterization shows that the performance of the proposed in situ methods is comparable or superior to that of existing ex situ techniques; specifically, the O3 method can grow aggressively scaled interfacial layers (4-5 Å) while preserving the electrical quality of the stack.
{"title":"In situ SiOx interfacial layer formation for scaled ALD high-k/metal gate stacks","authors":"E. Dentoni Litta, P. Hellstrom, C. Henkel, M. Ostling","doi":"10.1109/ULIS.2012.6193368","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193368","url":null,"abstract":"This work addresses the issue of interfacial layer formation in scaled high-k/metal gate stacks: the possibility of growing a thin SiOx interfacial layer in situ in a commercial ALD reactor has been evaluated, employing ozone-based Si oxidation. Three techniques (O3, O3/H2O and Pulsed) have been developed to grow scaled sub-nm interfacial layers and have been integrated in MOS capacitors and MOSFETs. A comparison based on electrical characterization shows that the performance of the proposed in situ methods is comparable or superior to that of existing ex situ techniques; specifically, the O3 method can grow aggressively scaled interfacial layers (4-5 Å) while preserving the electrical quality of the stack.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125873298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193356
Alfonso Alarcón, V. Nguyen, J. Saint-Martin, A. Bournel, P. Dollfus
We present a numerical study of the transport behavior of a top-gate 2D-graphene field-effect transistor with boron nitride as substrate and gate insulator material. It is based on a non-equilibrium Green's function approach to solving a tight-binding Hamiltonian of graphene, self-consistently coupled with 2D-Poisson's equation. The analysis emphasizes the effects of the chiral character of carriers in graphene in the different conduction regimes, including Klein and band-to-band tunneling processes. We investigate the effects of gate length and gate insulator thickness, and the possible effect of BN-induced bandgap opening on the device characteristics, in particular in terms of on/off ratio, short-channel effect and saturation behavior, found to be in good agreement with experimental results. Additionally, the possibility of current oscillations and negative differential conductance typical of GFET is demonstrated.
{"title":"Transport behaviors of graphene 2D field-effect transistors on boron nitride substrate","authors":"Alfonso Alarcón, V. Nguyen, J. Saint-Martin, A. Bournel, P. Dollfus","doi":"10.1109/ULIS.2012.6193356","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193356","url":null,"abstract":"We present a numerical study of the transport behavior of a top-gate 2D-graphene field-effect transistor with boron nitride as substrate and gate insulator material. It is based on a non-equilibrium Green's function approach to solving a tight-binding Hamiltonian of graphene, self-consistently coupled with 2D-Poisson's equation. The analysis emphasizes the effects of the chiral character of carriers in graphene in the different conduction regimes, including Klein and band-to-band tunneling processes. We investigate the effects of gate length and gate insulator thickness, and the possible effect of BN-induced bandgap opening on the device characteristics, in particular in terms of on/off ratio, short-channel effect and saturation behavior, found to be in good agreement with experimental results. Additionally, the possibility of current oscillations and negative differential conductance typical of GFET is demonstrated.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"418 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134640518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193344
C. Diouf, A. Cros, P. Morin, S. Renard, X. Federspiel, M. Rafik, A. Bianchi, J. Rosa, G. Ghibaudo
A comparative study of the effects of high pressure deuterium and hydrogen final anneal (HPD2FA and HPH2FA) is for the first time performed. Effects of high pressure final anneal (HPFA) on the electronic transport is deeply investigated. Reduction of the Coulomb scattering due to interface traps and possibly oxygen vacancies is evidenced after HPFA, and the link with long and short channel transport is explicited. The reliability of the annealed devices is also briefly discussed in terms of hot carrier injection (HCI) and negative bias thermal instability (NBTI).
{"title":"On the understanding of the effects of high pressure deuterium and hydrogen final anneal","authors":"C. Diouf, A. Cros, P. Morin, S. Renard, X. Federspiel, M. Rafik, A. Bianchi, J. Rosa, G. Ghibaudo","doi":"10.1109/ULIS.2012.6193344","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193344","url":null,"abstract":"A comparative study of the effects of high pressure deuterium and hydrogen final anneal (HPD2FA and HPH2FA) is for the first time performed. Effects of high pressure final anneal (HPFA) on the electronic transport is deeply investigated. Reduction of the Coulomb scattering due to interface traps and possibly oxygen vacancies is evidenced after HPFA, and the link with long and short channel transport is explicited. The reliability of the annealed devices is also briefly discussed in terms of hot carrier injection (HCI) and negative bias thermal instability (NBTI).","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122057198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193361
D. Griveau, S. Ecoffey, R. Parekh, M. Bounouar, Francis Calmon, Jacques Beauvais, Dominique Drouin
This paper presents a comparative study of a one-bit-full-adder cell based on metallic complementary capacitively coupled single-electron transistors with its 22 nm CMOS counterpart. Performance and energy efficiency are investigated. The CMOS-like single-electron transistor based full adder is used in two operating mode, hysteresis and non-hysteresis. Parallel and serial single electron transistors designs are introduced. The single electron inverter consumes less than 90.4 pW while it dissipates 4.21 nW in CMOS technology.
{"title":"Single electron CMOS-like one bit full adder","authors":"D. Griveau, S. Ecoffey, R. Parekh, M. Bounouar, Francis Calmon, Jacques Beauvais, Dominique Drouin","doi":"10.1109/ULIS.2012.6193361","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193361","url":null,"abstract":"This paper presents a comparative study of a one-bit-full-adder cell based on metallic complementary capacitively coupled single-electron transistors with its 22 nm CMOS counterpart. Performance and energy efficiency are investigated. The CMOS-like single-electron transistor based full adder is used in two operating mode, hysteresis and non-hysteresis. Parallel and serial single electron transistors designs are introduced. The single electron inverter consumes less than 90.4 pW while it dissipates 4.21 nW in CMOS technology.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117295835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193362
T. Holtij, M. Schwarz, A. Kloes, B. Iñíguez
We derived an analytical two-dimensional model to calculate the potential within ultra-scaled junctionless double-gate MOSFETs (DG MOSFETs) valid in subthreshold region. We propose an approach how to calculate the threshold voltage of such devices, and present our first results. Compared to conventional MOSFETs, the proposed junctionless transistor has no pn-junctions. Its type of doping in the channel region is the same as in the source/drain. The device is turned on by creating a conducting channel in the center of the silicon, and turned off by depleting it. To ensure a safe switching behavior, the investigation of the subthreshold region is therefore important. A Comparison of our model with numerical simulation results confirms its validity for ultra-scaled devices having a channel length about 22 nm.
{"title":"2D analytical potential modeling of junctionless DG MOSFETs in subthreshold region including proposal for calculating the threshold voltage","authors":"T. Holtij, M. Schwarz, A. Kloes, B. Iñíguez","doi":"10.1109/ULIS.2012.6193362","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193362","url":null,"abstract":"We derived an analytical two-dimensional model to calculate the potential within ultra-scaled junctionless double-gate MOSFETs (DG MOSFETs) valid in subthreshold region. We propose an approach how to calculate the threshold voltage of such devices, and present our first results. Compared to conventional MOSFETs, the proposed junctionless transistor has no pn-junctions. Its type of doping in the channel region is the same as in the source/drain. The device is turned on by creating a conducting channel in the center of the silicon, and turned off by depleting it. To ensure a safe switching behavior, the investigation of the subthreshold region is therefore important. A Comparison of our model with numerical simulation results confirms its validity for ultra-scaled devices having a channel length about 22 nm.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"2 23","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114044452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193379
F. Pittino, F. Widdershoven, L. Selmi
This paper presents a case study of the interaction between nanoelectrodes and dielectric nanoparticles possibly representative of biomolecules in a simple cylindrical capacitive biosensor. The small signal admittance change due to the insertion of the biomolecule in the biosensor electrolyte is studied as a function of the position, aspect ratio and charge of the biomolecule and of the signal frequency. Results suggest clear advantages in operating the biosensor beyond the electrolyte cutoff frequency.
{"title":"Efficient DC and AC simulation of nanoelectrode-nanoparticle interactions in capacitive biosensors","authors":"F. Pittino, F. Widdershoven, L. Selmi","doi":"10.1109/ULIS.2012.6193379","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193379","url":null,"abstract":"This paper presents a case study of the interaction between nanoelectrodes and dielectric nanoparticles possibly representative of biomolecules in a simple cylindrical capacitive biosensor. The small signal admittance change due to the insertion of the biomolecule in the biosensor electrolyte is studied as a function of the position, aspect ratio and charge of the biomolecule and of the signal frequency. Results suggest clear advantages in operating the biosensor beyond the electrolyte cutoff frequency.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128287542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193378
R. Yu, S. Das, R. Hobbs, Y. Georgiev, I. Ferain, P. Razavi, N. Akhavan, C. Colinge, J. Colinge
An initial top-down process of Germanium nanowires is developed in this work. The Silicon Nitride (Si3N4) is used as a hard mask to obtain a stable surface for lithography and a resistive mask for etch. The electron-beam lithography (EBL) is utilized for patterning the nanowires with Hydrogen Silsesquixane (HSQ) as a negative photoresist. Several different etch conditions are examined to transfer the patterns into the substrate.
{"title":"Top-down process of Germanium nanowires using EBL exposure of Hydrogen Silsesquioxane resist","authors":"R. Yu, S. Das, R. Hobbs, Y. Georgiev, I. Ferain, P. Razavi, N. Akhavan, C. Colinge, J. Colinge","doi":"10.1109/ULIS.2012.6193378","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193378","url":null,"abstract":"An initial top-down process of Germanium nanowires is developed in this work. The Silicon Nitride (Si3N4) is used as a hard mask to obtain a stable surface for lithography and a resistive mask for etch. The electron-beam lithography (EBL) is utilized for patterning the nanowires with Hydrogen Silsesquixane (HSQ) as a negative photoresist. Several different etch conditions are examined to transfer the patterns into the substrate.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128989950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193371
F. Murphy-Armando, S. Fahy
First-principles electronic structure methods are used to predict the piezoresistance of n-type Si1-xGex at various alloy compositions and strain configurations. We report very large gauge factors, G = dρ/dϵ/ρ, where ρ is resistivity and ϵ is strain: for compositions x ≃ 0.90 under uniaxial strain in the 〈111〉 direction, G >; 500. These gauge factors are over three times larger than the best values for single crystalline bulk Si. This large change in resistance due to strain is explained by the change in the occupancy of the higher-conductance L valley relative to the lower-conductance Δ valley, coupled to a change in inter-valley alloy and phonon scattering.
{"title":"Very large piezoresistance in Si1−xGex alloys","authors":"F. Murphy-Armando, S. Fahy","doi":"10.1109/ULIS.2012.6193371","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193371","url":null,"abstract":"First-principles electronic structure methods are used to predict the piezoresistance of n-type Si<sub>1-x</sub>Ge<sub>x</sub> at various alloy compositions and strain configurations. We report very large gauge factors, G = dρ/dϵ/ρ, where ρ is resistivity and ϵ is strain: for compositions x ≃ 0.90 under uniaxial strain in the 〈111〉 direction, G >; 500. These gauge factors are over three times larger than the best values for single crystalline bulk Si. This large change in resistance due to strain is explained by the change in the occupancy of the higher-conductance L valley relative to the lower-conductance Δ valley, coupled to a change in inter-valley alloy and phonon scattering.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132348757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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