Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193368
E. Dentoni Litta, P. Hellstrom, C. Henkel, M. Ostling
This work addresses the issue of interfacial layer formation in scaled high-k/metal gate stacks: the possibility of growing a thin SiOx interfacial layer in situ in a commercial ALD reactor has been evaluated, employing ozone-based Si oxidation. Three techniques (O3, O3/H2O and Pulsed) have been developed to grow scaled sub-nm interfacial layers and have been integrated in MOS capacitors and MOSFETs. A comparison based on electrical characterization shows that the performance of the proposed in situ methods is comparable or superior to that of existing ex situ techniques; specifically, the O3 method can grow aggressively scaled interfacial layers (4-5 Å) while preserving the electrical quality of the stack.
{"title":"In situ SiOx interfacial layer formation for scaled ALD high-k/metal gate stacks","authors":"E. Dentoni Litta, P. Hellstrom, C. Henkel, M. Ostling","doi":"10.1109/ULIS.2012.6193368","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193368","url":null,"abstract":"This work addresses the issue of interfacial layer formation in scaled high-k/metal gate stacks: the possibility of growing a thin SiOx interfacial layer in situ in a commercial ALD reactor has been evaluated, employing ozone-based Si oxidation. Three techniques (O3, O3/H2O and Pulsed) have been developed to grow scaled sub-nm interfacial layers and have been integrated in MOS capacitors and MOSFETs. A comparison based on electrical characterization shows that the performance of the proposed in situ methods is comparable or superior to that of existing ex situ techniques; specifically, the O3 method can grow aggressively scaled interfacial layers (4-5 Å) while preserving the electrical quality of the stack.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125873298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193356
Alfonso Alarcón, V. Nguyen, J. Saint-Martin, A. Bournel, P. Dollfus
We present a numerical study of the transport behavior of a top-gate 2D-graphene field-effect transistor with boron nitride as substrate and gate insulator material. It is based on a non-equilibrium Green's function approach to solving a tight-binding Hamiltonian of graphene, self-consistently coupled with 2D-Poisson's equation. The analysis emphasizes the effects of the chiral character of carriers in graphene in the different conduction regimes, including Klein and band-to-band tunneling processes. We investigate the effects of gate length and gate insulator thickness, and the possible effect of BN-induced bandgap opening on the device characteristics, in particular in terms of on/off ratio, short-channel effect and saturation behavior, found to be in good agreement with experimental results. Additionally, the possibility of current oscillations and negative differential conductance typical of GFET is demonstrated.
{"title":"Transport behaviors of graphene 2D field-effect transistors on boron nitride substrate","authors":"Alfonso Alarcón, V. Nguyen, J. Saint-Martin, A. Bournel, P. Dollfus","doi":"10.1109/ULIS.2012.6193356","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193356","url":null,"abstract":"We present a numerical study of the transport behavior of a top-gate 2D-graphene field-effect transistor with boron nitride as substrate and gate insulator material. It is based on a non-equilibrium Green's function approach to solving a tight-binding Hamiltonian of graphene, self-consistently coupled with 2D-Poisson's equation. The analysis emphasizes the effects of the chiral character of carriers in graphene in the different conduction regimes, including Klein and band-to-band tunneling processes. We investigate the effects of gate length and gate insulator thickness, and the possible effect of BN-induced bandgap opening on the device characteristics, in particular in terms of on/off ratio, short-channel effect and saturation behavior, found to be in good agreement with experimental results. Additionally, the possibility of current oscillations and negative differential conductance typical of GFET is demonstrated.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"418 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134640518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193389
A. Revelant, P. Palestri, L. Selmi
We present a newly developed model for Tunnel-FET (TFET) devices capable to describe band-to-band tunneling (BtBT) as well as off-equilibrium transport of the generated carriers. BtBT generation is implemented as an add-on into an existing Multi-subband Monte Carlo (MSMC) transport simulator that accounts for the effects of alternative channel materials and high-κ dielectrics. A simple correction for the calculation of the BtBT generation rate is proposed to account for carrier confinement in the subbands.
{"title":"Multi-subband semi-classical simulation of n-type Tunnel-FETs","authors":"A. Revelant, P. Palestri, L. Selmi","doi":"10.1109/ULIS.2012.6193389","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193389","url":null,"abstract":"We present a newly developed model for Tunnel-FET (TFET) devices capable to describe band-to-band tunneling (BtBT) as well as off-equilibrium transport of the generated carriers. BtBT generation is implemented as an add-on into an existing Multi-subband Monte Carlo (MSMC) transport simulator that accounts for the effects of alternative channel materials and high-κ dielectrics. A simple correction for the calculation of the BtBT generation rate is proposed to account for carrier confinement in the subbands.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124950129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193382
M. Nozue, R. Suzuki, H. Nomura, T. Saraya, T. Hiramoto
A single electron transistor (SET) with floating gate, which has a non-volatile memory effect, is successfully integrated with MOS circuits. By applying high voltage generated by the charge pump circuit to the floating gate SET, the characteristics control of Coulomb blockade oscillation is demonstrated for the first time at room temperature. This attempt will open a new path of adding new functionality to conventional MOS circuits by integration with so-called Beyond CMOS devices.
{"title":"Characteristics control of single electron transistor with floating gate by charge pump circuit","authors":"M. Nozue, R. Suzuki, H. Nomura, T. Saraya, T. Hiramoto","doi":"10.1109/ULIS.2012.6193382","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193382","url":null,"abstract":"A single electron transistor (SET) with floating gate, which has a non-volatile memory effect, is successfully integrated with MOS circuits. By applying high voltage generated by the charge pump circuit to the floating gate SET, the characteristics control of Coulomb blockade oscillation is demonstrated for the first time at room temperature. This attempt will open a new path of adding new functionality to conventional MOS circuits by integration with so-called Beyond CMOS devices.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125022425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193392
K. Romanjek, F. Andrieu, J. Cluzel, L. Brevard, P. Perreau, C. Tabone, G. Guégan, T. Poiroux
We demonstrate one of the most compact 1 Transistor DRAM (1T-DRAM) cell on Ultra-Thin-Body and 25nm thin Buried oxide (UTBB) down to a gate width of Wg=80nm and length of Lg=35nm for embedded DRAM applications. We have optimized the programming voltages and studied the influence of the device geometry (Wg, Lg) on the 1T-DRAM performance. The Meta Stable Dip (MSD) method provides high read current margin values, reaching 224μA/μm. This is the first experimental assessment of the MSD approach on such scaled 1T-DRAMs.
{"title":"Compact (Wg/Lg=80/85nm) FDSOI 1T-DRAM programmed by Meta Stable Dip","authors":"K. Romanjek, F. Andrieu, J. Cluzel, L. Brevard, P. Perreau, C. Tabone, G. Guégan, T. Poiroux","doi":"10.1109/ULIS.2012.6193392","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193392","url":null,"abstract":"We demonstrate one of the most compact 1 Transistor DRAM (1T-DRAM) cell on Ultra-Thin-Body and 25nm thin Buried oxide (UTBB) down to a gate width of Wg=80nm and length of Lg=35nm for embedded DRAM applications. We have optimized the programming voltages and studied the influence of the device geometry (Wg, Lg) on the 1T-DRAM performance. The Meta Stable Dip (MSD) method provides high read current margin values, reaching 224μA/μm. This is the first experimental assessment of the MSD approach on such scaled 1T-DRAMs.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134043199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193390
M. Schmidt, L. Knoll, S. Richter, A. Schafer, J. Hartmann, Qing-Tai Zhao, S. Mantl
Tunneling field-effect transistors (TFETs) were fabricated from compressively strained Si/SiGe wafers with a stepped gate to enhance band to band tunneling. In-situ highly p-doped Si0.5Ge0.5 was used as source and As-implanted Si as drain. For the gate stack, conformal HfO2 (k = 22) and TiN were deposited, which resulted in an effective oxide thickness (EOT) of ~ 1nm. The TFET devices exhibit minimum point inverse subthreshold slopes as small as 65 mV/dec with applied back-gate voltage, and greatly suppressed ambipolar behavior. The improved performance compared to homogeneous planar devices is attributed to the superiority of the source/channel heterojunction and the shallow p-i junction.
{"title":"Si/SiGe hetero-structure tunneling field effect transistors with in-situ doped SiGe source","authors":"M. Schmidt, L. Knoll, S. Richter, A. Schafer, J. Hartmann, Qing-Tai Zhao, S. Mantl","doi":"10.1109/ULIS.2012.6193390","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193390","url":null,"abstract":"Tunneling field-effect transistors (TFETs) were fabricated from compressively strained Si/SiGe wafers with a stepped gate to enhance band to band tunneling. In-situ highly p-doped Si0.5Ge0.5 was used as source and As-implanted Si as drain. For the gate stack, conformal HfO2 (k = 22) and TiN were deposited, which resulted in an effective oxide thickness (EOT) of ~ 1nm. The TFET devices exhibit minimum point inverse subthreshold slopes as small as 65 mV/dec with applied back-gate voltage, and greatly suppressed ambipolar behavior. The improved performance compared to homogeneous planar devices is attributed to the superiority of the source/channel heterojunction and the shallow p-i junction.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115856107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193359
M. G. C. de Andrade, J. Martino, M. Aoulaiche, N. Collaert, E. Simoen, C. Claeys
The Low-Frequency (LF) noise in Bulk and DTMOS triple-gate FinFETs is experimentally investigated under 60 MeV proton irradiation. Moreover, the important figures of merit for the analog performance such as Early voltage and intrinsic voltage gain will be analyzed. The results indicate that the better electrical characteristics and analog performance of DTMOS FinFETs make them very competitive candidates for low-noise RF analog applications in a radiation environment.
{"title":"Low-frequency noise behaviour of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiaton","authors":"M. G. C. de Andrade, J. Martino, M. Aoulaiche, N. Collaert, E. Simoen, C. Claeys","doi":"10.1109/ULIS.2012.6193359","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193359","url":null,"abstract":"The Low-Frequency (LF) noise in Bulk and DTMOS triple-gate FinFETs is experimentally investigated under 60 MeV proton irradiation. Moreover, the important figures of merit for the analog performance such as Early voltage and intrinsic voltage gain will be analyzed. The results indicate that the better electrical characteristics and analog performance of DTMOS FinFETs make them very competitive candidates for low-noise RF analog applications in a radiation environment.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116163841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193372
T. Nicoletti, S. Santos, L. Almeida, J. Martino, M. Aoulaiche, A. Veloso, M. Jurczak, E. Simoen, C. Claeys
In this paper we explore, from DC measurements, the impact of gate length scaling on the main digital/analog parameters of Ultra-Thin Buried Oxide (UTBOX) Fully Depleted Silicon-on-Insulator (FDSOI) devices at different temperatures. Standard junction reference devices are compared with the extension-less ones where the latter present superior characteristics for smaller device lengths such as improved DIBL, SS and IGIDL apart from the higher Ion/Ioff ratio, VEA and AV. The temperature tends to degrade all the device parameters although the extension-less structures show to be less susceptible to its influence.
{"title":"The impact of gate length scaling on UTBOX FDSOI devices: The digital/analog performance of extension-less structures","authors":"T. Nicoletti, S. Santos, L. Almeida, J. Martino, M. Aoulaiche, A. Veloso, M. Jurczak, E. Simoen, C. Claeys","doi":"10.1109/ULIS.2012.6193372","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193372","url":null,"abstract":"In this paper we explore, from DC measurements, the impact of gate length scaling on the main digital/analog parameters of Ultra-Thin Buried Oxide (UTBOX) Fully Depleted Silicon-on-Insulator (FDSOI) devices at different temperatures. Standard junction reference devices are compared with the extension-less ones where the latter present superior characteristics for smaller device lengths such as improved DIBL, SS and IGIDL apart from the higher Ion/Ioff ratio, VEA and AV. The temperature tends to degrade all the device parameters although the extension-less structures show to be less susceptible to its influence.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129937590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193364
D. Kotekar-Patil, Stefan Jauerneck, M. Ruoff, D. Wharam, D. Kern, X. Jehl, R. Wacquez, M. Sanquer
Low temperature electron transport measurements of single electron transistors fabricated in advanced CMOS technology with polysilicon gates not only exhibit clear Coulomb blockade behavior but also show a large number of additional conductance fluctuations in the nonlinear regime. By comparison with simulations these features are quantitatively attributed to the effects of discretely charged islands in the polysilicon gates.
{"title":"Charge granularity in single electron transistors with polysilicon gates","authors":"D. Kotekar-Patil, Stefan Jauerneck, M. Ruoff, D. Wharam, D. Kern, X. Jehl, R. Wacquez, M. Sanquer","doi":"10.1109/ULIS.2012.6193364","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193364","url":null,"abstract":"Low temperature electron transport measurements of single electron transistors fabricated in advanced CMOS technology with polysilicon gates not only exhibit clear Coulomb blockade behavior but also show a large number of additional conductance fluctuations in the nonlinear regime. By comparison with simulations these features are quantitatively attributed to the effects of discretely charged islands in the polysilicon gates.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130137338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193346
Sung Min Kim, Sejoon Lee, E. B. Song, S. Seo, D. Seo, K. Wang
A The non-volatile gEOTMs are fabricated using a single-layer graphene (SLG) channel with an Al2O3 gate oxide layer, in which an ion-bombarded AlOx layer is intentionally formed by oxygen ion bombardment (OIB) to create the charge trap sites. The whole processes are carried out at temperature below 120°C to exploit gEOTM's compatibility to the flexible substrates. The devices shows a large memory window (>; 11.0 V), attributing to the effective electron-injection into the trap sites in AlOx. The results suggest that the gEOTM has potential applications for the high-density-memory devices and modules in flexible electronics.
{"title":"Graphene-based embedded-oxide-trap memory (gEOTM) for flexible electronics application","authors":"Sung Min Kim, Sejoon Lee, E. B. Song, S. Seo, D. Seo, K. Wang","doi":"10.1109/ULIS.2012.6193346","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193346","url":null,"abstract":"A The non-volatile gEOTMs are fabricated using a single-layer graphene (SLG) channel with an Al2O3 gate oxide layer, in which an ion-bombarded AlOx layer is intentionally formed by oxygen ion bombardment (OIB) to create the charge trap sites. The whole processes are carried out at temperature below 120°C to exploit gEOTM's compatibility to the flexible substrates. The devices shows a large memory window (>; 11.0 V), attributing to the effective electron-injection into the trap sites in AlOx. The results suggest that the gEOTM has potential applications for the high-density-memory devices and modules in flexible electronics.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131059380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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