Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193374
B. Roche, B. Voisin, X. Jehl, M. Sanquer, R. Wacquez, M. Vinet, V. Deshpande, B. Previtali
A dual mode device has been realized with FDSOI MOSFET technology implementing both a single electron transistor (SET) and a field effect transistor (FET). The silicon substrate is used as a back gate to choose between these two functionalities. We show in this paper that the behavior of the device is determined by the position of the electron gas in the silicon mesa: the device is a SET if the electron gas is created by the top gate, and behaves as a FET when the back gate induces a electron gas at the bottom of the silicon mesa. This opens the possibility to design hybrid circuits exploiting both advantages of FETs and SETs.
{"title":"Realization of both a single electron transistor and a field effect transistor with an underlapped FDSOI MOSFET geometry","authors":"B. Roche, B. Voisin, X. Jehl, M. Sanquer, R. Wacquez, M. Vinet, V. Deshpande, B. Previtali","doi":"10.1109/ULIS.2012.6193374","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193374","url":null,"abstract":"A dual mode device has been realized with FDSOI MOSFET technology implementing both a single electron transistor (SET) and a field effect transistor (FET). The silicon substrate is used as a back gate to choose between these two functionalities. We show in this paper that the behavior of the device is determined by the position of the electron gas in the silicon mesa: the device is a SET if the electron gas is created by the top gate, and behaves as a FET when the back gate induces a electron gas at the bottom of the silicon mesa. This opens the possibility to design hybrid circuits exploiting both advantages of FETs and SETs.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132080365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193355
S. Richter, S. Trellenkamp, M. Schmidt, A. Schafer, K. Bourdelle, Q. Zhao, S. Mantl
This paper presents experimental results on metal oxide semiconductor field-effect transistors (MOSFETs) featuring an array of 1000 trigated uniaxially strained nanowires with a cross-sections of 15 × 15 nm2 in combination with a HfO2/TiN gate stack. The high uniaxial strain along the wires reduces the band gap energy by approximately 140 meV and enhances the electron mobility. Ideal inverse subthreshold slopes of n- and p-channel devices of 60 (62) mV/dec at room temperature and Ion/Ioff ratios up to 1010 were obtained.
{"title":"Strained silicon nanowire array MOSFETs with high-k/metal gate stack","authors":"S. Richter, S. Trellenkamp, M. Schmidt, A. Schafer, K. Bourdelle, Q. Zhao, S. Mantl","doi":"10.1109/ULIS.2012.6193355","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193355","url":null,"abstract":"This paper presents experimental results on metal oxide semiconductor field-effect transistors (MOSFETs) featuring an array of 1000 trigated uniaxially strained nanowires with a cross-sections of 15 × 15 nm<sup>2</sup> in combination with a HfO<sub>2</sub>/TiN gate stack. The high uniaxial strain along the wires reduces the band gap energy by approximately 140 meV and enhances the electron mobility. Ideal inverse subthreshold slopes of n- and p-channel devices of 60 (62) mV/dec at room temperature and I<sub>on</sub>/I<sub>off</sub> ratios up to 10<sup>10</sup> were obtained.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133633406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193367
X. Lian, S. Long, C. Cagli, J. Buckley, E. Miranda, Ming Liu, J. Suñé
The quantum point contact (QPC) model, originally developed to model the conduction after soft and hard breakdown events in thin-oxide MOS devices, is applied to resistive random access memories (RRAM). The QPC model is based on the idea that the conducting filament (CF) behaves as a quantum wire and it is shown to adequately describe the conduction in the low-resistance state (LRS) and in the high-resistance state (HRS). These two regimes show linear and nonlinear current-voltage (I-V) characteristics, respectively. In the LRS, the CF shows metallic conduction properties and the signature of conductance quantization. In the HRS, the conduction is linear at low and high enough voltages, and it is strongly nonlinear in the transition between these two linear regimes. After showing that the model is adequate for both the LRS and the HRS, the QPC picture is used to provide a compact model for the whole dynamic switching cycle of CF-based RRAM devices and memristors.
{"title":"Quantum point contact model of filamentary conduction in resistive switching memories","authors":"X. Lian, S. Long, C. Cagli, J. Buckley, E. Miranda, Ming Liu, J. Suñé","doi":"10.1109/ULIS.2012.6193367","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193367","url":null,"abstract":"The quantum point contact (QPC) model, originally developed to model the conduction after soft and hard breakdown events in thin-oxide MOS devices, is applied to resistive random access memories (RRAM). The QPC model is based on the idea that the conducting filament (CF) behaves as a quantum wire and it is shown to adequately describe the conduction in the low-resistance state (LRS) and in the high-resistance state (HRS). These two regimes show linear and nonlinear current-voltage (I-V) characteristics, respectively. In the LRS, the CF shows metallic conduction properties and the signature of conductance quantization. In the HRS, the conduction is linear at low and high enough voltages, and it is strongly nonlinear in the transition between these two linear regimes. After showing that the model is adequate for both the LRS and the HRS, the QPC picture is used to provide a compact model for the whole dynamic switching cycle of CF-based RRAM devices and memristors.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131320599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193343
S. Flachowsky, T. Herrmann, J. Hontschel, R. Illgen, S. Ong, M. Wiatr, T. Baldauf, W. Klix, R. Stenzel
The impact of compressive and tensile stress on CMOS performance is studied for <;100>; and <;110>; oriented silicon and SiGe channels. The <;110>; channel direction is found to be more stress sensitive whereas the <;100>; oriented transistor has a higher initial hole mobility. These results recommend to use the <;110>; channel orientation for high performance application due to the high drive current gain and <;100>; channel orientation for low power applications where no stress elements are included to ease the overall process complexity and to decrease costs.
{"title":"Mobility and strain effects for <100> and <110> oriented silicon and SiGe transistor channels","authors":"S. Flachowsky, T. Herrmann, J. Hontschel, R. Illgen, S. Ong, M. Wiatr, T. Baldauf, W. Klix, R. Stenzel","doi":"10.1109/ULIS.2012.6193343","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193343","url":null,"abstract":"The impact of compressive and tensile stress on CMOS performance is studied for <;100>; and <;110>; oriented silicon and SiGe channels. The <;110>; channel direction is found to be more stress sensitive whereas the <;100>; oriented transistor has a higher initial hole mobility. These results recommend to use the <;110>; channel orientation for high performance application due to the high drive current gain and <;100>; channel orientation for low power applications where no stress elements are included to ease the overall process complexity and to decrease costs.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133332999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193348
T. Dutta, Q. Rafhay, R. Clerc, J. Lacord, S. Monfray, G. Pananakakis, F. Boeuf, G. Ghibaudo
This paper investigates the different mechanisms responsible for the increase of short channel effects in III-V MOSFETs. As expected, the first origin of this increase is due to the higher dielectric constant of III-V semiconductors. The second is due to their small density of states, which induces larger DIBL, but only in the strong inversion regime, due to larger dark space. Finally, barrier layers, used in the Quantum Well FET architecture, are shown to cause additional DIBL increase.
{"title":"Origins of the short channel effects increase in III-V nMOSFET technologies","authors":"T. Dutta, Q. Rafhay, R. Clerc, J. Lacord, S. Monfray, G. Pananakakis, F. Boeuf, G. Ghibaudo","doi":"10.1109/ULIS.2012.6193348","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193348","url":null,"abstract":"This paper investigates the different mechanisms responsible for the increase of short channel effects in III-V MOSFETs. As expected, the first origin of this increase is due to the higher dielectric constant of III-V semiconductors. The second is due to their small density of states, which induces larger DIBL, but only in the strong inversion regime, due to larger dark space. Finally, barrier layers, used in the Quantum Well FET architecture, are shown to cause additional DIBL increase.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128995659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193376
M. Turowski, A. Raman, W. Xiong
Detailed, physics-based three-dimensional (3D) technology computer-aided-design (TCAD) device model, coupled in mixed-mode with external load circuit and parasitics, enabled accurate simulation of single-event effects (SEEs) in nonplanar silicon-on-insulator (SOI) Multi-Gate Field Effect Transistors (MuGFETs) or FinFETs. We show the importance of correct device physics models, including mobility in different crystal planes of strained silicon - validated with experimental data - for correct computation of both steady-state and transient characteristics of FinFETs. Mixed-mode coupling of a realistic load circuit, including experimental parasitics, with the 3D TCAD device model, is critical to be able to compute single-event transient current waveforms and charge collection characteristics that reflect well experimental results.
{"title":"Accurate modeling of SOI Multi-Gate FETs and their transient response to radiation","authors":"M. Turowski, A. Raman, W. Xiong","doi":"10.1109/ULIS.2012.6193376","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193376","url":null,"abstract":"Detailed, physics-based three-dimensional (3D) technology computer-aided-design (TCAD) device model, coupled in mixed-mode with external load circuit and parasitics, enabled accurate simulation of single-event effects (SEEs) in nonplanar silicon-on-insulator (SOI) Multi-Gate Field Effect Transistors (MuGFETs) or FinFETs. We show the importance of correct device physics models, including mobility in different crystal planes of strained silicon - validated with experimental data - for correct computation of both steady-state and transient characteristics of FinFETs. Mixed-mode coupling of a realistic load circuit, including experimental parasitics, with the 3D TCAD device model, is critical to be able to compute single-event transient current waveforms and charge collection characteristics that reflect well experimental results.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126973209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193360
G. Darbandy, J. Aghassi, J. Sedlmeir, U. Monga, I. Garduño, A. Cerdeira, B. Iñíguez
This paper presents Double Gate (DG) MOSFET models of the temperature dependences as part of a compact analytical model for the direct tunneling gate leakage and Trap-Assisted-Tunneling (TAT) current. We compare the adapted modeling calculations with experimental data of the gate leakage current in Trigate MOSFETs at various temperatures. The results of the direct tunneling current in the strong inversion regime and TAT in the subthreshold regime show good agreement with temperature dependent measurements with SiON as a gate oxide material. Our analysis above threshold voltage shows that the direct tunneling gate leakage current is clearly dominant over the TAT, while it is the opposite below threshold.
{"title":"Temperature dependence of compact analytical modeling of gate tunneling current in Double Gate MOSFETs","authors":"G. Darbandy, J. Aghassi, J. Sedlmeir, U. Monga, I. Garduño, A. Cerdeira, B. Iñíguez","doi":"10.1109/ULIS.2012.6193360","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193360","url":null,"abstract":"This paper presents Double Gate (DG) MOSFET models of the temperature dependences as part of a compact analytical model for the direct tunneling gate leakage and Trap-Assisted-Tunneling (TAT) current. We compare the adapted modeling calculations with experimental data of the gate leakage current in Trigate MOSFETs at various temperatures. The results of the direct tunneling current in the strong inversion regime and TAT in the subthreshold regime show good agreement with temperature dependent measurements with SiON as a gate oxide material. Our analysis above threshold voltage shows that the direct tunneling gate leakage current is clearly dominant over the TAT, while it is the opposite below threshold.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129627386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193358
A. Basavalingappa, Anumeha, G. Sheu
Energy capability of a LDMOS device structure is shown to have nonlinear relationship with ambient temperature. Analytical model for energy capability has been discussed and is in good agreement with the simulation results. The dependency of critical temperature on ambient temperature is shown.
{"title":"Energy capability of LDMOS as a function of ambient temperature","authors":"A. Basavalingappa, Anumeha, G. Sheu","doi":"10.1109/ULIS.2012.6193358","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193358","url":null,"abstract":"Energy capability of a LDMOS device structure is shown to have nonlinear relationship with ambient temperature. Analytical model for energy capability has been discussed and is in good agreement with the simulation results. The dependency of critical temperature on ambient temperature is shown.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"153 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114005099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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