Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193386
I. Ben Akkez, C. Fenouillet-Béranger, A. Cros, P. Perreau, S. Haendler, O. Weber, F. Andrieu, D. Pellissier-Tanon, F. Abbate, C. Richard, R. Beneyton, P. Gouraud, A. Margain, C. Borowiak, E. Gourvest, K. Bourdelle, B. Nguyen, T. Poiroux, T. Skotnicki, O. Faynot, F. Balestra, G. Ghibaudo, F. Boeuf
In this paper, we compare the electrical properties of Ultra Thin Buried Oxide (UTBOX) Fully Depleted Silicon On Insulator (FD-SOI) MOS devices for rotated and not rotated substrate with different gate lengths. We found a significant performance enhancement on FD-SOI PMOSFETs as expected, while keeping a good control of short channel effects. Surprisingly, to a lower extent, an improvement is also found for NMOS devices. We have also studied the carrier mobility degradation as a function of temperature and we point out the contribution of different mechanisms that reduce the mobility such as impurity Coulomb scattering, phonons and neutral defects as a function gate length. We find that there is no significant effect of rotated substrate on the mobility degradation. All these results are discussed and possible explanations are also given.
{"title":"Impact of substrate orientation on Ultra Thin BOX Fully Depleted SOI electrical performances","authors":"I. Ben Akkez, C. Fenouillet-Béranger, A. Cros, P. Perreau, S. Haendler, O. Weber, F. Andrieu, D. Pellissier-Tanon, F. Abbate, C. Richard, R. Beneyton, P. Gouraud, A. Margain, C. Borowiak, E. Gourvest, K. Bourdelle, B. Nguyen, T. Poiroux, T. Skotnicki, O. Faynot, F. Balestra, G. Ghibaudo, F. Boeuf","doi":"10.1109/ULIS.2012.6193386","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193386","url":null,"abstract":"In this paper, we compare the electrical properties of Ultra Thin Buried Oxide (UTBOX) Fully Depleted Silicon On Insulator (FD-SOI) MOS devices for rotated and not rotated substrate with different gate lengths. We found a significant performance enhancement on FD-SOI PMOSFETs as expected, while keeping a good control of short channel effects. Surprisingly, to a lower extent, an improvement is also found for NMOS devices. We have also studied the carrier mobility degradation as a function of temperature and we point out the contribution of different mechanisms that reduce the mobility such as impurity Coulomb scattering, phonons and neutral defects as a function gate length. We find that there is no significant effect of rotated substrate on the mobility degradation. All these results are discussed and possible explanations are also given.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121669453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193363
T. Kutsuki, K. Shimizu, H. Nomura, T. Saraya, T. Hiramoto
The direction dependence of hole mobility in (100) and (110) UTB pFETs has been investigated experimentally using special test device structures exclusive for the direction dependence measurements. It is found that there is no direction dependence under quantum confinement in (100) UTB pFETs with SOI thickness of 5nm. On the other hand, in (110) UTB pFETs, it is shown that hole mobility superiority in <;110>; to <;100>; decreases at low temperature and in high inversion carrier density.
{"title":"Experimental investigation on direction dependence of Si (100) and Si (110) hole mobility in ultra-thin body pFETs","authors":"T. Kutsuki, K. Shimizu, H. Nomura, T. Saraya, T. Hiramoto","doi":"10.1109/ULIS.2012.6193363","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193363","url":null,"abstract":"The direction dependence of hole mobility in (100) and (110) UTB pFETs has been investigated experimentally using special test device structures exclusive for the direction dependence measurements. It is found that there is no direction dependence under quantum confinement in (100) UTB pFETs with SOI thickness of 5nm. On the other hand, in (110) UTB pFETs, it is shown that hole mobility superiority in <;110>; to <;100>; decreases at low temperature and in high inversion carrier density.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121471019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193370
A. Medury, K. Mercha, R. Ritzenthaler, A. De Keersgieter, T. Chiarella, N. Collaert, N. Bhat, K. N. Bhat
FinFETs are being considered as an attractive alternative to enable further CMOS Scaling. In this paper, a device scaling model for the electrostatics of bulk FinFETs is presented. Device parameters such as subthreshold slope (SS), threshold voltage (Vth), off-state current (IOFF)>; drain-induced-barrier lowering (DIBL) are modeled showing good agreement with TCAD and experimental results. Besides predicting the effects of technology scaling, this model provides good insight in terms of device design. By accounting for the effects of fin geometry variation and the drain voltage (Vd) on the effective fin doping (Na(ef)), the present work is very useful in determining Na(ff)) for low Vth, standard Vth and high Vth applications. Based on this model, it is also possible to determine the geometrical parameters required to achieve SS = 80 mV/dec, DIBL = 50 mV/V.
{"title":"Device scaling model for bulk FinFETs","authors":"A. Medury, K. Mercha, R. Ritzenthaler, A. De Keersgieter, T. Chiarella, N. Collaert, N. Bhat, K. N. Bhat","doi":"10.1109/ULIS.2012.6193370","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193370","url":null,"abstract":"FinFETs are being considered as an attractive alternative to enable further CMOS Scaling. In this paper, a device scaling model for the electrostatics of bulk FinFETs is presented. Device parameters such as subthreshold slope (SS), threshold voltage (Vth), off-state current (IOFF)>; drain-induced-barrier lowering (DIBL) are modeled showing good agreement with TCAD and experimental results. Besides predicting the effects of technology scaling, this model provides good insight in terms of device design. By accounting for the effects of fin geometry variation and the drain voltage (Vd) on the effective fin doping (Na(ef)), the present work is very useful in determining Na(ff)) for low Vth, standard Vth and high Vth applications. Based on this model, it is also possible to determine the geometrical parameters required to achieve SS = 80 mV/dec, DIBL = 50 mV/V.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"2 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113980821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193351
R. Coquand, S. Barraud, M. Cassé, P. Leroux, C. Vizioz, C. Comboroure, P. Perreau, E. Ernst, M. Samson, V. Maffini-Alvaro, C. Tabone, S. Barnola, D. Munteanu, G. Ghibaudo, S. Monfray, F. Boeuf, T. Poiroux
In this paper, Tri-Gate Nanowire (TGNW) FETs with high-k/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14 nm and beyond). The influence of Si film thickness (H) and nanowire width (W) on electrical performances of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by the additive contributions of the (100) top surface and (110) sidewalls. As compared to wide planar devices, the improvement of electrostatic integrity (SS and DIBL) of scaled down TGNW FET is clearly demonstrated.
{"title":"Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width","authors":"R. Coquand, S. Barraud, M. Cassé, P. Leroux, C. Vizioz, C. Comboroure, P. Perreau, E. Ernst, M. Samson, V. Maffini-Alvaro, C. Tabone, S. Barnola, D. Munteanu, G. Ghibaudo, S. Monfray, F. Boeuf, T. Poiroux","doi":"10.1109/ULIS.2012.6193351","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193351","url":null,"abstract":"In this paper, Tri-Gate Nanowire (TGNW) FETs with high-k/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14 nm and beyond). The influence of Si film thickness (H) and nanowire width (W) on electrical performances of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by the additive contributions of the (100) top surface and (110) sidewalls. As compared to wide planar devices, the improvement of electrostatic integrity (SS and DIBL) of scaled down TGNW FET is clearly demonstrated.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129216429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193384
B. Sklénard, C. Xu, P. Batude, B. Previtali, C. Tabone, Q. Rafhay, B. Colombeau, F. Khaja, I. Martín-Bragado, J. Berthoz, F. Allain, A. Toffoli, R. Kies, M. Jaud, P. Rivallin, S. Cristoloveanu, C. Tavernier, O. Faynot, T. Poiroux
In this paper, we demonstrate low junction leakage for devices fabricated at low temperature (≤ 650°C). This is explained by the reduced channel thickness of our device (6 nm). We show this through both experimental data and KMC simulations that enable to understand the origin of the leakage reduction.
{"title":"FDSOI devices: A solution to achieve low junction leakage with low temperature processes (≤ 650°C)","authors":"B. Sklénard, C. Xu, P. Batude, B. Previtali, C. Tabone, Q. Rafhay, B. Colombeau, F. Khaja, I. Martín-Bragado, J. Berthoz, F. Allain, A. Toffoli, R. Kies, M. Jaud, P. Rivallin, S. Cristoloveanu, C. Tavernier, O. Faynot, T. Poiroux","doi":"10.1109/ULIS.2012.6193384","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193384","url":null,"abstract":"In this paper, we demonstrate low junction leakage for devices fabricated at low temperature (≤ 650°C). This is explained by the reduced channel thickness of our device (6 nm). We show this through both experimental data and KMC simulations that enable to understand the origin of the leakage reduction.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126742134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193349
V. Djara, K. Cherkaoui, M. Schmidt, Y. Gomeniuk, E. O'Connor, I. Povey, D. O'Connell, S. Monaghan, M. Pemble, P. Hurley
Interface and oxide defects in surface-channel In0.53Ga0.47As n-MOSFETs, featuring a threshold voltage, VT, of 0.43 V, a subthreshold swing, SS, of 150 mV/dec, an ION/IOFF of ~ 104 and a source/drain resistance, RSD, of 103 Ω, have been investigated using “split C-V” measurements and self-consistent Poisson-Schrödinger quasi-static C-V simulations. An integrated density of traps across the In0.53Ga0.47As band gap at the Al2O3/In0.53Ga0.47As interface, NTrap, of ~ 7.8 × 1012 /cm2, has been obtained from a comparison of the theoretical and experimental quasi-static C-V responses, where NTrap reflects the combined contribution of interface traps and border traps. An equivalent surface density of fixed positive oxide charges, N+, of 1.4 × 1012 /cm2 is also reported. Finally, the application of the Maserjian Y-function to the Al2O3/In0.53Ga0.47As MOS system is briefly discussed.
{"title":"Study of interface and oxide defects in high-k/In0.53Ga0.47As n-MOSFETs","authors":"V. Djara, K. Cherkaoui, M. Schmidt, Y. Gomeniuk, E. O'Connor, I. Povey, D. O'Connell, S. Monaghan, M. Pemble, P. Hurley","doi":"10.1109/ULIS.2012.6193349","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193349","url":null,"abstract":"Interface and oxide defects in surface-channel In<sub>0.53</sub>Ga<sub>0.47</sub>As n-MOSFETs, featuring a threshold voltage, V<sub>T</sub>, of 0.43 V, a subthreshold swing, SS, of 150 mV/dec, an I<sub>ON</sub>/I<sub>OFF</sub> of ~ 10<sup>4</sup> and a source/drain resistance, R<sub>SD</sub>, of 103 Ω, have been investigated using “split C-V” measurements and self-consistent Poisson-Schrödinger quasi-static C-V simulations. An integrated density of traps across the In<sub>0.53</sub>Ga<sub>0.47</sub>As band gap at the Al<sub>2</sub>O<sub>3</sub>/In<sub>0.53</sub>Ga<sub>0.47</sub>As interface, N<sub>Trap</sub>, of ~ 7.8 × 10<sup>12</sup> /cm<sup>2</sup>, has been obtained from a comparison of the theoretical and experimental quasi-static C-V responses, where N<sub>Trap</sub> reflects the combined contribution of interface traps and border traps. An equivalent surface density of fixed positive oxide charges, N<sup>+</sup>, of 1.4 × 10<sup>12</sup> /cm<sup>2</sup> is also reported. Finally, the application of the Maserjian Y-function to the Al<sub>2</sub>O<sub>3</sub>/In<sub>0.53</sub>Ga<sub>0.47</sub>As MOS system is briefly discussed.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130665420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193347
A. D. Smith, S. Vaziri, A. Delin, M. Ostling, M. Lemme
The present paper describes a device structure for controlling and measuring strain in graphene membranes. We propose to induce strain by creating a pressure difference between the inside and the outside of a cavity covered with a graphene membrane. The combination of tight-binding calculations and a COMSOL model predicts strain induced band gaps in graphene for certain conditions and provides a guideline for potential device layouts. Raman spectroscopy on fabricated devices indicates the feasibility of this approach. Ultimately, pressure-induced band structure changes could be detected electrically, suggesting an application as ultra-sensitive pressure sensors.
{"title":"Strain engineering in suspended graphene devices for pressure sensor applications","authors":"A. D. Smith, S. Vaziri, A. Delin, M. Ostling, M. Lemme","doi":"10.1109/ULIS.2012.6193347","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193347","url":null,"abstract":"The present paper describes a device structure for controlling and measuring strain in graphene membranes. We propose to induce strain by creating a pressure difference between the inside and the outside of a cavity covered with a graphene membrane. The combination of tight-binding calculations and a COMSOL model predicts strain induced band gaps in graphene for certain conditions and provides a guideline for potential device layouts. Raman spectroscopy on fabricated devices indicates the feasibility of this approach. Ultimately, pressure-induced band structure changes could be detected electrically, suggesting an application as ultra-sensitive pressure sensors.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"129 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120907433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193375
M. Schwarz, T. Holtij, A. Kloes, B. Iñíguez
In this paper we present a new approach to calculate the tunneling and thermionic current in Schottky barrier Double-Gate MOSFETs (SB-DG-MOSFETs). This prediction is based on a physics-based two-dimensional analysis. Analytical approximations for the spatial tunneling current density and carrier distributions in the channel are introduced. From this explicit analytical model equations for the tunneling current are derived in closed-form which inherently include two-dimensional effects on the tunneling probability and the carrier distributions. Furthermore, an explicit analytical model equation for the thermionic current is derived. Comparison of the current with an already existing analytical numerical model and TCAD simulation data are in a good agreement for channel lengths down to 22nm.
{"title":"Explicit model for tunneling and thermionic current in Schottky barrier Double-Gate MOSFETs","authors":"M. Schwarz, T. Holtij, A. Kloes, B. Iñíguez","doi":"10.1109/ULIS.2012.6193375","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193375","url":null,"abstract":"In this paper we present a new approach to calculate the tunneling and thermionic current in Schottky barrier Double-Gate MOSFETs (SB-DG-MOSFETs). This prediction is based on a physics-based two-dimensional analysis. Analytical approximations for the spatial tunneling current density and carrier distributions in the channel are introduced. From this explicit analytical model equations for the tunneling current are derived in closed-form which inherently include two-dimensional effects on the tunneling probability and the carrier distributions. Furthermore, an explicit analytical model equation for the thermionic current is derived. Comparison of the current with an already existing analytical numerical model and TCAD simulation data are in a good agreement for channel lengths down to 22nm.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127235951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193352
H. Nomura, R. Suzuki, T. Kutsuki, T. Saraya, T. Hiramoto
The mechanism of high mobility in <;110>;-directed nanowire pMOSFETs with height of 10nm on (100) SOI substrate is investigated. The 9nm-wide nanowire pFET has higher mobility than the (100) universal mobility at 300K The temperature dependence measurements of hole mobility show that the high mobility in nanowire pFET originates from the effect of (110) side surface of the nanowire. On the other hand, it is shown that the degraded mobility in 4nm-wide nanowire pFET is caused by the increase in surface roughness scattering.
{"title":"Mechanisms of high hole mobility in (100) nanowire pMOSFETs with width of less than 10nm","authors":"H. Nomura, R. Suzuki, T. Kutsuki, T. Saraya, T. Hiramoto","doi":"10.1109/ULIS.2012.6193352","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193352","url":null,"abstract":"The mechanism of high mobility in <;110>;-directed nanowire pMOSFETs with height of 10nm on (100) SOI substrate is investigated. The 9nm-wide nanowire pFET has higher mobility than the (100) universal mobility at 300K The temperature dependence measurements of hole mobility show that the high mobility in nanowire pFET originates from the effect of (110) side surface of the nanowire. On the other hand, it is shown that the degraded mobility in 4nm-wide nanowire pFET is caused by the increase in surface roughness scattering.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114132144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-06DOI: 10.1109/ULIS.2012.6193381
M. Bounouar, A. Beaumont, F. Calmon, D. Drouin
Single Electron Transistors have the potential to be a very promising candidate for future computing architectures due to their low voltage operation and low power consumption. In this paper, for the first time, logic cells based on metallic SET operating at room temperature and up to 125 °C were designed. An evaluation of the energy consumption and a comparison with their equivalents in CMOS technology has been made. Based on results using accurate SET model, SET-based logic cells provide a significant consumption reduction as compared with their CMOS counterparts.
{"title":"On the use of nanoelectronic logic cells based on metallic Single Electron Transistors","authors":"M. Bounouar, A. Beaumont, F. Calmon, D. Drouin","doi":"10.1109/ULIS.2012.6193381","DOIUrl":"https://doi.org/10.1109/ULIS.2012.6193381","url":null,"abstract":"Single Electron Transistors have the potential to be a very promising candidate for future computing architectures due to their low voltage operation and low power consumption. In this paper, for the first time, logic cells based on metallic SET operating at room temperature and up to 125 °C were designed. An evaluation of the energy consumption and a comparison with their equivalents in CMOS technology has been made. Based on results using accurate SET model, SET-based logic cells provide a significant consumption reduction as compared with their CMOS counterparts.","PeriodicalId":350544,"journal":{"name":"2012 13th International Conference on Ultimate Integration on Silicon (ULIS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116348443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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