Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586241
T. Akioka, S. Yukutake, K. Fukui, K. Mitsumoto, A. Hiraishi, K. Nakagawa, N. Akiyama, M. Iwamura, Y. Kobayashi, S. Ikeda, H. Uchida
We describe new circuit techniques for an 8-11s ECL compatible 16Mb BiCMOS SRAM. This is the first reported implementation of ECL lOOK U0 compatibility with an operation voltage of less than 3.0V. We developed an ECL reference circuit that operates with a 2.3V supply voltage. A novel hierarchically divided common-emitter sense circuit reduces the delay due to long data lines to achieve a simulated address access time of 8ns under typical operating conditions.
{"title":"Circuit Techniques For An 8-ns Ecl 100K Compatible 3.3v 16mb Bicmos Sram With Minimum Operation Voltage Of 2.3v","authors":"T. Akioka, S. Yukutake, K. Fukui, K. Mitsumoto, A. Hiraishi, K. Nakagawa, N. Akiyama, M. Iwamura, Y. Kobayashi, S. Ikeda, H. Uchida","doi":"10.1109/VLSIC.1994.586241","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586241","url":null,"abstract":"We describe new circuit techniques for an 8-11s ECL compatible 16Mb BiCMOS SRAM. This is the first reported implementation of ECL lOOK U0 compatibility with an operation voltage of less than 3.0V. We developed an ECL reference circuit that operates with a 2.3V supply voltage. A novel hierarchically divided common-emitter sense circuit reduces the delay due to long data lines to achieve a simulated address access time of 8ns under typical operating conditions.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114064911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586249
M. Soyuer, J. Ewen, H.L. Chuang
A fully monolithic frcqucncy synthesizer PLL circuit implcmented in a 0.45pm CMOS tcchnology is prcscntcd. ?’lie test cliip consumcs 27omw at 1.25GIIz from a 3.3V supply. 1 he rms jitter of the gcnerated clock is 1.4~s. No external componcnts are uscd except supply dccoupling capacitois.
{"title":"A Fully Monolithic 1.25ghz cmos Frequency Synthesizer","authors":"M. Soyuer, J. Ewen, H.L. Chuang","doi":"10.1109/VLSIC.1994.586249","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586249","url":null,"abstract":"A fully monolithic frcqucncy synthesizer PLL circuit implcmented in a 0.45pm CMOS tcchnology is prcscntcd. ?’lie test cliip consumcs 27omw at 1.25GIIz from a 3.3V supply. 1 he rms jitter of the gcnerated clock is 1.4~s. No external componcnts are uscd except supply dccoupling capacitois.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125835734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586224
T. Ooishi, Y. Komiya, K. Hamade, Mho Asakura, K. Yasuda, K. Furutani, H. Hidaka, H. Miyamoto, H. Ozaki
This paper describes DRAM array driving techniques and the parameter scaling techniques for low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. Temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current for a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from the leakage current problem and the influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (V/sub th/), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the V/sub th/ of the MC-Tr simply (0.45 V at K=0.4) for the satisfaction of the small leakage current, for high speed and stable operation, and for high reliability (V/sub PP/ is below 2 V/sub CC/). They are applicable to subquarter micron DRAM's of 256 Mb and more. >
{"title":"An Automatic Temperature Compensation Of Internal Sense Ground For Sub-quarter Micron Drams","authors":"T. Ooishi, Y. Komiya, K. Hamade, Mho Asakura, K. Yasuda, K. Furutani, H. Hidaka, H. Miyamoto, H. Ozaki","doi":"10.1109/VLSIC.1994.586224","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586224","url":null,"abstract":"This paper describes DRAM array driving techniques and the parameter scaling techniques for low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. Temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current for a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from the leakage current problem and the influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (V/sub th/), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the V/sub th/ of the MC-Tr simply (0.45 V at K=0.4) for the satisfaction of the small leakage current, for high speed and stable operation, and for high reliability (V/sub PP/ is below 2 V/sub CC/). They are applicable to subquarter micron DRAM's of 256 Mb and more. >","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126175034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586204
S. Sidiropoulos, C. Yang, Mark Horowitz
This paper describes the design of a high speed interface for a multiprocessor interconnection network. To achieve higher transfer rates, the interface utilizes a voltage swing of 1 V, a Delay Line PLL and sampling of the data on both edges of the clock. Chips fabricated in a 0.8 pm CMOS technology achieve transfer rates of 700 Mbpdpin operating from a 3.3-V supply. Worst case measured peak-to-peak clock jitter is 260 ps (63 ps RMS). The layout area occupied by the DLL and the associated clock duty cycle adjuster is 460x800 pni2.
{"title":"A Cmos 500 Mbps/pin Synchronous Point to Point Link Interface","authors":"S. Sidiropoulos, C. Yang, Mark Horowitz","doi":"10.1109/VLSIC.1994.586204","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586204","url":null,"abstract":"This paper describes the design of a high speed interface for a multiprocessor interconnection network. To achieve higher transfer rates, the interface utilizes a voltage swing of 1 V, a Delay Line PLL and sampling of the data on both edges of the clock. Chips fabricated in a 0.8 pm CMOS technology achieve transfer rates of 700 Mbpdpin operating from a 3.3-V supply. Worst case measured peak-to-peak clock jitter is 260 ps (63 ps RMS). The layout area occupied by the DLL and the associated clock duty cycle adjuster is 460x800 pni2.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132032306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586209
Chin-Chieh Chao, K. Miyamoto, K. Sakui, Wheling Cheng, B. Wooley
This paper describes an approach to multi-chip module packaging in which a silicon wafer containing active circuits is used as the substrate. Custom interface circuits have been designed for the chip-to-substrate boundary, and series regulation is used to stabilize the power supply for the VLSI chips. In an experimental prototype, a chip-to-chip delay of 7.9 nsec has been achieved, while the supply noise has been reduced by more than a factor of four.
{"title":"An Active Substrate Mcm System","authors":"Chin-Chieh Chao, K. Miyamoto, K. Sakui, Wheling Cheng, B. Wooley","doi":"10.1109/VLSIC.1994.586209","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586209","url":null,"abstract":"This paper describes an approach to multi-chip module packaging in which a silicon wafer containing active circuits is used as the substrate. Custom interface circuits have been designed for the chip-to-substrate boundary, and series regulation is used to stabilize the power supply for the VLSI chips. In an experimental prototype, a chip-to-chip delay of 7.9 nsec has been achieved, while the supply noise has been reduced by more than a factor of four.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117196707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586237
S. Sakiyama, S. Dosho, M. Maruyama, G. Hayashi, S. Inagaki, T. Moriiwa, M. Matsushita, K. Mochizuki, S. Ito
This piper clescrihes rtri overxinipling cinnlog-io-digitctl converter (ADC) suiirible for PCM codecs. Non-linear 5-level quctrttiier is iiiipleiiwiied to the itoise-s/iaping modulator. This ADC cun sciti.$fi the specifications of CCITT G. 712. in .siii/e of using ,firs[ order delta-siRma irioddrttor rinc/'reniiie.s low xwer opemfiori. This clrip is fdJriccitcd in O.t+iii dou/i/e-po/y (im/ dr,uL/e-rnetci[ CMOS lirocess orid occupies clrip urefi of 1Snim2. The ruri.riinuni power consurnpiion is 12.8m W with u single +3Vporver supply iwludirig DAC ciml TONE genercttor. INTHODUCTION Oversampling ADCs and DACs usin second order delta-sigma modulatorsl) or interpolation modulators8 have been developed for applying PCM codecs along with the progress of VLSI technology. However. the second order delta-sigma modulator requires sever specifications",, for SCF circuits such as high low-frequency open-loop voltage gain over 70dB for each operational amplifiers, small settling error lower than O.S%, and small relative enor of capacitors less than 0.2%. Hence it is difficult to realize operational amplifiers satisfying these severe specifications with low power consumption. The interpolation modulator needs the local DAC having 7b equivalent precision and it causes large area of analog circuits compared with other oversampling techniques. Thus we have proposed a new conversion scheme of ADC suitable for PCM codecs with paying attention to the SNR specifications defined as CCITT G.7 12. As a result, it can satisfy the needed SNR by introducing the non-linear S-level quantizer, in spite of using the first order delta-sigma modulator.
{"title":"An Oversampling Adc With Non-linear Quantizer For Pcm-codec","authors":"S. Sakiyama, S. Dosho, M. Maruyama, G. Hayashi, S. Inagaki, T. Moriiwa, M. Matsushita, K. Mochizuki, S. Ito","doi":"10.1109/VLSIC.1994.586237","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586237","url":null,"abstract":"This piper clescrihes rtri overxinipling cinnlog-io-digitctl converter (ADC) suiirible for PCM codecs. Non-linear 5-level quctrttiier is iiiipleiiwiied to the itoise-s/iaping modulator. This ADC cun sciti.$fi the specifications of CCITT G. 712. in .siii/e of using ,firs[ order delta-siRma irioddrttor rinc/'reniiie.s low xwer opemfiori. This clrip is fdJriccitcd in O.t+iii dou/i/e-po/y (im/ dr,uL/e-rnetci[ CMOS lirocess orid occupies clrip urefi of 1Snim2. The ruri.riinuni power consurnpiion is 12.8m W with u single +3Vporver supply iwludirig DAC ciml TONE genercttor. INTHODUCTION Oversampling ADCs and DACs usin second order delta-sigma modulatorsl) or interpolation modulators8 have been developed for applying PCM codecs along with the progress of VLSI technology. However. the second order delta-sigma modulator requires sever specifications\",, for SCF circuits such as high low-frequency open-loop voltage gain over 70dB for each operational amplifiers, small settling error lower than O.S%, and small relative enor of capacitors less than 0.2%. Hence it is difficult to realize operational amplifiers satisfying these severe specifications with low power consumption. The interpolation modulator needs the local DAC having 7b equivalent precision and it causes large area of analog circuits compared with other oversampling techniques. Thus we have proposed a new conversion scheme of ADC suitable for PCM codecs with paying attention to the SNR specifications defined as CCITT G.7 12. As a result, it can satisfy the needed SNR by introducing the non-linear S-level quantizer, in spite of using the first order delta-sigma modulator.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126411193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586232
H. Kimura, S. Miyazawa, R. Horita, K. Hase, K. Watanabe, T. Hirooka, T. Nara
{"title":"A 3.3v 36 Mbps Single-chip Data Channel Processor With Wide Programmable Range Filter For Disk Drives","authors":"H. Kimura, S. Miyazawa, R. Horita, K. Hase, K. Watanabe, T. Hirooka, T. Nara","doi":"10.1109/VLSIC.1994.586232","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586232","url":null,"abstract":"","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"348 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120864517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586197
T. Kawamura, M. Suzuki, H. Ichino
An extremely low-power bipolar current-mode 1/0 circuit is proposed. This 1/0 circuit can achieve a 2.5 Gbit/s transmission with a 50 R impedance matching at both terminals and with a power dissipation one fifth that of an ECL I/O.
{"title":"An Extremely Low-Power Bipolar Current-Mode I/O Circuit for Multi-Gbit/s Interfaces","authors":"T. Kawamura, M. Suzuki, H. Ichino","doi":"10.1109/VLSIC.1994.586197","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586197","url":null,"abstract":"An extremely low-power bipolar current-mode 1/0 circuit is proposed. This 1/0 circuit can achieve a 2.5 Gbit/s transmission with a 50 R impedance matching at both terminals and with a power dissipation one fifth that of an ECL I/O.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122665759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586230
D. Stark, H. Watanabe, T. Furuyama
Series connected storage cells provide greater storage density for a given DRAM technology. We introduce several new features to exploit this advantage: an extra wordline to allow read and restore of the serial bits in the same order, a shift register row decoder with variable size redundancy, and a sense amp exchange configuration to ameliorate inter-bitline noise, We have designed and fabricated an experimental 32M DRAM that shows these ideas are feasible.
{"title":"An Experimental Cascade Cell Dynamic Memory","authors":"D. Stark, H. Watanabe, T. Furuyama","doi":"10.1109/VLSIC.1994.586230","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586230","url":null,"abstract":"Series connected storage cells provide greater storage density for a given DRAM technology. We introduce several new features to exploit this advantage: an extra wordline to allow read and restore of the serial bits in the same order, a shift register row decoder with variable size redundancy, and a sense amp exchange configuration to ameliorate inter-bitline noise, We have designed and fabricated an experimental 32M DRAM that shows these ideas are feasible.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128758456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586167
N. Kumazawa, N. Fukushima, T. Fujiwara, K. Motoyama, N. Akui
{"title":"A cmos 3v 24mw 20msps 10bit A/d converter with Self Calibration Unit","authors":"N. Kumazawa, N. Fukushima, T. Fujiwara, K. Motoyama, N. Akui","doi":"10.1109/VLSIC.1994.586167","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586167","url":null,"abstract":"","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125243211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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