Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586169
H. Hasegawa, M. Yotsuyanagi, M. Yamaguchi, K. Sone
{"title":"A 1.5v Video-Speed Current-Mode Current-Tree A/d Converter","authors":"H. Hasegawa, M. Yotsuyanagi, M. Yamaguchi, K. Sone","doi":"10.1109/VLSIC.1994.586169","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586169","url":null,"abstract":"","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116832246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586216
Y. Miyawaki, T. Nakayama, M. Mihara, S. Kawai, M. Ohkawa, N. Ajika, M. Hatanaka, Y. Terada, T. Yoshihara
Introduction Recent development of hand-held digital equipment demands a low voltage operation non-volatile memory. Already a 3.3-V operation 16-Mb flash memories have been reported [1][2], and word line boost schemes have been shown to be very effective in lowering operational voltage[2][3]. Further Vcc reduction by word line boosting, however, increases power consumption and access time. Lowering the threshold voltage in the erased state becomes inevitable, which induces an over-erasure problem if the fluctuation of memory cell characteristics is large. If the detection of over-erased bits can be performed, the threshold voltage distribution can be tightened by an over-erasure recovery procedure such as bit-by-bit "1" programming. This paper describes a source line bias scheme and the supply voltage shifting of a sense amplifier for over-erased bit detection without a negative voltage and chip area penalty.
{"title":"An Over-Erasure Detection Technique for Tightening Vth Distribution for Low Voltage Operation Nor Type Flash Memory","authors":"Y. Miyawaki, T. Nakayama, M. Mihara, S. Kawai, M. Ohkawa, N. Ajika, M. Hatanaka, Y. Terada, T. Yoshihara","doi":"10.1109/VLSIC.1994.586216","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586216","url":null,"abstract":"Introduction Recent development of hand-held digital equipment demands a low voltage operation non-volatile memory. Already a 3.3-V operation 16-Mb flash memories have been reported [1][2], and word line boost schemes have been shown to be very effective in lowering operational voltage[2][3]. Further Vcc reduction by word line boosting, however, increases power consumption and access time. Lowering the threshold voltage in the erased state becomes inevitable, which induces an over-erasure problem if the fluctuation of memory cell characteristics is large. If the detection of over-erased bits can be performed, the threshold voltage distribution can be tightened by an over-erasure recovery procedure such as bit-by-bit \"1\" programming. This paper describes a source line bias scheme and the supply voltage shifting of a sense amplifier for over-erased bit detection without a negative voltage and chip area penalty.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121679634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586245
K. O'Connor
This paper proposes a new SRAM cell topology for full CMOS applications that relaxes interconnect density, lowers word line capacitance and reduces cell data access delays. This is achieved by replacing the conventional differential bit lines and access transmission gates with a single ended sensing scheme via the cell ground bus. It is ideally suited for multiported embedded ASIC memories where logic based technologies limit exotic approaches. Read word line loading is reduced by 1/2 and traditional read bit lines are. eliminated, relaxing the wiring pitch while reducing inter-signal cross coupling.
{"title":"The Source Sensed Sram (S3) Cell","authors":"K. O'Connor","doi":"10.1109/VLSIC.1994.586245","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586245","url":null,"abstract":"This paper proposes a new SRAM cell topology for full CMOS applications that relaxes interconnect density, lowers word line capacitance and reduces cell data access delays. This is achieved by replacing the conventional differential bit lines and access transmission gates with a single ended sensing scheme via the cell ground bus. It is ideally suited for multiported embedded ASIC memories where logic based technologies limit exotic approaches. Read word line loading is reduced by 1/2 and traditional read bit lines are. eliminated, relaxing the wiring pitch while reducing inter-signal cross coupling.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131115196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586227
Do-Chan Choi, Young-Rae Kim, Gi-Won Cha, Jae-Hyeong Lee, Sang-Bo Lee, Keum-Yong Kim, E. Haq, Dong-Soo Jun, Kyupil Lee, Sooin Cho, Jong-Woo Park, Hyung-Kyu Lim
with wide operating voltage range of 1.8~ to 3.6~ for battery based portable applications. Low power during data retention is obtained with Vcc and temperature variable self refresh which is programmable after packaging using electrical fuses. High performance is achieved at low voltage with dual VPPs for well bias and on-chip high voltage power supply, dual threshold voltages for NMOS and voltage variable sensing control. The 16M has a measured RAS access time of 58ns at 1.8~ and 83°C. This paper describes a I6M DRAM
具有宽工作电压范围1.8~ 3.6~为电池为基础的便携式应用。在数据保留期间，通过Vcc和温度可变自刷新获得低功耗，该自刷新在使用保险丝包装后可编程。在低电压下实现高性能，双电压点用于井偏置和片上高压电源，双阈值电压用于NMOS和电压可变传感控制。16M在1.8~ 83°C下的RAS存取时间为58ns。本文介绍了一种I6M DRAM
{"title":"Battery Operated 16m Dram With Post Package Programmable And Variable Self Refresh","authors":"Do-Chan Choi, Young-Rae Kim, Gi-Won Cha, Jae-Hyeong Lee, Sang-Bo Lee, Keum-Yong Kim, E. Haq, Dong-Soo Jun, Kyupil Lee, Sooin Cho, Jong-Woo Park, Hyung-Kyu Lim","doi":"10.1109/VLSIC.1994.586227","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586227","url":null,"abstract":"with wide operating voltage range of 1.8~ to 3.6~ for battery based portable applications. Low power during data retention is obtained with Vcc and temperature variable self refresh which is programmable after packaging using electrical fuses. High performance is achieved at low voltage with dual VPPs for well bias and on-chip high voltage power supply, dual threshold voltages for NMOS and voltage variable sensing control. The 16M has a measured RAS access time of 58ns at 1.8~ and 83°C. This paper describes a I6M DRAM","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"os-1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127846411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586196
M. Hiraki, H. Kojima, H. Misawa, T. Akazawa, Y. Hatano
A reduced-swing internal bus scheme is proposed for achieving ultralow-power LSI's. The proposed data-dependent logic swing bus (DDL bus) uses charge sharing between bus wires and an additional bus wire to reduce its voltage swing. With this technique, the power dissipation of the proposed bus is reduced to 1/16 that of a conventional bus when used for a 16-b-wide bus. In addition, a dual-reference sense-amplifying receiver (DRSA receiver) has been developed to convert a reduced-swing bus signal to a CMOS-level signal without loss of noise margin or speed. Experimental circuits fabricated using 0.5-μm CMOS process verify the low-power operation of the proposed bus at an operating frequency of 40 MHz with a supply voltage of 3.3 V
{"title":"Data-Dependent Logic Swing Internal Bus Architecture for Ultra-Low-Power Lsis","authors":"M. Hiraki, H. Kojima, H. Misawa, T. Akazawa, Y. Hatano","doi":"10.1109/VLSIC.1994.586196","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586196","url":null,"abstract":"A reduced-swing internal bus scheme is proposed for achieving ultralow-power LSI's. The proposed data-dependent logic swing bus (DDL bus) uses charge sharing between bus wires and an additional bus wire to reduce its voltage swing. With this technique, the power dissipation of the proposed bus is reduced to 1/16 that of a conventional bus when used for a 16-b-wide bus. In addition, a dual-reference sense-amplifying receiver (DRSA receiver) has been developed to convert a reduced-swing bus signal to a CMOS-level signal without loss of noise margin or speed. Experimental circuits fabricated using 0.5-μm CMOS process verify the low-power operation of the proposed bus at an operating frequency of 40 MHz with a supply voltage of 3.3 V","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127893867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586194
A. Kramer, John, Denker, S. Avery, A. Dickinson, Thomas, R., Wik
Low-energy computing is an idea whose time has come. Applications include the smallest systems (where battery size and weight are crucial) as well as the largest systems (where power supply and cooling are crucial). To turn an F E T on or off requires transferring a certain amount of energy (the switching energy). The energy dissipated during this transfer need not be related to the energy transferred, but in ordinary CMOS logic circuits both quantities are on the order of $CV,2,, where C is the capacitance of a typical node, and V d d is the operating voltage. This level of dissipation is unavoidable if a l l the needed electrons are extracted from the V d d terminal of the power supply and ret,urned to the ground terminal. The essential idea of adiabatic computing is to construct circuits that allow each needed electron to be extracted at the lowest feasible voltage and returned at the highest feasible voltage. Ramp-like power/clock signals are required. Obviously it is advantageous to reduce c and V d d , but there are limits; in any case for the purposes of this paper we take such reductions for granted and show how dissipation can be further reduced at any particular V d d and c. The theoretical limit on dissipation is 0 for logically reversible operations, and kT for logically irreversible operations (1). Since kT is six or seven orders of magnitude below present-day values of $CV2d, there is considerable room for compromise. The logic family considered here, which we call 2N-2N2D, emphasizes overall system feasibility and throughput, while providing energy savings of “only” half an order of magnitude or so. Unlike previous diode-based energy recovery schemes (2; 3; 4) our major design goal was to present a nearly constant, data-independent capacitive load to the clock even though it makes 2N-2N2D about twice as complex as 1T1D (4). Constant load is vital, permitting operation from “stored energy” clock drivers. We have detailed simulations of such a clock driving a 6000-bit 2N-2N2D shift register ring, recovering over 75% of the transferred energy.
低能耗计算的时代已经到来。应用包括最小的系统(其中电池的尺寸和重量至关重要)以及最大的系统(其中电源和冷却是至关重要的)。要打开或关闭一个fe - T需要转移一定的能量(开关能量)。传递过程中耗散的能量不必与传递的能量相关，但在普通CMOS逻辑电路中，这两个量都在$CV,2，的数量级上，其中C为典型节点的电容，vdd为工作电压。如果所有需要的电子都从电源的V / d端子中提取出来，然后转到接地端子，这种程度的耗散是不可避免的。绝热计算的基本思想是构建电路，使每个需要的电子在最低可行电压下被提取，并在最高可行电压下返回。需要坡道式电源/时钟信号。显然减小c和vdd是有利的，但也有限制;在任何情况下，为了本文的目的，我们都认为这种减少是理所当然的，并展示了如何在任何特定的V d d和c下进一步减少耗散。对于逻辑可逆操作，耗散的理论极限为0，对于逻辑不可逆操作，耗散的理论极限为kT(1)。由于kT比当前的$CV2d值低六到七个数量级，因此有相当大的妥协空间。这里考虑的逻辑家族，我们称之为2N-2N2D，强调整体系统可行性和吞吐量，同时提供“仅”半个数量级左右的节能。不同于以往基于二极管的能量回收方案(2;3;4)我们的主要设计目标是为时钟提供一个几乎恒定的、与数据无关的容性负载，尽管它使2N-2N2D的复杂性大约是1T1D的两倍(4)。恒定负载至关重要，允许从“存储能量”时钟驱动器操作。我们详细模拟了这样一个时钟驱动6000位2N-2N2D移位寄存器环，恢复超过75%的转移能量。
{"title":"Adiabatic Computing with the 2n-2n2d Logic Family","authors":"A. Kramer, John, Denker, S. Avery, A. Dickinson, Thomas, R., Wik","doi":"10.1109/VLSIC.1994.586194","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586194","url":null,"abstract":"Low-energy computing is an idea whose time has come. Applications include the smallest systems (where battery size and weight are crucial) as well as the largest systems (where power supply and cooling are crucial). To turn an F E T on or off requires transferring a certain amount of energy (the switching energy). The energy dissipated during this transfer need not be related to the energy transferred, but in ordinary CMOS logic circuits both quantities are on the order of $CV,2,, where C is the capacitance of a typical node, and V d d is the operating voltage. This level of dissipation is unavoidable if a l l the needed electrons are extracted from the V d d terminal of the power supply and ret,urned to the ground terminal. The essential idea of adiabatic computing is to construct circuits that allow each needed electron to be extracted at the lowest feasible voltage and returned at the highest feasible voltage. Ramp-like power/clock signals are required. Obviously it is advantageous to reduce c and V d d , but there are limits; in any case for the purposes of this paper we take such reductions for granted and show how dissipation can be further reduced at any particular V d d and c. The theoretical limit on dissipation is 0 for logically reversible operations, and kT for logically irreversible operations (1). Since kT is six or seven orders of magnitude below present-day values of $CV2d, there is considerable room for compromise. The logic family considered here, which we call 2N-2N2D, emphasizes overall system feasibility and throughput, while providing energy savings of “only” half an order of magnitude or so. Unlike previous diode-based energy recovery schemes (2; 3; 4) our major design goal was to present a nearly constant, data-independent capacitive load to the clock even though it makes 2N-2N2D about twice as complex as 1T1D (4). Constant load is vital, permitting operation from “stored energy” clock drivers. We have detailed simulations of such a clock driving a 6000-bit 2N-2N2D shift register ring, recovering over 75% of the transferred energy.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116386997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586220
M. Motomura, T. Inoue, H. Yamada, A. Konagaya
This paper presents a new data cache design, cache-processor coupling, which tightly binds an on-chip data cache with a microprocessor. Parallel architectures and high-speed circuit techniques are developed for speeding address handling process associated with accessing the data cache. The address handling time has been reduced by 51 % by these architectures and circuit techniques. On the other hand, newly proposed instructions increase data cache bandwidth by eight times. Excessive power consumption due to the wide-bandwidth data transfer is carefully avoided by newly developed circuit techniques, which reduce dissipation power per bit to 1/26. Simulation study of the proposed architecture and circuit techniques yields a 1.8 ns delay each for address handling, cache access, and register access for a 16 kilobyte direct mapped cache with a 0.4 μm CMOS design rule
{"title":"Cache-Processor Coupling: A Fast & Wide On-Chip Data Cache Design","authors":"M. Motomura, T. Inoue, H. Yamada, A. Konagaya","doi":"10.1109/VLSIC.1994.586220","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586220","url":null,"abstract":"This paper presents a new data cache design, cache-processor coupling, which tightly binds an on-chip data cache with a microprocessor. Parallel architectures and high-speed circuit techniques are developed for speeding address handling process associated with accessing the data cache. The address handling time has been reduced by 51 % by these architectures and circuit techniques. On the other hand, newly proposed instructions increase data cache bandwidth by eight times. Excessive power consumption due to the wide-bandwidth data transfer is carefully avoided by newly developed circuit techniques, which reduce dissipation power per bit to 1/26. Simulation study of the proposed architecture and circuit techniques yields a 1.8 ns delay each for address handling, cache access, and register access for a 16 kilobyte direct mapped cache with a 0.4 μm CMOS design rule","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116548770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586222
S. Hino, M. Togashi, K. Yamasaki
The LSIs demonstrated in this paper fit on a switching fabric using chip-tq-cltip optical interconnections and have IO-Gbivs serial input and output pons facilitating the easy layout of optically interfaced switching element modules. A test switching module made up of these LSIs has been successfully operated at 10.2 Gbit/s without bit errors.
{"title":"Asynchronous Transfer Mode Switching Lsis With 10 Gbit/s Serial Inputs And Outputs","authors":"S. Hino, M. Togashi, K. Yamasaki","doi":"10.1109/VLSIC.1994.586222","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586222","url":null,"abstract":"The LSIs demonstrated in this paper fit on a switching fabric using chip-tq-cltip optical interconnections and have IO-Gbivs serial input and output pons facilitating the easy layout of optically interfaced switching element modules. A test switching module made up of these LSIs has been successfully operated at 10.2 Gbit/s without bit errors.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122456512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586206
T. Kawahara, M. Horiguchi, J. Etoh, T. Sekiguchi, M. Aoki
{"title":"Low Power Chip Interconnection by Dynamic Termination","authors":"T. Kawahara, M. Horiguchi, J. Etoh, T. Sekiguchi, M. Aoki","doi":"10.1109/VLSIC.1994.586206","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586206","url":null,"abstract":"","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124083342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586252
M. Rofougaran, A. Rofougaran, C. Olgaard, A. Abidi
The power amplifier module constitutes the largest current drain on a wireless transceiver during transmit mode. In future cellular networks for digital wireless transceivers, the base station will adaptively regulate the transmitted p o i w leeels of each transceiver to enable the largest possible number ofusers to share a wireless channel. This requires a high-efficiency power amplifier with a digitally selectable output level spanning a wide range. The power amplifier reported here is intended for use in an all-CMOS frequency-hopped spreadspectrum transceiver operating in the 902-928 MHz band. It delivers a controllable power between 20-pW and 20. " from a 3-V supply to the antenna.
{"title":"A 900 Mhz Cmos Rf Power Amplifier With Programmable Output","authors":"M. Rofougaran, A. Rofougaran, C. Olgaard, A. Abidi","doi":"10.1109/VLSIC.1994.586252","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586252","url":null,"abstract":"The power amplifier module constitutes the largest current drain on a wireless transceiver during transmit mode. In future cellular networks for digital wireless transceivers, the base station will adaptively regulate the transmitted p o i w leeels of each transceiver to enable the largest possible number ofusers to share a wireless channel. This requires a high-efficiency power amplifier with a digitally selectable output level spanning a wide range. The power amplifier reported here is intended for use in an all-CMOS frequency-hopped spreadspectrum transceiver operating in the 902-928 MHz band. It delivers a controllable power between 20-pW and 20. \" from a 3-V supply to the antenna.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"504 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123069051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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