Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586193
H. Kojima, Satoshi Tanaka, K. Sasaki
We propose a half-swing clocking scheme that allows us to reduce power consumption of clocking circuitry by as much as 75%, because all the clock signal swings are reduced to half of the LSI supply voltage. The new clocking scheme causes quite small speed degradation, because the random logic circuits in the critical path are still supplied by the full supply voltage. We also propose a clock driver which supplies half-swing clock and generates half V/sub DD/ by itself. We confirmed that the half-swing clocking scheme provided 67% power saving in a test chip fabricated with 0.5 /spl mu/m CMOS technology, ideally 75%, in the clocking circuitry, and that the degradation in speed was only 0.5 ns by circuit simulation. The key to the proposed clocking scheme is the concept that the voltage swing is reduced only for clocking circuitry, but is retained for all other circuits in the chip. This results in significant power reduction with minimal speed degradation. >
{"title":"Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry","authors":"H. Kojima, Satoshi Tanaka, K. Sasaki","doi":"10.1109/VLSIC.1994.586193","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586193","url":null,"abstract":"We propose a half-swing clocking scheme that allows us to reduce power consumption of clocking circuitry by as much as 75%, because all the clock signal swings are reduced to half of the LSI supply voltage. The new clocking scheme causes quite small speed degradation, because the random logic circuits in the critical path are still supplied by the full supply voltage. We also propose a clock driver which supplies half-swing clock and generates half V/sub DD/ by itself. We confirmed that the half-swing clocking scheme provided 67% power saving in a test chip fabricated with 0.5 /spl mu/m CMOS technology, ideally 75%, in the clocking circuitry, and that the degradation in speed was only 0.5 ns by circuit simulation. The key to the proposed clocking scheme is the concept that the voltage swing is reduced only for clocking circuitry, but is retained for all other circuits in the chip. This results in significant power reduction with minimal speed degradation. >","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116683667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586240
H. Nambu, K. Kanetani, Y. Idei, T. Masuda, K. Higeta, M. Ohayashi, M. Usami, K. Yamaguchi, T. Kikuchi, T. Ikeda, K. Ohhata, T. Kusunoki, N. Homma
An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-μm 2 memory cells has been developed using 0.3-μm BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71 % and 58 % of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAM's, witch have been used as cache and control storages in mainframe computers
{"title":"A 0.65ns, 72kb Ecl-cmos Ram Macro For A 1mb Sram","authors":"H. Nambu, K. Kanetani, Y. Idei, T. Masuda, K. Higeta, M. Ohayashi, M. Usami, K. Yamaguchi, T. Kikuchi, T. Ikeda, K. Ohhata, T. Kusunoki, N. Homma","doi":"10.1109/VLSIC.1994.586240","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586240","url":null,"abstract":"An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-μm 2 memory cells has been developed using 0.3-μm BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71 % and 58 % of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAM's, witch have been used as cache and control storages in mainframe computers","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128454244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586233
Alex Gusinov
achieve 0.03% & 0.03” Differential Gain & Phase performance on a single 3V supply. The op-amp was fabricated on a 4GHz, Dielectrically Isolated (DI), Complementary Bipolar Process. The op-amp employes a fully differential NPN & PNP input stage that can swing 300mV beyond either supply rail. A novel output stage is used to achieve Rail to Rail performance with common emitter output devices having Rsat < 10R The circuit has biasing that compensates for thermal self-heating and early-voltage effects of transistors in the absence of degeneration. PSRR is maintained at 64dB down to 2V single supply operation. A 40MHz operational amplifier (op-amp) has been built to
{"title":"2 To 12v, Single Supply, 40mhz, Video Operational Amplifier With Rail To Rail Input And Output Operation","authors":"Alex Gusinov","doi":"10.1109/VLSIC.1994.586233","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586233","url":null,"abstract":"achieve 0.03% & 0.03” Differential Gain & Phase performance on a single 3V supply. The op-amp was fabricated on a 4GHz, Dielectrically Isolated (DI), Complementary Bipolar Process. The op-amp employes a fully differential NPN & PNP input stage that can swing 300mV beyond either supply rail. A novel output stage is used to achieve Rail to Rail performance with common emitter output devices having Rsat < 10R The circuit has biasing that compensates for thermal self-heating and early-voltage effects of transistors in the absence of degeneration. PSRR is maintained at 64dB down to 2V single supply operation. A 40MHz operational amplifier (op-amp) has been built to","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131985783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586198
R. Landers, S. Mahant-Shetti, C. Lemonds
This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to create any 2 input and some 3 input functions in one basecell. Internal fanout, rather than typical output load, defines the size of driver and multiplexer transistors, which can be independently tailored for the desired speed/area/power target. This basecell, which is well suited for implementing datapath elements, has been used to create a 16 × 16-b multiplier operating at 50 MHz in 314 500 μm 2 in 0.6 μm technology
{"title":"Multiplexer-Based Architecture for High-Density, Low-Power Gate Arrays","authors":"R. Landers, S. Mahant-Shetti, C. Lemonds","doi":"10.1109/VLSIC.1994.586198","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586198","url":null,"abstract":"This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to create any 2 input and some 3 input functions in one basecell. Internal fanout, rather than typical output load, defines the size of driver and multiplexer transistors, which can be independently tailored for the desired speed/area/power target. This basecell, which is well suited for implementing datapath elements, has been used to create a 16 × 16-b multiplier operating at 50 MHz in 314 500 μm 2 in 0.6 μm technology","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122525281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586170
R. T. Hinman, F. Martin, Schlecht
Recovered Energy Logic is a low power logic topology powered and clocked by a single ac supply volt- age. This paper describes the operation of the circuit and presents measurements showing that this approach can re- duce dissipation by a factor of 5 to 17 over conventional CMOS logic.
{"title":"Power Dissipation Measurements on Recovered Energy Logic","authors":"R. T. Hinman, F. Martin, Schlecht","doi":"10.1109/VLSIC.1994.586170","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586170","url":null,"abstract":"Recovered Energy Logic is a low power logic topology powered and clocked by a single ac supply volt- age. This paper describes the operation of the circuit and presents measurements showing that this approach can re- duce dissipation by a factor of 5 to 17 over conventional CMOS logic.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121471000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586160
Ook Kim, Jungwook Yang, Suk-ki Kim, Wonchan Kim
This paper presents a digital self compensation method for video-rate D/A converters(DAC's). In this method, the compensation operation is isolated from the high speed operation of the current switch. Therefore, the errors of each element of the device can be corrected without interrupting the device operation. This method was implemented using standard 0.8 pnt CMOS technology. The measured Integral Nonlinearity of the IO-bit CMOS DAC decreased to 0.22LSB.
{"title":"A Digital Self Compensation Circuit for High Speed D/a Converters","authors":"Ook Kim, Jungwook Yang, Suk-ki Kim, Wonchan Kim","doi":"10.1109/VLSIC.1994.586160","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586160","url":null,"abstract":"This paper presents a digital self compensation method for video-rate D/A converters(DAC's). In this method, the compensation operation is isolated from the high speed operation of the current switch. Therefore, the errors of each element of the device can be corrected without interrupting the device operation. This method was implemented using standard 0.8 pnt CMOS technology. The measured Integral Nonlinearity of the IO-bit CMOS DAC decreased to 0.22LSB.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115114360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586242
A. Suzuki, H. Kato
{"title":"A Novel Synchronous Timing Control For 200mhz Mega-bits BiCMOS SRAM at 2.5V Operation","authors":"A. Suzuki, H. Kato","doi":"10.1109/VLSIC.1994.586242","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586242","url":null,"abstract":"","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126022127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586229
M. Tsukude, M. Hirose, S. Tomishima, T. Tsuruda, T. Yamagata, K. Arimoto, K. Fujishima
LIntroduction Recently, low power DRAMs[l-3] are strongly needed for handheld machines. To reduce the data-retention current, the DRAMs should have 1)long data-retention time, 2)low active current for a refresh operation, and 3)low stand-by current. This paper describes new current saving techniques for the high-density DRAMs. The combination of the Voltage-DownConvertor (VDC) and Boosted-SenseGround (BSG) scheme[4] achieves the low active current b reducing
{"title":"Automatic Voltage-swing Reduction (avr) Scheme For Ultra Low Power Drams","authors":"M. Tsukude, M. Hirose, S. Tomishima, T. Tsuruda, T. Yamagata, K. Arimoto, K. Fujishima","doi":"10.1109/VLSIC.1994.586229","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586229","url":null,"abstract":"LIntroduction Recently, low power DRAMs[l-3] are strongly needed for handheld machines. To reduce the data-retention current, the DRAMs should have 1)long data-retention time, 2)low active current for a refresh operation, and 3)low stand-by current. This paper describes new current saving techniques for the high-density DRAMs. The combination of the Voltage-DownConvertor (VDC) and Boosted-SenseGround (BSG) scheme[4] achieves the low active current b reducing","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121582481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586199
J. Lundberg, E. Nuckolls
Introduction As microprocessor frequencies have increased, it has become necessary to de-skew internal and external clocks. It is also desirable to run internal docks faster than system clock rates. Clock generation via an analog PLL has previously performed this function(l), but as low-power applications for microprocessors proliferate, it has become necessary to use power management techniques. One such technique entails using a state wherein the on-chip clocks are quiescent, shutting down the microprocessor while statically maintaining machine states. Analog PLLs are not well suited to this since it is preferable that the PLL consume no power in this state. Furthermore, the frequency at which this state can be used is limited by how fast a PLL can stop and start (i.e., re-acquire phase lock). Slow PLL lock and stop times reduce the usage of this state and result in increased power consumption. This paper describes an alldigital PLL (ADPLL) with 50cycle lock time and lcycle shutdown to zero power. The ADPLL has process/temperature/voltage-independent gain for increased stability and is immune to inputclock jitter. At the ADPLL core is a digitallycontrolled oscillator (DCO) that runs at 4 times the reference frequency and has 16 bits of binarily-weighted control. The frequency and phase of the DCO are varied by arithmetically incrementing or decrementing the 16 control bits. The ADPLL achieves a skew-to-reference of less than 250ps and a peak-to-peak jitter under 125ps.
{"title":"A 15- 150mhz, All-Digital Phase-Locked Loop with 50-Cycle Lock Time for High-Performance Low-Power Microprocessors","authors":"J. Lundberg, E. Nuckolls","doi":"10.1109/VLSIC.1994.586199","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586199","url":null,"abstract":"Introduction As microprocessor frequencies have increased, it has become necessary to de-skew internal and external clocks. It is also desirable to run internal docks faster than system clock rates. Clock generation via an analog PLL has previously performed this function(l), but as low-power applications for microprocessors proliferate, it has become necessary to use power management techniques. One such technique entails using a state wherein the on-chip clocks are quiescent, shutting down the microprocessor while statically maintaining machine states. Analog PLLs are not well suited to this since it is preferable that the PLL consume no power in this state. Furthermore, the frequency at which this state can be used is limited by how fast a PLL can stop and start (i.e., re-acquire phase lock). Slow PLL lock and stop times reduce the usage of this state and result in increased power consumption. This paper describes an alldigital PLL (ADPLL) with 50cycle lock time and lcycle shutdown to zero power. The ADPLL has process/temperature/voltage-independent gain for increased stability and is immune to inputclock jitter. At the ADPLL core is a digitallycontrolled oscillator (DCO) that runs at 4 times the reference frequency and has 16 bits of binarily-weighted control. The frequency and phase of the DCO are varied by arithmetically incrementing or decrementing the 16 control bits. The ADPLL achieves a skew-to-reference of less than 250ps and a peak-to-peak jitter under 125ps.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115091432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586251
B. Razavi, Kwing F. Lee, R. Yan, R. Swartz
The demand for high-speed, low-power communication circuits has dramatically grown over the past few years. Potential markets from powerful personal communicators to wireless ATM systems have stimulated great effort in reducing the supply voltage and power dissipation of gigahertz circuits. In this respect, deep submicron CMOS technologies have become contenders to 111-V and silicon bipolar devices because they offer the speed, density, and power required for such applications. This paper describes the design of a 3-GHz phase-locked loop (PLL) fabricated in a partially-scaled 0.1-pm bulk CMOS technology [l]. The circuit employs a number of techniques to allow operation from a low supply voltage and overcome the limitations due to device layout rules described below. In order to improve the yield and reduce the turnaround time and cost, the CMOS process used here scales only the channel
{"title":"A 3-ghz 25-mw Cmos Phase-locked Loop","authors":"B. Razavi, Kwing F. Lee, R. Yan, R. Swartz","doi":"10.1109/VLSIC.1994.586251","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586251","url":null,"abstract":"The demand for high-speed, low-power communication circuits has dramatically grown over the past few years. Potential markets from powerful personal communicators to wireless ATM systems have stimulated great effort in reducing the supply voltage and power dissipation of gigahertz circuits. In this respect, deep submicron CMOS technologies have become contenders to 111-V and silicon bipolar devices because they offer the speed, density, and power required for such applications. This paper describes the design of a 3-GHz phase-locked loop (PLL) fabricated in a partially-scaled 0.1-pm bulk CMOS technology [l]. The circuit employs a number of techniques to allow operation from a low supply voltage and overcome the limitations due to device layout rules described below. In order to improve the yield and reduce the turnaround time and cost, the CMOS process used here scales only the channel","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132185431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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