Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586247
K. Ueda, N. Sasaki, H. Sato, S. Kubo, K. Mashiko
I . INTRODUCTION Optical transmission systems require multiplexer and demultiplexer chips as the major ingredients. There have been proposed and realized several architectures for multiplexers and demultiplexers. Such as the shift resister architecture, the interleaved architecture, the series gated architecture, and so on. In general, these previous architectures have aimed at high speed operation rather than low power dissipation. In multiplexers, the series gated architecture is effective in reducing power dissipation because the series gate can implement complex logic with fewer current sources. However, the architecture requires the 3-level for the series gate [l]. Thus it is difficult to lower the supply voltage for multiplexers. Furthermore, the architecture requires larger current to drive the 3-level series gate at high speed. On the other hand, the interleaved architecture is widely used in demultiplexers. In this architecture, conversion from serial to parallel data requires the lst, 2nd and 3rd stage flipflops [2]. This requires a large amount of hardware and therefore consumes much power. In this paper, 8:l multiplexer and 1% demultiplexer chips with low power dissipation are described. The multiplexer chip adopts the modified series gated architecture, while the demultiplexer chip adopts the modified interleaved architecture.
{"title":"3. Ogb/s, 272mw, 8:1 Multiplexer And 4.1gb/s, 388mw, 1:8 Demultiplexer","authors":"K. Ueda, N. Sasaki, H. Sato, S. Kubo, K. Mashiko","doi":"10.1109/VLSIC.1994.586247","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586247","url":null,"abstract":"I . INTRODUCTION Optical transmission systems require multiplexer and demultiplexer chips as the major ingredients. There have been proposed and realized several architectures for multiplexers and demultiplexers. Such as the shift resister architecture, the interleaved architecture, the series gated architecture, and so on. In general, these previous architectures have aimed at high speed operation rather than low power dissipation. In multiplexers, the series gated architecture is effective in reducing power dissipation because the series gate can implement complex logic with fewer current sources. However, the architecture requires the 3-level for the series gate [l]. Thus it is difficult to lower the supply voltage for multiplexers. Furthermore, the architecture requires larger current to drive the 3-level series gate at high speed. On the other hand, the interleaved architecture is widely used in demultiplexers. In this architecture, conversion from serial to parallel data requires the lst, 2nd and 3rd stage flipflops [2]. This requires a large amount of hardware and therefore consumes much power. In this paper, 8:l multiplexer and 1% demultiplexer chips with low power dissipation are described. The multiplexer chip adopts the modified series gated architecture, while the demultiplexer chip adopts the modified interleaved architecture.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124231903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586234
Changhyun Kim, K. Wise
This paper describes a micromachined CMOS probe for multisite stimulation and recording in the central nervous system. The probe uses flexible silicon interconnects to allow the signal processing circuitry to fold at right anglcs to the probe shanks, limiting the implanted profile above thc cortex to llmm while driving any 8 of the 64 sites with 0 to k127p.A f1p.A. An on-chip amplifier allows the neural activity on any selected site to be recorded with an overall gain of 50 and bandwidth from 50Hz to 7kHz. Micropower circuit techniques allow the probe to dissipate 4Op.W in standby from f5V.
{"title":"A 64-site Multiplexed Low-profile Neural Probe With On-chip Cmos Circuitry","authors":"Changhyun Kim, K. Wise","doi":"10.1109/VLSIC.1994.586234","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586234","url":null,"abstract":"This paper describes a micromachined CMOS probe for multisite stimulation and recording in the central nervous system. The probe uses flexible silicon interconnects to allow the signal processing circuitry to fold at right anglcs to the probe shanks, limiting the implanted profile above thc cortex to llmm while driving any 8 of the 64 sites with 0 to k127p.A f1p.A. An on-chip amplifier allows the neural activity on any selected site to be recorded with an overall gain of 50 and bandwidth from 50Hz to 7kHz. Micropower circuit techniques allow the probe to dissipate 4Op.W in standby from f5V.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126776368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586238
P. Hurst, B. Rothenberg
~[n]=s(f~)=Acos[ dnT+Tn)]= A clock generator with a wide range of programmable frequencies and high programming resolution is described. The average frequency is adjusted by introducing jitter that is concentrated at high frequencies through noise shaping. The sin(") yield
{"title":"A Programmable Clock Generator Using Noise Shaping And Its Application In A Switched-capacitor Filter","authors":"P. Hurst, B. Rothenberg","doi":"10.1109/VLSIC.1994.586238","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586238","url":null,"abstract":"~[n]=s(f~)=Acos[ dnT+Tn)]= A clock generator with a wide range of programmable frequencies and high programming resolution is described. The average frequency is adjusted by introducing jitter that is concentrated at high frequencies through noise shaping. The sin(\") yield","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130065162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586198
R. Landers, S. Mahant-Shetti, C. Lemonds
This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to create any 2 input and some 3 input functions in one basecell. Internal fanout, rather than typical output load, defines the size of driver and multiplexer transistors, which can be independently tailored for the desired speed/area/power target. This basecell, which is well suited for implementing datapath elements, has been used to create a 16 × 16-b multiplier operating at 50 MHz in 314 500 μm 2 in 0.6 μm technology
{"title":"Multiplexer-Based Architecture for High-Density, Low-Power Gate Arrays","authors":"R. Landers, S. Mahant-Shetti, C. Lemonds","doi":"10.1109/VLSIC.1994.586198","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586198","url":null,"abstract":"This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to create any 2 input and some 3 input functions in one basecell. Internal fanout, rather than typical output load, defines the size of driver and multiplexer transistors, which can be independently tailored for the desired speed/area/power target. This basecell, which is well suited for implementing datapath elements, has been used to create a 16 × 16-b multiplier operating at 50 MHz in 314 500 μm 2 in 0.6 μm technology","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122525281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586170
R. T. Hinman, F. Martin, Schlecht
Recovered Energy Logic is a low power logic topology powered and clocked by a single ac supply volt- age. This paper describes the operation of the circuit and presents measurements showing that this approach can re- duce dissipation by a factor of 5 to 17 over conventional CMOS logic.
{"title":"Power Dissipation Measurements on Recovered Energy Logic","authors":"R. T. Hinman, F. Martin, Schlecht","doi":"10.1109/VLSIC.1994.586170","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586170","url":null,"abstract":"Recovered Energy Logic is a low power logic topology powered and clocked by a single ac supply volt- age. This paper describes the operation of the circuit and presents measurements showing that this approach can re- duce dissipation by a factor of 5 to 17 over conventional CMOS logic.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121471000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586160
Ook Kim, Jungwook Yang, Suk-ki Kim, Wonchan Kim
This paper presents a digital self compensation method for video-rate D/A converters(DAC's). In this method, the compensation operation is isolated from the high speed operation of the current switch. Therefore, the errors of each element of the device can be corrected without interrupting the device operation. This method was implemented using standard 0.8 pnt CMOS technology. The measured Integral Nonlinearity of the IO-bit CMOS DAC decreased to 0.22LSB.
{"title":"A Digital Self Compensation Circuit for High Speed D/a Converters","authors":"Ook Kim, Jungwook Yang, Suk-ki Kim, Wonchan Kim","doi":"10.1109/VLSIC.1994.586160","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586160","url":null,"abstract":"This paper presents a digital self compensation method for video-rate D/A converters(DAC's). In this method, the compensation operation is isolated from the high speed operation of the current switch. Therefore, the errors of each element of the device can be corrected without interrupting the device operation. This method was implemented using standard 0.8 pnt CMOS technology. The measured Integral Nonlinearity of the IO-bit CMOS DAC decreased to 0.22LSB.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115114360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586242
A. Suzuki, H. Kato
{"title":"A Novel Synchronous Timing Control For 200mhz Mega-bits BiCMOS SRAM at 2.5V Operation","authors":"A. Suzuki, H. Kato","doi":"10.1109/VLSIC.1994.586242","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586242","url":null,"abstract":"","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126022127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586229
M. Tsukude, M. Hirose, S. Tomishima, T. Tsuruda, T. Yamagata, K. Arimoto, K. Fujishima
LIntroduction Recently, low power DRAMs[l-3] are strongly needed for handheld machines. To reduce the data-retention current, the DRAMs should have 1)long data-retention time, 2)low active current for a refresh operation, and 3)low stand-by current. This paper describes new current saving techniques for the high-density DRAMs. The combination of the Voltage-DownConvertor (VDC) and Boosted-SenseGround (BSG) scheme[4] achieves the low active current b reducing
{"title":"Automatic Voltage-swing Reduction (avr) Scheme For Ultra Low Power Drams","authors":"M. Tsukude, M. Hirose, S. Tomishima, T. Tsuruda, T. Yamagata, K. Arimoto, K. Fujishima","doi":"10.1109/VLSIC.1994.586229","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586229","url":null,"abstract":"LIntroduction Recently, low power DRAMs[l-3] are strongly needed for handheld machines. To reduce the data-retention current, the DRAMs should have 1)long data-retention time, 2)low active current for a refresh operation, and 3)low stand-by current. This paper describes new current saving techniques for the high-density DRAMs. The combination of the Voltage-DownConvertor (VDC) and Boosted-SenseGround (BSG) scheme[4] achieves the low active current b reducing","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121582481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586199
J. Lundberg, E. Nuckolls
Introduction As microprocessor frequencies have increased, it has become necessary to de-skew internal and external clocks. It is also desirable to run internal docks faster than system clock rates. Clock generation via an analog PLL has previously performed this function(l), but as low-power applications for microprocessors proliferate, it has become necessary to use power management techniques. One such technique entails using a state wherein the on-chip clocks are quiescent, shutting down the microprocessor while statically maintaining machine states. Analog PLLs are not well suited to this since it is preferable that the PLL consume no power in this state. Furthermore, the frequency at which this state can be used is limited by how fast a PLL can stop and start (i.e., re-acquire phase lock). Slow PLL lock and stop times reduce the usage of this state and result in increased power consumption. This paper describes an alldigital PLL (ADPLL) with 50cycle lock time and lcycle shutdown to zero power. The ADPLL has process/temperature/voltage-independent gain for increased stability and is immune to inputclock jitter. At the ADPLL core is a digitallycontrolled oscillator (DCO) that runs at 4 times the reference frequency and has 16 bits of binarily-weighted control. The frequency and phase of the DCO are varied by arithmetically incrementing or decrementing the 16 control bits. The ADPLL achieves a skew-to-reference of less than 250ps and a peak-to-peak jitter under 125ps.
{"title":"A 15- 150mhz, All-Digital Phase-Locked Loop with 50-Cycle Lock Time for High-Performance Low-Power Microprocessors","authors":"J. Lundberg, E. Nuckolls","doi":"10.1109/VLSIC.1994.586199","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586199","url":null,"abstract":"Introduction As microprocessor frequencies have increased, it has become necessary to de-skew internal and external clocks. It is also desirable to run internal docks faster than system clock rates. Clock generation via an analog PLL has previously performed this function(l), but as low-power applications for microprocessors proliferate, it has become necessary to use power management techniques. One such technique entails using a state wherein the on-chip clocks are quiescent, shutting down the microprocessor while statically maintaining machine states. Analog PLLs are not well suited to this since it is preferable that the PLL consume no power in this state. Furthermore, the frequency at which this state can be used is limited by how fast a PLL can stop and start (i.e., re-acquire phase lock). Slow PLL lock and stop times reduce the usage of this state and result in increased power consumption. This paper describes an alldigital PLL (ADPLL) with 50cycle lock time and lcycle shutdown to zero power. The ADPLL has process/temperature/voltage-independent gain for increased stability and is immune to inputclock jitter. At the ADPLL core is a digitallycontrolled oscillator (DCO) that runs at 4 times the reference frequency and has 16 bits of binarily-weighted control. The frequency and phase of the DCO are varied by arithmetically incrementing or decrementing the 16 control bits. The ADPLL achieves a skew-to-reference of less than 250ps and a peak-to-peak jitter under 125ps.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115091432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586251
B. Razavi, Kwing F. Lee, R. Yan, R. Swartz
The demand for high-speed, low-power communication circuits has dramatically grown over the past few years. Potential markets from powerful personal communicators to wireless ATM systems have stimulated great effort in reducing the supply voltage and power dissipation of gigahertz circuits. In this respect, deep submicron CMOS technologies have become contenders to 111-V and silicon bipolar devices because they offer the speed, density, and power required for such applications. This paper describes the design of a 3-GHz phase-locked loop (PLL) fabricated in a partially-scaled 0.1-pm bulk CMOS technology [l]. The circuit employs a number of techniques to allow operation from a low supply voltage and overcome the limitations due to device layout rules described below. In order to improve the yield and reduce the turnaround time and cost, the CMOS process used here scales only the channel
{"title":"A 3-ghz 25-mw Cmos Phase-locked Loop","authors":"B. Razavi, Kwing F. Lee, R. Yan, R. Swartz","doi":"10.1109/VLSIC.1994.586251","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586251","url":null,"abstract":"The demand for high-speed, low-power communication circuits has dramatically grown over the past few years. Potential markets from powerful personal communicators to wireless ATM systems have stimulated great effort in reducing the supply voltage and power dissipation of gigahertz circuits. In this respect, deep submicron CMOS technologies have become contenders to 111-V and silicon bipolar devices because they offer the speed, density, and power required for such applications. This paper describes the design of a 3-GHz phase-locked loop (PLL) fabricated in a partially-scaled 0.1-pm bulk CMOS technology [l]. The circuit employs a number of techniques to allow operation from a low supply voltage and overcome the limitations due to device layout rules described below. In order to improve the yield and reduce the turnaround time and cost, the CMOS process used here scales only the channel","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132185431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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