Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586200
J. Alvarez, Hector Sanchez, G. Gerosa, C. Hanke, Roger Countryman, S. Thadasina
A 3.3 V Phase-Locked-Loop (PLL) clock synthesizer implemented in 0.5 μm CMOS technology is described. The PLL support internal to external clock frequency ratios of 1, 1.5, 2, 3, and 4 as well as numerous static power down modes for PowerPC microprocessors. The CPU clock lock range spans from 6 to 175 MHz. Lock times below 15 μs, PLL power dissipation below 10 mW as well as phase error and jitter below ±100 ps have been measured. The total area of the PLL is 0.52 mm 2
介绍了一种采用0.5 μm CMOS技术实现的3.3 V锁相环(PLL)时钟合成器。锁相环支持1、1.5、2、3和4的内部到外部时钟频率比，以及PowerPC微处理器的许多静态断电模式。CPU时钟锁定范围从6到175 MHz。锁相时间小于15 μs，锁相功耗小于10 mW，相位误差和抖动小于±100 ps。锁相环的总面积为0.52 mm 2
{"title":"A Wide-Bandwidth Low-Voltage Pll for Powerpc Microprocessors","authors":"J. Alvarez, Hector Sanchez, G. Gerosa, C. Hanke, Roger Countryman, S. Thadasina","doi":"10.1109/VLSIC.1994.586200","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586200","url":null,"abstract":"A 3.3 V Phase-Locked-Loop (PLL) clock synthesizer implemented in 0.5 μm CMOS technology is described. The PLL support internal to external clock frequency ratios of 1, 1.5, 2, 3, and 4 as well as numerous static power down modes for PowerPC microprocessors. The CPU clock lock range spans from 6 to 175 MHz. Lock times below 15 μs, PLL power dissipation below 10 mW as well as phase error and jitter below ±100 ps have been measured. The total area of the PLL is 0.52 mm 2","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126435357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586219
S. Ozaki, Y. Nishimichi, T. Kakiage, H. Yamamoto, M. Sumita, G. Inoue, M. Urano, H. Yamashita, T. Maeda, T. Nishiyama
This paper desci-ibes a lOOMHz embedded RISC microcontroller which adopts a zero-cycle branching scheme. By this scheme, two instructions are executed in a single cycle if one of them is a branch instruction. A self-clocking cache access scheme and a separated local clock generator are adopted to attain high operating frequency.
{"title":"A 100 Mhz Embedded Risc Microcontroller","authors":"S. Ozaki, Y. Nishimichi, T. Kakiage, H. Yamamoto, M. Sumita, G. Inoue, M. Urano, H. Yamashita, T. Maeda, T. Nishiyama","doi":"10.1109/VLSIC.1994.586219","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586219","url":null,"abstract":"This paper desci-ibes a lOOMHz embedded RISC microcontroller which adopts a zero-cycle branching scheme. By this scheme, two instructions are executed in a single cycle if one of them is a branch instruction. A self-clocking cache access scheme and a separated local clock generator are adopted to attain high operating frequency.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123138336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586223
S. Shiratake, D. Takashima, T. Hasegawa, H. Nakano, Y. Oowaki, S. Watanabe, K. Ohuchi, F. Masuoka
Cascade arrangement of DRAM cells, NAND structured DRAM cell, have already been proposed to reduce the cell size[l] and the experimental 256Mbit chip has been fabricated to demonstrate a small chip size[2]. However, realizing IGbit or further, the NAND DRAM faces a crucial array noise problem due to its open bitline (BL) array arrangement which has larger array noise than the folded BL arrangement[3]. The conventional NAND DRAM inevitably adopts the open BL arrangement, because memory cells are placed a t all the intersection between wordlines and bitlines, so all the BL’s receive the cell data when a wordline is activated, accordingly reference BL’s cannot be arranged in the same memory mat. To overcome this problem, we propose a Staggered NAND DRAM array architecture which realizes folded BL scheme in a NAND DRAM.
{"title":"A Staggered Nand Dram Array Architecture For A Gbit Scale Integration","authors":"S. Shiratake, D. Takashima, T. Hasegawa, H. Nakano, Y. Oowaki, S. Watanabe, K. Ohuchi, F. Masuoka","doi":"10.1109/VLSIC.1994.586223","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586223","url":null,"abstract":"Cascade arrangement of DRAM cells, NAND structured DRAM cell, have already been proposed to reduce the cell size[l] and the experimental 256Mbit chip has been fabricated to demonstrate a small chip size[2]. However, realizing IGbit or further, the NAND DRAM faces a crucial array noise problem due to its open bitline (BL) array arrangement which has larger array noise than the folded BL arrangement[3]. The conventional NAND DRAM inevitably adopts the open BL arrangement, because memory cells are placed a t all the intersection between wordlines and bitlines, so all the BL’s receive the cell data when a wordline is activated, accordingly reference BL’s cannot be arranged in the same memory mat. To overcome this problem, we propose a Staggered NAND DRAM array architecture which realizes folded BL scheme in a NAND DRAM.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125058097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586153
M. Borota, K. Johnson, R. Leopold, A. Miller
Introduction The goal of the IRIDIUM System is to make instant global communications a reality. At first thought, it would seem that we already have global communications. From the U.S., we can place calls to a vast number of domestic and international locations. However, there are niany areas without telephone service, not only in emerging countries, but in developed nations as well. Consider that in Russia, ,
{"title":"The IRIDIUM TM/SM1 Personal Communication System","authors":"M. Borota, K. Johnson, R. Leopold, A. Miller","doi":"10.1109/VLSIC.1994.586153","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586153","url":null,"abstract":"Introduction The goal of the IRIDIUM System is to make instant global communications a reality. At first thought, it would seem that we already have global communications. From the U.S., we can place calls to a vast number of domestic and international locations. However, there are niany areas without telephone service, not only in emerging countries, but in developed nations as well. Consider that in Russia, ,","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"7 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131406032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586246
D. Takashima, H. Nakano, T. Ozaki, Y. Oowaki, S. Shiratake, S. Watanabe, K. Ohuchi
{"title":"Folded-read And Open/folded-restore Bit-line Scheme For Giga Scale 6f2 Dram Cell","authors":"D. Takashima, H. Nakano, T. Ozaki, Y. Oowaki, S. Shiratake, S. Watanabe, K. Ohuchi","doi":"10.1109/VLSIC.1994.586246","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586246","url":null,"abstract":"","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"582 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115670668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586226
Y. Kodama, M. Yanagisawa, K. Shigenobu, T. Suzuki, H. Mochizuki, T. Ema
We developed a 150-MHz 64M-bit SDRAM with an address incrementing pipeline scheme. For a synchronous read/write operation, we divided the column access path into three pipeline stages [l]. To increase the operating speed, we developed an address incrementing pipeline scheme, which can concurrently access data at two consecutive addresses. Using this scheme, the area penalty is 1.5% more than that of the conventional DRAM. For high frequency signals, we used T
{"title":"A 150-mhz 4-bank 64m-bit Sdram With Address Incrementing Pipeline Scheme","authors":"Y. Kodama, M. Yanagisawa, K. Shigenobu, T. Suzuki, H. Mochizuki, T. Ema","doi":"10.1109/VLSIC.1994.586226","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586226","url":null,"abstract":"We developed a 150-MHz 64M-bit SDRAM with an address incrementing pipeline scheme. For a synchronous read/write operation, we divided the column access path into three pipeline stages [l]. To increase the operating speed, we developed an address incrementing pipeline scheme, which can concurrently access data at two consecutive addresses. Using this scheme, the area penalty is 1.5% more than that of the conventional DRAM. For high frequency signals, we used T","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121738178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586247
K. Ueda, N. Sasaki, H. Sato, S. Kubo, K. Mashiko
I . INTRODUCTION Optical transmission systems require multiplexer and demultiplexer chips as the major ingredients. There have been proposed and realized several architectures for multiplexers and demultiplexers. Such as the shift resister architecture, the interleaved architecture, the series gated architecture, and so on. In general, these previous architectures have aimed at high speed operation rather than low power dissipation. In multiplexers, the series gated architecture is effective in reducing power dissipation because the series gate can implement complex logic with fewer current sources. However, the architecture requires the 3-level for the series gate [l]. Thus it is difficult to lower the supply voltage for multiplexers. Furthermore, the architecture requires larger current to drive the 3-level series gate at high speed. On the other hand, the interleaved architecture is widely used in demultiplexers. In this architecture, conversion from serial to parallel data requires the lst, 2nd and 3rd stage flipflops [2]. This requires a large amount of hardware and therefore consumes much power. In this paper, 8:l multiplexer and 1% demultiplexer chips with low power dissipation are described. The multiplexer chip adopts the modified series gated architecture, while the demultiplexer chip adopts the modified interleaved architecture.
{"title":"3. Ogb/s, 272mw, 8:1 Multiplexer And 4.1gb/s, 388mw, 1:8 Demultiplexer","authors":"K. Ueda, N. Sasaki, H. Sato, S. Kubo, K. Mashiko","doi":"10.1109/VLSIC.1994.586247","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586247","url":null,"abstract":"I . INTRODUCTION Optical transmission systems require multiplexer and demultiplexer chips as the major ingredients. There have been proposed and realized several architectures for multiplexers and demultiplexers. Such as the shift resister architecture, the interleaved architecture, the series gated architecture, and so on. In general, these previous architectures have aimed at high speed operation rather than low power dissipation. In multiplexers, the series gated architecture is effective in reducing power dissipation because the series gate can implement complex logic with fewer current sources. However, the architecture requires the 3-level for the series gate [l]. Thus it is difficult to lower the supply voltage for multiplexers. Furthermore, the architecture requires larger current to drive the 3-level series gate at high speed. On the other hand, the interleaved architecture is widely used in demultiplexers. In this architecture, conversion from serial to parallel data requires the lst, 2nd and 3rd stage flipflops [2]. This requires a large amount of hardware and therefore consumes much power. In this paper, 8:l multiplexer and 1% demultiplexer chips with low power dissipation are described. The multiplexer chip adopts the modified series gated architecture, while the demultiplexer chip adopts the modified interleaved architecture.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124231903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586238
P. Hurst, B. Rothenberg
~[n]=s(f~)=Acos[ dnT+Tn)]= A clock generator with a wide range of programmable frequencies and high programming resolution is described. The average frequency is adjusted by introducing jitter that is concentrated at high frequencies through noise shaping. The sin(") yield
{"title":"A Programmable Clock Generator Using Noise Shaping And Its Application In A Switched-capacitor Filter","authors":"P. Hurst, B. Rothenberg","doi":"10.1109/VLSIC.1994.586238","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586238","url":null,"abstract":"~[n]=s(f~)=Acos[ dnT+Tn)]= A clock generator with a wide range of programmable frequencies and high programming resolution is described. The average frequency is adjusted by introducing jitter that is concentrated at high frequencies through noise shaping. The sin(\") yield","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130065162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586234
Changhyun Kim, K. Wise
This paper describes a micromachined CMOS probe for multisite stimulation and recording in the central nervous system. The probe uses flexible silicon interconnects to allow the signal processing circuitry to fold at right anglcs to the probe shanks, limiting the implanted profile above thc cortex to llmm while driving any 8 of the 64 sites with 0 to k127p.A f1p.A. An on-chip amplifier allows the neural activity on any selected site to be recorded with an overall gain of 50 and bandwidth from 50Hz to 7kHz. Micropower circuit techniques allow the probe to dissipate 4Op.W in standby from f5V.
{"title":"A 64-site Multiplexed Low-profile Neural Probe With On-chip Cmos Circuitry","authors":"Changhyun Kim, K. Wise","doi":"10.1109/VLSIC.1994.586234","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586234","url":null,"abstract":"This paper describes a micromachined CMOS probe for multisite stimulation and recording in the central nervous system. The probe uses flexible silicon interconnects to allow the signal processing circuitry to fold at right anglcs to the probe shanks, limiting the implanted profile above thc cortex to llmm while driving any 8 of the 64 sites with 0 to k127p.A f1p.A. An on-chip amplifier allows the neural activity on any selected site to be recorded with an overall gain of 50 and bandwidth from 50Hz to 7kHz. Micropower circuit techniques allow the probe to dissipate 4Op.W in standby from f5V.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126776368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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