Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586200
J. Alvarez, Hector Sanchez, G. Gerosa, C. Hanke, Roger Countryman, S. Thadasina
A 3.3 V Phase-Locked-Loop (PLL) clock synthesizer implemented in 0.5 μm CMOS technology is described. The PLL support internal to external clock frequency ratios of 1, 1.5, 2, 3, and 4 as well as numerous static power down modes for PowerPC microprocessors. The CPU clock lock range spans from 6 to 175 MHz. Lock times below 15 μs, PLL power dissipation below 10 mW as well as phase error and jitter below ±100 ps have been measured. The total area of the PLL is 0.52 mm 2
介绍了一种采用0.5 μm CMOS技术实现的3.3 V锁相环(PLL)时钟合成器。锁相环支持1、1.5、2、3和4的内部到外部时钟频率比，以及PowerPC微处理器的许多静态断电模式。CPU时钟锁定范围从6到175 MHz。锁相时间小于15 μs，锁相功耗小于10 mW，相位误差和抖动小于±100 ps。锁相环的总面积为0.52 mm 2
{"title":"A Wide-Bandwidth Low-Voltage Pll for Powerpc Microprocessors","authors":"J. Alvarez, Hector Sanchez, G. Gerosa, C. Hanke, Roger Countryman, S. Thadasina","doi":"10.1109/VLSIC.1994.586200","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586200","url":null,"abstract":"A 3.3 V Phase-Locked-Loop (PLL) clock synthesizer implemented in 0.5 μm CMOS technology is described. The PLL support internal to external clock frequency ratios of 1, 1.5, 2, 3, and 4 as well as numerous static power down modes for PowerPC microprocessors. The CPU clock lock range spans from 6 to 175 MHz. Lock times below 15 μs, PLL power dissipation below 10 mW as well as phase error and jitter below ±100 ps have been measured. The total area of the PLL is 0.52 mm 2","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126435357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586219
S. Ozaki, Y. Nishimichi, T. Kakiage, H. Yamamoto, M. Sumita, G. Inoue, M. Urano, H. Yamashita, T. Maeda, T. Nishiyama
This paper desci-ibes a lOOMHz embedded RISC microcontroller which adopts a zero-cycle branching scheme. By this scheme, two instructions are executed in a single cycle if one of them is a branch instruction. A self-clocking cache access scheme and a separated local clock generator are adopted to attain high operating frequency.
{"title":"A 100 Mhz Embedded Risc Microcontroller","authors":"S. Ozaki, Y. Nishimichi, T. Kakiage, H. Yamamoto, M. Sumita, G. Inoue, M. Urano, H. Yamashita, T. Maeda, T. Nishiyama","doi":"10.1109/VLSIC.1994.586219","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586219","url":null,"abstract":"This paper desci-ibes a lOOMHz embedded RISC microcontroller which adopts a zero-cycle branching scheme. By this scheme, two instructions are executed in a single cycle if one of them is a branch instruction. A self-clocking cache access scheme and a separated local clock generator are adopted to attain high operating frequency.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123138336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586223
S. Shiratake, D. Takashima, T. Hasegawa, H. Nakano, Y. Oowaki, S. Watanabe, K. Ohuchi, F. Masuoka
Cascade arrangement of DRAM cells, NAND structured DRAM cell, have already been proposed to reduce the cell size[l] and the experimental 256Mbit chip has been fabricated to demonstrate a small chip size[2]. However, realizing IGbit or further, the NAND DRAM faces a crucial array noise problem due to its open bitline (BL) array arrangement which has larger array noise than the folded BL arrangement[3]. The conventional NAND DRAM inevitably adopts the open BL arrangement, because memory cells are placed a t all the intersection between wordlines and bitlines, so all the BL’s receive the cell data when a wordline is activated, accordingly reference BL’s cannot be arranged in the same memory mat. To overcome this problem, we propose a Staggered NAND DRAM array architecture which realizes folded BL scheme in a NAND DRAM.
{"title":"A Staggered Nand Dram Array Architecture For A Gbit Scale Integration","authors":"S. Shiratake, D. Takashima, T. Hasegawa, H. Nakano, Y. Oowaki, S. Watanabe, K. Ohuchi, F. Masuoka","doi":"10.1109/VLSIC.1994.586223","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586223","url":null,"abstract":"Cascade arrangement of DRAM cells, NAND structured DRAM cell, have already been proposed to reduce the cell size[l] and the experimental 256Mbit chip has been fabricated to demonstrate a small chip size[2]. However, realizing IGbit or further, the NAND DRAM faces a crucial array noise problem due to its open bitline (BL) array arrangement which has larger array noise than the folded BL arrangement[3]. The conventional NAND DRAM inevitably adopts the open BL arrangement, because memory cells are placed a t all the intersection between wordlines and bitlines, so all the BL’s receive the cell data when a wordline is activated, accordingly reference BL’s cannot be arranged in the same memory mat. To overcome this problem, we propose a Staggered NAND DRAM array architecture which realizes folded BL scheme in a NAND DRAM.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125058097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586153
M. Borota, K. Johnson, R. Leopold, A. Miller
Introduction The goal of the IRIDIUM System is to make instant global communications a reality. At first thought, it would seem that we already have global communications. From the U.S., we can place calls to a vast number of domestic and international locations. However, there are niany areas without telephone service, not only in emerging countries, but in developed nations as well. Consider that in Russia, ,
{"title":"The IRIDIUM TM/SM1 Personal Communication System","authors":"M. Borota, K. Johnson, R. Leopold, A. Miller","doi":"10.1109/VLSIC.1994.586153","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586153","url":null,"abstract":"Introduction The goal of the IRIDIUM System is to make instant global communications a reality. At first thought, it would seem that we already have global communications. From the U.S., we can place calls to a vast number of domestic and international locations. However, there are niany areas without telephone service, not only in emerging countries, but in developed nations as well. Consider that in Russia, ,","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"7 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131406032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586233
Alex Gusinov
achieve 0.03% & 0.03” Differential Gain & Phase performance on a single 3V supply. The op-amp was fabricated on a 4GHz, Dielectrically Isolated (DI), Complementary Bipolar Process. The op-amp employes a fully differential NPN & PNP input stage that can swing 300mV beyond either supply rail. A novel output stage is used to achieve Rail to Rail performance with common emitter output devices having Rsat < 10R The circuit has biasing that compensates for thermal self-heating and early-voltage effects of transistors in the absence of degeneration. PSRR is maintained at 64dB down to 2V single supply operation. A 40MHz operational amplifier (op-amp) has been built to
{"title":"2 To 12v, Single Supply, 40mhz, Video Operational Amplifier With Rail To Rail Input And Output Operation","authors":"Alex Gusinov","doi":"10.1109/VLSIC.1994.586233","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586233","url":null,"abstract":"achieve 0.03% & 0.03” Differential Gain & Phase performance on a single 3V supply. The op-amp was fabricated on a 4GHz, Dielectrically Isolated (DI), Complementary Bipolar Process. The op-amp employes a fully differential NPN & PNP input stage that can swing 300mV beyond either supply rail. A novel output stage is used to achieve Rail to Rail performance with common emitter output devices having Rsat < 10R The circuit has biasing that compensates for thermal self-heating and early-voltage effects of transistors in the absence of degeneration. PSRR is maintained at 64dB down to 2V single supply operation. A 40MHz operational amplifier (op-amp) has been built to","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131985783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586193
H. Kojima, Satoshi Tanaka, K. Sasaki
We propose a half-swing clocking scheme that allows us to reduce power consumption of clocking circuitry by as much as 75%, because all the clock signal swings are reduced to half of the LSI supply voltage. The new clocking scheme causes quite small speed degradation, because the random logic circuits in the critical path are still supplied by the full supply voltage. We also propose a clock driver which supplies half-swing clock and generates half V/sub DD/ by itself. We confirmed that the half-swing clocking scheme provided 67% power saving in a test chip fabricated with 0.5 /spl mu/m CMOS technology, ideally 75%, in the clocking circuitry, and that the degradation in speed was only 0.5 ns by circuit simulation. The key to the proposed clocking scheme is the concept that the voltage swing is reduced only for clocking circuitry, but is retained for all other circuits in the chip. This results in significant power reduction with minimal speed degradation. >
{"title":"Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry","authors":"H. Kojima, Satoshi Tanaka, K. Sasaki","doi":"10.1109/VLSIC.1994.586193","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586193","url":null,"abstract":"We propose a half-swing clocking scheme that allows us to reduce power consumption of clocking circuitry by as much as 75%, because all the clock signal swings are reduced to half of the LSI supply voltage. The new clocking scheme causes quite small speed degradation, because the random logic circuits in the critical path are still supplied by the full supply voltage. We also propose a clock driver which supplies half-swing clock and generates half V/sub DD/ by itself. We confirmed that the half-swing clocking scheme provided 67% power saving in a test chip fabricated with 0.5 /spl mu/m CMOS technology, ideally 75%, in the clocking circuitry, and that the degradation in speed was only 0.5 ns by circuit simulation. The key to the proposed clocking scheme is the concept that the voltage swing is reduced only for clocking circuitry, but is retained for all other circuits in the chip. This results in significant power reduction with minimal speed degradation. >","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116683667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586246
D. Takashima, H. Nakano, T. Ozaki, Y. Oowaki, S. Shiratake, S. Watanabe, K. Ohuchi
{"title":"Folded-read And Open/folded-restore Bit-line Scheme For Giga Scale 6f2 Dram Cell","authors":"D. Takashima, H. Nakano, T. Ozaki, Y. Oowaki, S. Shiratake, S. Watanabe, K. Ohuchi","doi":"10.1109/VLSIC.1994.586246","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586246","url":null,"abstract":"","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"582 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115670668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586226
Y. Kodama, M. Yanagisawa, K. Shigenobu, T. Suzuki, H. Mochizuki, T. Ema
We developed a 150-MHz 64M-bit SDRAM with an address incrementing pipeline scheme. For a synchronous read/write operation, we divided the column access path into three pipeline stages [l]. To increase the operating speed, we developed an address incrementing pipeline scheme, which can concurrently access data at two consecutive addresses. Using this scheme, the area penalty is 1.5% more than that of the conventional DRAM. For high frequency signals, we used T
{"title":"A 150-mhz 4-bank 64m-bit Sdram With Address Incrementing Pipeline Scheme","authors":"Y. Kodama, M. Yanagisawa, K. Shigenobu, T. Suzuki, H. Mochizuki, T. Ema","doi":"10.1109/VLSIC.1994.586226","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586226","url":null,"abstract":"We developed a 150-MHz 64M-bit SDRAM with an address incrementing pipeline scheme. For a synchronous read/write operation, we divided the column access path into three pipeline stages [l]. To increase the operating speed, we developed an address incrementing pipeline scheme, which can concurrently access data at two consecutive addresses. Using this scheme, the area penalty is 1.5% more than that of the conventional DRAM. For high frequency signals, we used T","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121738178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-06-09DOI: 10.1109/VLSIC.1994.586240
H. Nambu, K. Kanetani, Y. Idei, T. Masuda, K. Higeta, M. Ohayashi, M. Usami, K. Yamaguchi, T. Kikuchi, T. Ikeda, K. Ohhata, T. Kusunoki, N. Homma
An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-μm 2 memory cells has been developed using 0.3-μm BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71 % and 58 % of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAM's, witch have been used as cache and control storages in mainframe computers
{"title":"A 0.65ns, 72kb Ecl-cmos Ram Macro For A 1mb Sram","authors":"H. Nambu, K. Kanetani, Y. Idei, T. Masuda, K. Higeta, M. Ohayashi, M. Usami, K. Yamaguchi, T. Kikuchi, T. Ikeda, K. Ohhata, T. Kusunoki, N. Homma","doi":"10.1109/VLSIC.1994.586240","DOIUrl":"https://doi.org/10.1109/VLSIC.1994.586240","url":null,"abstract":"An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-μm 2 memory cells has been developed using 0.3-μm BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71 % and 58 % of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAM's, witch have been used as cache and control storages in mainframe computers","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128454244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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