Pub Date : 2023-01-22DOI: 10.1109/SiRF56960.2023.10046278
Festim Iseini, M. Inac, A. Malignaggi, A. Peczek, G. Kahmen
This paper presents a monolithically integrated optoelectronic transmitter based on a segmented Mach-Zehnder modulator. The chip is fabricated in the 250nmSiGe BiCMOS SG25H5 EPIC technology developed at IHP, a silicon-photonic technology combining 0.25 $mu$m CMOS, high-performance npn HBTs (featuring $mathrm{f}_{mathrm{t}}$/fmax of 210/290 GHz), and a full photonic device set for C/O-band. The chip includes a linear electrical driver, a 5 segments Mach-Zehnder modulator, for a total phase shifter length of 2 mm. Electro-optical time-domain measurements demonstrate open eye diagrams up to 44 Gb/s NRZ. The electro-optical bandwidth is 35 GHz, while the power consumption is 500mW, resulting in a power efficiency of 11.3 pJ/bit at 44 Gb/s. The reported transmitter results in a compact and power efficient solution compared to others in a silicon monolithic approach and comparable to hybrid solutions, within the higher 3 dB electro-optical bandwidth that can be found in the literature.
{"title":"Monolithically Integrated Optoelectronic Transmitter based on Segmented Mach-Zehnder Modulator in EPIC 250 nm BiCMOS Technology","authors":"Festim Iseini, M. Inac, A. Malignaggi, A. Peczek, G. Kahmen","doi":"10.1109/SiRF56960.2023.10046278","DOIUrl":"https://doi.org/10.1109/SiRF56960.2023.10046278","url":null,"abstract":"This paper presents a monolithically integrated optoelectronic transmitter based on a segmented Mach-Zehnder modulator. The chip is fabricated in the 250nmSiGe BiCMOS SG25H5 EPIC technology developed at IHP, a silicon-photonic technology combining 0.25 $mu$m CMOS, high-performance npn HBTs (featuring $mathrm{f}_{mathrm{t}}$/fmax of 210/290 GHz), and a full photonic device set for C/O-band. The chip includes a linear electrical driver, a 5 segments Mach-Zehnder modulator, for a total phase shifter length of 2 mm. Electro-optical time-domain measurements demonstrate open eye diagrams up to 44 Gb/s NRZ. The electro-optical bandwidth is 35 GHz, while the power consumption is 500mW, resulting in a power efficiency of 11.3 pJ/bit at 44 Gb/s. The reported transmitter results in a compact and power efficient solution compared to others in a silicon monolithic approach and comparable to hybrid solutions, within the higher 3 dB electro-optical bandwidth that can be found in the literature.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125303491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-22DOI: 10.1109/SiRF56960.2023.10046217
Kyung Pil Jung, Seung Hun Kim, Chulwoo Park
This study developed a 60-GHz CMOS heterodyne I/Q up-converter with local oscillator feedthrough (LOFT) suppression and I/Q calibration in 65-nm process. The compact onchip passive I/Q calibration circuits are proposed to suppress image leakage while requiring no additional power consumption. By using varactors and attenuators, the phase and gain difference of up to 20° and 1.5 dB can be calibrated in I/Q mixers, respectively. The proposed I/Q up-converter delivered a peak conversion gain of 4.2 dB across 55-6S.5 GHz for 3-dB bandwidth. With the proposed calibration, the measured LOFT suppression and IRR are 54 and 44 dB respectively, improved by 23.5 and 12 dB compared to without calibration, respectively.
{"title":"A 60-GHz CMOS Broadband Heterodyne I/Q Up-Converter with Suppressed LOFeedthrough and Image Leakages","authors":"Kyung Pil Jung, Seung Hun Kim, Chulwoo Park","doi":"10.1109/SiRF56960.2023.10046217","DOIUrl":"https://doi.org/10.1109/SiRF56960.2023.10046217","url":null,"abstract":"This study developed a 60-GHz CMOS heterodyne I/Q up-converter with local oscillator feedthrough (LOFT) suppression and I/Q calibration in 65-nm process. The compact onchip passive I/Q calibration circuits are proposed to suppress image leakage while requiring no additional power consumption. By using varactors and attenuators, the phase and gain difference of up to 20° and 1.5 dB can be calibrated in I/Q mixers, respectively. The proposed I/Q up-converter delivered a peak conversion gain of 4.2 dB across 55-6S.5 GHz for 3-dB bandwidth. With the proposed calibration, the measured LOFT suppression and IRR are 54 and 44 dB respectively, improved by 23.5 and 12 dB compared to without calibration, respectively.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123658700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-22DOI: 10.1109/SiRF56960.2023.10046254
Ramy Rady, Chriti K. Madsen, S. Palermo, K. Entesari
This paper presents an automatically calibrated and tuned microwave silicon photonic ring resonator. Due to process variations, the initial response of the ring resonator is severely distorted. By embedding a tunable coupler (Mach-Zehnder interferometer (MZI)) and a photo-detector (PD)-based monitor within the ring, and developing a proper automatic tuning algorithm, the desired microwave frequency response of the ring with free spectral range (FSR) of 50 GHz is reconstructed and its resonance frequency is tuned. RF measurements show cancellation of10 and 20 GHz signals by tuning the ORR.
{"title":"Automatic Tuning of Microwave Silicon Photonic Ring Resonators","authors":"Ramy Rady, Chriti K. Madsen, S. Palermo, K. Entesari","doi":"10.1109/SiRF56960.2023.10046254","DOIUrl":"https://doi.org/10.1109/SiRF56960.2023.10046254","url":null,"abstract":"This paper presents an automatically calibrated and tuned microwave silicon photonic ring resonator. Due to process variations, the initial response of the ring resonator is severely distorted. By embedding a tunable coupler (Mach-Zehnder interferometer (MZI)) and a photo-detector (PD)-based monitor within the ring, and developing a proper automatic tuning algorithm, the desired microwave frequency response of the ring with free spectral range (FSR) of 50 GHz is reconstructed and its resonance frequency is tuned. RF measurements show cancellation of10 and 20 GHz signals by tuning the ORR.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125012723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-22DOI: 10.1109/SiRF56960.2023.10046229
T. Fache, M. Moulin, I. Charlet, Z. Chalupa, J. Raskin, F. Allibert, C. Plantier, F. Gaillard, L. Hutin
This paper shows the effect of buried PN junctions on the performances of inductors, and investigates the limitation of the subsequent substrate losses. We provide a simple and robust model that enables a precise evaluation of the substrate losses for devices fabricated on various substrates, and using various PN junctions implantation conditions. We point out that buried PN junctions are very efficient to counter the parasitic surface conduction, increasing the quality factor of inductors by more than 30% in the best experimental conditions. However, this integration does not reach the same performance level as trap rich substrates measured in the same conditions.
{"title":"Buried PN Junctions Impact on the Performances of an Inductor at RF Frequencies","authors":"T. Fache, M. Moulin, I. Charlet, Z. Chalupa, J. Raskin, F. Allibert, C. Plantier, F. Gaillard, L. Hutin","doi":"10.1109/SiRF56960.2023.10046229","DOIUrl":"https://doi.org/10.1109/SiRF56960.2023.10046229","url":null,"abstract":"This paper shows the effect of buried PN junctions on the performances of inductors, and investigates the limitation of the subsequent substrate losses. We provide a simple and robust model that enables a precise evaluation of the substrate losses for devices fabricated on various substrates, and using various PN junctions implantation conditions. We point out that buried PN junctions are very efficient to counter the parasitic surface conduction, increasing the quality factor of inductors by more than 30% in the best experimental conditions. However, this integration does not reach the same performance level as trap rich substrates measured in the same conditions.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126944795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-22DOI: 10.1109/SiRF56960.2023.10046225
Lachlan Cuskelly, Dhruv Bhaskar, L. Belostotski
This paper discusses a linear, high-speed voltage-to-time converter (VTC) as the front end in a time-based analog to-digital converter (TB-ADC). The VTC architecture is based on a constant-slope charging technique with an inherent sampleand-hold stage and adjustable output delay range, capable of up to 7-GS/s conversion rate. The design in implemented in a 65-nm TSMC CMOS process and measured results at 3, 5, and 7GS/s are presented. At 7GS/s, the VTC has a max. output differential delay range of 33 ps, ENOB of 5. lbits (at low input frequencies), and the VTC core consumes 9. 0mW. The input effective resolution bandwidth (ERBW) of this VTC makes it capable of wideband conversion, with a maximum ERBW of greater than 10 GHz measured at 3 GS/s. Time-domain measurements of the VTC are also discussed.
{"title":"A High-Linearity 10-GHz-ERBW 3-to-7-GS/s Voltage-to-Time Converter with Built-In S/H","authors":"Lachlan Cuskelly, Dhruv Bhaskar, L. Belostotski","doi":"10.1109/SiRF56960.2023.10046225","DOIUrl":"https://doi.org/10.1109/SiRF56960.2023.10046225","url":null,"abstract":"This paper discusses a linear, high-speed voltage-to-time converter (VTC) as the front end in a time-based analog to-digital converter (TB-ADC). The VTC architecture is based on a constant-slope charging technique with an inherent sampleand-hold stage and adjustable output delay range, capable of up to 7-GS/s conversion rate. The design in implemented in a 65-nm TSMC CMOS process and measured results at 3, 5, and 7GS/s are presented. At 7GS/s, the VTC has a max. output differential delay range of 33 ps, ENOB of 5. lbits (at low input frequencies), and the VTC core consumes 9. 0mW. The input effective resolution bandwidth (ERBW) of this VTC makes it capable of wideband conversion, with a maximum ERBW of greater than 10 GHz measured at 3 GS/s. Time-domain measurements of the VTC are also discussed.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131531780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-22DOI: 10.1109/SiRF56960.2023.10046146
Siddharth Dhar, S. Monfray, F. Gianesello, F. Julien, Julien Dura, C. Legrand, J. Amouroux, B. Gros, L. Welter, C. Charbuillet, P. Cathelin, E. Canderle, N. Vulliet, E. Escolier, L. Antunes, E. Rouchouze, P. Fornara, C. Rivero, G. Bertrand, P. Chevalier, A. Régnier, D. Gloria, A. Fleury
Over the years, RFSOI has emerged as dominant technology for building RF FEM modules with optimum cost and performance. RFSOI switches are typically designed using thick gate oxides with biasing up to 3. 3V to deliver minimum RON x COFF. With the strong push of operating digital devices at lower voltages, it would become necessary to evaluate the performance of the switch under such operating conditions. In this paper, we analyze the impact of RON x COFF of the switch in 200mm RFSOI technology, under scaled bias conditions and propose path for device optimization.
多年来，RFSOI已成为构建具有最佳成本和性能的射频有限元模块的主导技术。RFSOI开关通常使用偏置高达3的厚栅极氧化物设计。3V提供最小的RON x COFF。随着数字器件在较低电压下工作的强烈推动，有必要在这种工作条件下评估开关的性能。在本文中，我们分析了200mm RFSOI技术中开关在比例偏置条件下的RON x COFF的影响，并提出了器件优化的途径。
{"title":"Performance Trade-Off of RFSOI Switches Under Scaled Bias Conditions","authors":"Siddharth Dhar, S. Monfray, F. Gianesello, F. Julien, Julien Dura, C. Legrand, J. Amouroux, B. Gros, L. Welter, C. Charbuillet, P. Cathelin, E. Canderle, N. Vulliet, E. Escolier, L. Antunes, E. Rouchouze, P. Fornara, C. Rivero, G. Bertrand, P. Chevalier, A. Régnier, D. Gloria, A. Fleury","doi":"10.1109/SiRF56960.2023.10046146","DOIUrl":"https://doi.org/10.1109/SiRF56960.2023.10046146","url":null,"abstract":"Over the years, RFSOI has emerged as dominant technology for building RF FEM modules with optimum cost and performance. RFSOI switches are typically designed using thick gate oxides with biasing up to 3. 3V to deliver minimum RON x COFF. With the strong push of operating digital devices at lower voltages, it would become necessary to evaluate the performance of the switch under such operating conditions. In this paper, we analyze the impact of RON x COFF of the switch in 200mm RFSOI technology, under scaled bias conditions and propose path for device optimization.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123472277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-22DOI: 10.1109/SiRF56960.2023.10046275
Jan Schoepfel, H. Rücker, N. Pohl
In this paper, a differential Doherty power amplifier for automotive applications in a 130nm SiGe BiCMOS technology, featuring ft/fmax of 470/650 GHz, is presented. The amplifier achieves a measured, peak power added efficiency of 11.6% with 17.0dBm saturated output power at a frequency of 79GHz. In the 6dB power back-off, the proposed amplifier offers a power added efficiency of 6.1%. For comparison, a reference Class-A amplifier has been designed that achieves an output power of 7.2dBm at the 6dB power back-off with a power added efficiency of 1.8%. Compared to other state-of-the-art Doherty approaches, the proposed architecture first time proves the traditional transmission line-based impedance inversion in the automotive frequency range from 76GHz to 81GHz.
{"title":"A Differential SiGe HBT Doherty Power Amplifier for Automotive Radar at 79 GHz","authors":"Jan Schoepfel, H. Rücker, N. Pohl","doi":"10.1109/SiRF56960.2023.10046275","DOIUrl":"https://doi.org/10.1109/SiRF56960.2023.10046275","url":null,"abstract":"In this paper, a differential Doherty power amplifier for automotive applications in a 130nm SiGe BiCMOS technology, featuring ft/fmax of 470/650 GHz, is presented. The amplifier achieves a measured, peak power added efficiency of 11.6% with 17.0dBm saturated output power at a frequency of 79GHz. In the 6dB power back-off, the proposed amplifier offers a power added efficiency of 6.1%. For comparison, a reference Class-A amplifier has been designed that achieves an output power of 7.2dBm at the 6dB power back-off with a power added efficiency of 1.8%. Compared to other state-of-the-art Doherty approaches, the proposed architecture first time proves the traditional transmission line-based impedance inversion in the automotive frequency range from 76GHz to 81GHz.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124889585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-22DOI: 10.1109/SiRF56960.2023.10046259
Hao-Yu Chien, Christopher Chen, J. Woo, S. Pamarti, C. Yang, Mau-Chung Frank Chang
A100 GHz wideband static divider is implemented on a 0. 1S$mu$mSiGe BiCMOS technology. The divider achieves a self-resonant frequency (SRF) of 92.5 GHz with a maximum dividing frequency of 100 GHz. The required input power is less than 0dBm across the entire operating range. The divider consumes 66 mW. The circuit has a 100 x SO $mu mathrm{m}^{2}$ active area
一个100ghz宽带静态分频器是在一个0。$ $ $ $ $mSiGe BiCMOS技术。该分频器自谐振频率(SRF)为92.5 GHz，最大分频频率为100 GHz。在整个工作范围内，所需的输入功率小于0dBm。分压器消耗66兆瓦。电路有一个100 x SO $mu mathm {m}^{2}$的活动区域
{"title":"A Low Power 100 GHz Static CML Frequency Divider in 0.18 μm SiGe BiCMOS Technology","authors":"Hao-Yu Chien, Christopher Chen, J. Woo, S. Pamarti, C. Yang, Mau-Chung Frank Chang","doi":"10.1109/SiRF56960.2023.10046259","DOIUrl":"https://doi.org/10.1109/SiRF56960.2023.10046259","url":null,"abstract":"A100 GHz wideband static divider is implemented on a 0. 1S$mu$mSiGe BiCMOS technology. The divider achieves a self-resonant frequency (SRF) of 92.5 GHz with a maximum dividing frequency of 100 GHz. The required input power is less than 0dBm across the entire operating range. The divider consumes 66 mW. The circuit has a 100 x SO $mu mathrm{m}^{2}$ active area","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128024436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-22DOI: 10.1109/SiRF56960.2023.10046216
G. Simoncini, F. Alimenti
Integrated noise sources are fundamental for precise gain and noise figure measurements in Built-In Test Equipments. In this paper a custom-developed, avalanche noise diode model is used in a commercial CAD software and applied to the input of a Ka-band Low Noise Amplifier for Built-In Self-Test purposes. Few noise diodes have been characterized in recent years, and among those whose models are available in the literature, the 20$mu m^{2}$ p-i-n diode developed with commercial 130-nm SiGe BiCMOS technology is considered. The diode is connected with an LNA realized in 130-nm SiGe BiCMOS IHP technology. Noise measurements are simulated to extract the noise figure and gain of the LNA. The extracted parameters are then compared with those autonomously simulated with the CAD. The obtained results show the importance of simulations in defining the theoretical limits of a noise BITE in ideal power measurements conditions. Moreover they present how the model can be successfully used to simulate a noise Built-In Test Equipment block for calibration purposes.
{"title":"Simulation of Built-In Test Equipments based on Avalanche Noise Diodes: Ka-band LNA Case Study","authors":"G. Simoncini, F. Alimenti","doi":"10.1109/SiRF56960.2023.10046216","DOIUrl":"https://doi.org/10.1109/SiRF56960.2023.10046216","url":null,"abstract":"Integrated noise sources are fundamental for precise gain and noise figure measurements in Built-In Test Equipments. In this paper a custom-developed, avalanche noise diode model is used in a commercial CAD software and applied to the input of a Ka-band Low Noise Amplifier for Built-In Self-Test purposes. Few noise diodes have been characterized in recent years, and among those whose models are available in the literature, the 20$mu m^{2}$ p-i-n diode developed with commercial 130-nm SiGe BiCMOS technology is considered. The diode is connected with an LNA realized in 130-nm SiGe BiCMOS IHP technology. Noise measurements are simulated to extract the noise figure and gain of the LNA. The extracted parameters are then compared with those autonomously simulated with the CAD. The obtained results show the importance of simulations in defining the theoretical limits of a noise BITE in ideal power measurements conditions. Moreover they present how the model can be successfully used to simulate a noise Built-In Test Equipment block for calibration purposes.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114918475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-22DOI: 10.1109/SiRF56960.2023.10046248
M. Inac, F. Korndoerfer, F. Gerfers, A. Malignaggi
In this paper, a highly efficient linear traveling wave amplifier enabling beyond 100GBaud optical data communication is presented, utilizing the “quasi-off” states approach to decrease the overall power consumption maintaining a high bandwidth. The circuit is designed in a SiGe BiCMOS technology featuring 15.3 dB small signal gain within a 87.4 GHz 3 dB bandwidth, while the 1dB output compression point reaches 13.3 dBm for a power efficiency of 4.1%. Time domain measurements demonstrate a non-return-to-zero transmission data rate of 120 Gb/s. The amplifier consumes an overall DC power of 499mW at maximum gain state, and the “quasi-off” states approach enables a power saving up to 50% without deteriorating the bandwidth.
{"title":"Tunable and Highly Power Efficient Traveling Wave Amplifier in SiGe BiCMOS for Optical Modulators","authors":"M. Inac, F. Korndoerfer, F. Gerfers, A. Malignaggi","doi":"10.1109/SiRF56960.2023.10046248","DOIUrl":"https://doi.org/10.1109/SiRF56960.2023.10046248","url":null,"abstract":"In this paper, a highly efficient linear traveling wave amplifier enabling beyond 100GBaud optical data communication is presented, utilizing the “quasi-off” states approach to decrease the overall power consumption maintaining a high bandwidth. The circuit is designed in a SiGe BiCMOS technology featuring 15.3 dB small signal gain within a 87.4 GHz 3 dB bandwidth, while the 1dB output compression point reaches 13.3 dBm for a power efficiency of 4.1%. Time domain measurements demonstrate a non-return-to-zero transmission data rate of 120 Gb/s. The amplifier consumes an overall DC power of 499mW at maximum gain state, and the “quasi-off” states approach enables a power saving up to 50% without deteriorating the bandwidth.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121141582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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