Pub Date : 2023-01-22DOI: 10.1109/SiRF56960.2023.10046233
A. Siligaris, P. Courouve, G. Waltener, A. Hamani, C. Dehos, J. González-Jiménez
This paper presents an energy-efficient wideband Vband channel-bonding up-converter. The circuit, fabricated in 45nm CMOS RFSOI technology is composed of four lanes and an output hybrid combiner based on differential coupled lines. The circuit has four I and Q inputs and each one gets up-converted to a different channel at V-band at the output. The four required LO frequencies (58.32, 60.48, 62.64 and 64.48 GHz) are generated onchip using high integer number frequency multiplication from a common reference input at2.16 GHz that sets the channel spacing. Four-channel 64-QAM modulation is demonstrated with a total data rate of 42.24 Gb/s and 9.9 pJ/b of energy efficiency.
{"title":"A 42.24 Gb/s Channel Bonding Up-Converter with integrated multi-LO generation in 45nm CMOS","authors":"A. Siligaris, P. Courouve, G. Waltener, A. Hamani, C. Dehos, J. González-Jiménez","doi":"10.1109/SiRF56960.2023.10046233","DOIUrl":"https://doi.org/10.1109/SiRF56960.2023.10046233","url":null,"abstract":"This paper presents an energy-efficient wideband Vband channel-bonding up-converter. The circuit, fabricated in 45nm CMOS RFSOI technology is composed of four lanes and an output hybrid combiner based on differential coupled lines. The circuit has four I and Q inputs and each one gets up-converted to a different channel at V-band at the output. The four required LO frequencies (58.32, 60.48, 62.64 and 64.48 GHz) are generated onchip using high integer number frequency multiplication from a common reference input at2.16 GHz that sets the channel spacing. Four-channel 64-QAM modulation is demonstrated with a total data rate of 42.24 Gb/s and 9.9 pJ/b of energy efficiency.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114699285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-22DOI: 10.1109/SiRF56960.2023.10046223
M. Kucharski, M. Klemm, R. Piesiewicz, V. Valenta
This paper presents a SiGe BiCMOS tunable quadrature (IQ) local oscillator (LO) source used in multichannel receiver (RX) front-ends for L, C and X-band space applications. The LO is based on a single X-band voltagecontrolled oscillator (VCO) and programmable frequency divider (FD) chain. The VCO implements a common-collector Colpitts topology with a transformer load and butter chain to isolate the VCO tank circuit from the FD. The FD comprises one divide-by2/3 and two divide-by-2 flip-flop based stages enabling division ratios up to 12 to support C and L-band. The circuit provides IQ differential signals in 1. 05-1.9GHz, 4.3-5.9 GHz and 8.6-11.8 GHz range derived from a single 10.2 GHz VCO with 31% tuning range and -99.7dBc/Hz worst case phase noise at lMHz offset from the carrier.
{"title":"A Tunable SiGe BiCMOS Quadrature LO Source with 31% Tuning Range for L, C and X-band Space-borne Remote Sensing","authors":"M. Kucharski, M. Klemm, R. Piesiewicz, V. Valenta","doi":"10.1109/SiRF56960.2023.10046223","DOIUrl":"https://doi.org/10.1109/SiRF56960.2023.10046223","url":null,"abstract":"This paper presents a SiGe BiCMOS tunable quadrature (IQ) local oscillator (LO) source used in multichannel receiver (RX) front-ends for L, C and X-band space applications. The LO is based on a single X-band voltagecontrolled oscillator (VCO) and programmable frequency divider (FD) chain. The VCO implements a common-collector Colpitts topology with a transformer load and butter chain to isolate the VCO tank circuit from the FD. The FD comprises one divide-by2/3 and two divide-by-2 flip-flop based stages enabling division ratios up to 12 to support C and L-band. The circuit provides IQ differential signals in 1. 05-1.9GHz, 4.3-5.9 GHz and 8.6-11.8 GHz range derived from a single 10.2 GHz VCO with 31% tuning range and -99.7dBc/Hz worst case phase noise at lMHz offset from the carrier.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124135407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-22DOI: 10.1109/SiRF56960.2023.10046210
Q. H. Le, D. K. Huynh, S. Lehmann, Zhixing Zhao, C. Schwan, T. Kämpfe, M. Rudolph
This paper presents the modeling and analysis of the high-frequency noise in 22-nm FDSOI CMOS technology. Experimental noise parameters up to 170 GHz of a multi-finger n-channel transistor are extracted by utilizing the tuner-based method. The Pucel (PRC) noise model is applied and validated for prediction of 22-nm FDSOI noise characteristics from low frequencies to D-band frequencies. In addition, extraction and analysis of the model parameters versus drain current at the W-band frequency 94 GHz are demonstrated.
{"title":"22-nm FDSOI CMOS Noise Modeling and Analysis in mm-Wave Frequency Range","authors":"Q. H. Le, D. K. Huynh, S. Lehmann, Zhixing Zhao, C. Schwan, T. Kämpfe, M. Rudolph","doi":"10.1109/SiRF56960.2023.10046210","DOIUrl":"https://doi.org/10.1109/SiRF56960.2023.10046210","url":null,"abstract":"This paper presents the modeling and analysis of the high-frequency noise in 22-nm FDSOI CMOS technology. Experimental noise parameters up to 170 GHz of a multi-finger n-channel transistor are extracted by utilizing the tuner-based method. The Pucel (PRC) noise model is applied and validated for prediction of 22-nm FDSOI noise characteristics from low frequencies to D-band frequencies. In addition, extraction and analysis of the model parameters versus drain current at the W-band frequency 94 GHz are demonstrated.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"604 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131610677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-22DOI: 10.1109/SiRF56960.2023.10046276
Kaan Balaban, Matthias Möck, A. Ulusoy
This paper presents the design and experimental characterization of a D-band down-conversion mixer in 22-nm FDSOI CMOS technology, which exhibits a conversion gain of 1 to 4 dB within a frequency range of115 to 165 GHz, when driven with an LO power of 3.5 dBm. Further, the passive architecture presents a good out-of-band rejection, with a 3-dB bandwidth of 500 MHz within the entire operating frequency range. The downconversion mixer exhibits an input 1-dB compression point of -5.2dBm measured with an LO power of -19dBm at the center frequency of 140 GHz.
{"title":"A Highly Linear D-Band Broadband Down Conversion Mixer in 22-nm FDSOI CMOS","authors":"Kaan Balaban, Matthias Möck, A. Ulusoy","doi":"10.1109/SiRF56960.2023.10046276","DOIUrl":"https://doi.org/10.1109/SiRF56960.2023.10046276","url":null,"abstract":"This paper presents the design and experimental characterization of a D-band down-conversion mixer in 22-nm FDSOI CMOS technology, which exhibits a conversion gain of 1 to 4 dB within a frequency range of115 to 165 GHz, when driven with an LO power of 3.5 dBm. Further, the passive architecture presents a good out-of-band rejection, with a 3-dB bandwidth of 500 MHz within the entire operating frequency range. The downconversion mixer exhibits an input 1-dB compression point of -5.2dBm measured with an LO power of -19dBm at the center frequency of 140 GHz.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134358212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-22DOI: 10.1109/SiRF56960.2023.10046279
Alexander Haag, M. Kaynak, A. Ulusoy
This paper presents the design and thermal challenges of large-scale silicon-based power amplifiers (PAs). As an example, a Ka-Band PA in 130 nm silicon germanium (SiGe) BiCMOS with an aluminum back end of line (BEOL) is presented. It is a pseudo differential transformer-based design featuring efficient 2:1 transformers for a high impedance transformation ratio. The PA achieves Psat of 23.2 dBm at 26 % power added efficiency (PAE). Differing results due to on-chip thermal effects are presented and discussed in this paper.
{"title":"Thermal Analysis and Design of a Ka-Band Power Amplifier in 130 nm SiGe BiCMOS","authors":"Alexander Haag, M. Kaynak, A. Ulusoy","doi":"10.1109/SiRF56960.2023.10046279","DOIUrl":"https://doi.org/10.1109/SiRF56960.2023.10046279","url":null,"abstract":"This paper presents the design and thermal challenges of large-scale silicon-based power amplifiers (PAs). As an example, a Ka-Band PA in 130 nm silicon germanium (SiGe) BiCMOS with an aluminum back end of line (BEOL) is presented. It is a pseudo differential transformer-based design featuring efficient 2:1 transformers for a high impedance transformation ratio. The PA achieves Psat of 23.2 dBm at 26 % power added efficiency (PAE). Differing results due to on-chip thermal effects are presented and discussed in this paper.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131391952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-22DOI: 10.1109/SiRF56960.2023.10046255
Ho‐Chang Lee, S. Jang, Ren-Xiang Yang
This letter designs an LC-type CMOS NP-crosscoupled voltage-controlled oscillator (VCO) using an S-shape transformer used to boost the P-FET and N-FET source voltage swings for low power dissipation. The transformer uses two 3-turn coils twisted in series as the primary and the layout method reduces the number of crossing metal lines and parasitic capacitance. The one-turn 8-shaped secondary interleaves with the primary to get high-coupling coefficient. The transformer topology enables symmetric transformer layout and the two lobes of the 8-shaped primary and secondary inductors radiate far-field magnetic fields to suppress the magnetic field radiation. The die area of the VCO in the TSMC 0.1S$mu$m CMOS process is 0.762 × 0.S55 mm2. The measured phase noise of the VCO at 2. 7S GHz.
本文设计了一种lc型CMOS np交叉耦合压控振荡器(VCO)，该振荡器使用s形变压器来提升P-FET和N-FET源电压波动，以实现低功耗。该变压器采用2个3匝线圈串联绞合为主线，这种布置方式减少了金属线交叉数和寄生电容。一圈8形次级与初级相互交织，获得高耦合系数。变压器拓扑结构使变压器对称布局，8形初级和次级电感的两个叶向远场磁场辐射，以抑制磁场辐射。在台积电0.1S$mu$m CMOS工艺中，压控振荡器的模面积为0.762 × 0。S55平方毫米。测量的VCO在2时的相位噪声。7 s GHz。
{"title":"Low Power CMOS VCO Using an 8-shaped Transformer","authors":"Ho‐Chang Lee, S. Jang, Ren-Xiang Yang","doi":"10.1109/SiRF56960.2023.10046255","DOIUrl":"https://doi.org/10.1109/SiRF56960.2023.10046255","url":null,"abstract":"This letter designs an LC-type CMOS NP-crosscoupled voltage-controlled oscillator (VCO) using an S-shape transformer used to boost the P-FET and N-FET source voltage swings for low power dissipation. The transformer uses two 3-turn coils twisted in series as the primary and the layout method reduces the number of crossing metal lines and parasitic capacitance. The one-turn 8-shaped secondary interleaves with the primary to get high-coupling coefficient. The transformer topology enables symmetric transformer layout and the two lobes of the 8-shaped primary and secondary inductors radiate far-field magnetic fields to suppress the magnetic field radiation. The die area of the VCO in the TSMC 0.1S$mu$m CMOS process is 0.762 × 0.S55 mm2. The measured phase noise of the VCO at 2. 7S GHz.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"80 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126220325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-22DOI: 10.1109/SiRF56960.2023.10046285
Meghana Kadam, F. Padovan, V. Issakov
The voltage-controlled oscillator is the heart of every mm-wave radar or communication system and it needs to attain stringent requirements such as low phase noise and a wide tuning range. In this work, we extend our previous work on dual-core VCO by proposing an enhanced common-mode coupling device for the second harmonic extraction from the VCO resonator using the mode separation principle. he proposed coupling device targets the elimination of eddy currents to reduce power losses and ensure better phase noise. The proposed VCO in measurements exhibits the phase noise of -105.72dBc/Hz at lMHz offset from a 58 GHz carrier and a -ldBm of the output power spectrum. It was tunable up to the tuning range of 26.41 % centered at 58.48 GHz frequency. The VCO along with the butter and 4-stage divide-by-8 fundamental frequency divider consume 112mA from a 1. 8V supply.
{"title":"Dual-Core mm-Wave VCO with Enhanced Second Harmonic Extraction by Mode Separation","authors":"Meghana Kadam, F. Padovan, V. Issakov","doi":"10.1109/SiRF56960.2023.10046285","DOIUrl":"https://doi.org/10.1109/SiRF56960.2023.10046285","url":null,"abstract":"The voltage-controlled oscillator is the heart of every mm-wave radar or communication system and it needs to attain stringent requirements such as low phase noise and a wide tuning range. In this work, we extend our previous work on dual-core VCO by proposing an enhanced common-mode coupling device for the second harmonic extraction from the VCO resonator using the mode separation principle. he proposed coupling device targets the elimination of eddy currents to reduce power losses and ensure better phase noise. The proposed VCO in measurements exhibits the phase noise of -105.72dBc/Hz at lMHz offset from a 58 GHz carrier and a -ldBm of the output power spectrum. It was tunable up to the tuning range of 26.41 % centered at 58.48 GHz frequency. The VCO along with the butter and 4-stage divide-by-8 fundamental frequency divider consume 112mA from a 1. 8V supply.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124061116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-22DOI: 10.1109/SiRF56960.2023.10046145
M. Perrosé, P. Alba, M. Moulin, E. Augendre, J. Lugo, J. Raskin, S. Reboh
We report on polysilicon trap-rich layers fabricated locally by ion implantation and nanosecond laser annealing on high-resistivity Si substrates. Using coplanar waveguides (of 1.5 mm length, $70 mu mathrm{m}$ central line width and $42 mu mathrm{m}$ spacing between central line and planar ground) we demonstrated RF figures of merit with the second harmonic of -84 dBm at an input RF power of 15 dBm and losses lower than 0.10 dB/mm at a 10 GHz frequency. The characteristics are stable with bias voltage. The proposed method is intended to fabricate trap-rich layers in selected wafer areas, potentially enabling the cointegration with FD-SOI technology.
本文报道了利用离子注入和纳秒激光退火在高电阻率硅衬底上局部制备的多晶硅富阱层。使用共面波导(长度为1.5 mm，中心线宽度为70 mu mathrm{m}$，中心线与平面地间距为42 mu mathrm{m}$)，我们展示了在输入RF功率为15 dBm时二次谐波为-84 dBm，损耗低于0.10 dB/mm的射频数字。该特性在偏置电压下稳定。所提出的方法旨在在选定的晶圆区域制造富含陷阱的层，可能实现与FD-SOI技术的协整。
{"title":"RF figures of merit of polysilicon trap-rich layers formed locally by ion amorphization and nanosecond laser annealing","authors":"M. Perrosé, P. Alba, M. Moulin, E. Augendre, J. Lugo, J. Raskin, S. Reboh","doi":"10.1109/SiRF56960.2023.10046145","DOIUrl":"https://doi.org/10.1109/SiRF56960.2023.10046145","url":null,"abstract":"We report on polysilicon trap-rich layers fabricated locally by ion implantation and nanosecond laser annealing on high-resistivity Si substrates. Using coplanar waveguides (of 1.5 mm length, $70 mu mathrm{m}$ central line width and $42 mu mathrm{m}$ spacing between central line and planar ground) we demonstrated RF figures of merit with the second harmonic of -84 dBm at an input RF power of 15 dBm and losses lower than 0.10 dB/mm at a 10 GHz frequency. The characteristics are stable with bias voltage. The proposed method is intended to fabricate trap-rich layers in selected wafer areas, potentially enabling the cointegration with FD-SOI technology.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115417434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-22DOI: 10.1109/SiRF56960.2023.10046260
H. Papurcu, J. Romstadt, Steffen Hansen, C. Krebs, K. Aufinger, N. Pohl
This paper presents a wideband D-Band transceiver MMIC in Infineon’s 0.13 $mu$mSiGe BiCMOS technology BIIHFC. The MMIC has four channels and is designed for an FMCW MIMO radar application with Time Division Multiplexing. Each channel can either be operated as a transmitter or a receiver. Measurements show a maximum transmitted power of 4. 6dBm and a harmonic rejection of 32.5 dBc at the center frequency ($approx$133GHz). The corresponding 3-dB bandwidth covers a range of 42.5 GHz from 111.5 GHz to 154 GHz. If a channel is operated as a receiver, a maximum voltage gain of 26. 5dB, an input referred 1-dB compression point above -13.5dBm, and a 3-dB bandwidth of 42 GHz (114 GHz -156 GHz) are exhibited.
{"title":"A Wideband Four-Channel SiGe D-Band Transceiver MMIC For TDM MIMO FMCW Radar","authors":"H. Papurcu, J. Romstadt, Steffen Hansen, C. Krebs, K. Aufinger, N. Pohl","doi":"10.1109/SiRF56960.2023.10046260","DOIUrl":"https://doi.org/10.1109/SiRF56960.2023.10046260","url":null,"abstract":"This paper presents a wideband D-Band transceiver MMIC in Infineon’s 0.13 $mu$mSiGe BiCMOS technology BIIHFC. The MMIC has four channels and is designed for an FMCW MIMO radar application with Time Division Multiplexing. Each channel can either be operated as a transmitter or a receiver. Measurements show a maximum transmitted power of 4. 6dBm and a harmonic rejection of 32.5 dBc at the center frequency ($approx$133GHz). The corresponding 3-dB bandwidth covers a range of 42.5 GHz from 111.5 GHz to 154 GHz. If a channel is operated as a receiver, a maximum voltage gain of 26. 5dB, an input referred 1-dB compression point above -13.5dBm, and a 3-dB bandwidth of 42 GHz (114 GHz -156 GHz) are exhibited.","PeriodicalId":354948,"journal":{"name":"2023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125238715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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