Rajeev R. Rao, A. Srivastava, D. Blaauw, D. Sylvester
We develop a method to estimate the variation of leakage current due to both intra-die and inter-die gate length process variability. We derive an analytical expression to estimate the probability density function (PDF) of the leakage current for stacked devices found in CMOS gates. These distributions of individual gate leakage currents are then combined to obtain the mean and variance of the leakage current for an entire circuit. We also present an approach to account for both the inter- and intra-die gate length variations to ensure that the circuit leakage PDF correctly models both types of variation. The proposed methods were implemented and tested on a number of benchmark circuits. Comparison to Monte-Carlo simulation validates the accuracy of the proposed method and demonstrates the efficiency of the proposed analysis method. Comparison with traditional deterministic leakage current analysis demonstrates the need for statistical methods for leakage current analysis.
{"title":"Statistical estimation of leakage current considering inter- and intra-die process variation","authors":"Rajeev R. Rao, A. Srivastava, D. Blaauw, D. Sylvester","doi":"10.1145/871506.871530","DOIUrl":"https://doi.org/10.1145/871506.871530","url":null,"abstract":"We develop a method to estimate the variation of leakage current due to both intra-die and inter-die gate length process variability. We derive an analytical expression to estimate the probability density function (PDF) of the leakage current for stacked devices found in CMOS gates. These distributions of individual gate leakage currents are then combined to obtain the mean and variance of the leakage current for an entire circuit. We also present an approach to account for both the inter- and intra-die gate length variations to ensure that the circuit leakage PDF correctly models both types of variation. The proposed methods were implemented and tested on a number of benchmark circuits. Comparison to Monte-Carlo simulation validates the accuracy of the proposed method and demonstrates the efficiency of the proposed analysis method. Comparison with traditional deterministic leakage current analysis demonstrates the need for statistical methods for leakage current analysis.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116972259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose an efficient approach to minimize total power (switching, short-circuit, and leakage power) without performance loss for ultra-low power CMOS circuits in nanometer technologies. We present a framework for combining supply/threshold voltage scaling, gate sizing, and interconnect scaling techniques for power optimization and propose an efficient heuristic algorithm which ensures that the total slack budget is maximal and the total power is minimal in the presence of back end (post-layout-based) UDSM effects. We have tested the proposed algorithms on a set of benchmark circuits and some building blocks of a synthesizable ARM core. The experimental results show that our polynomial-time solvable strategy delivers over an order of magnitude savings in total power without compromising performance.
{"title":"UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI","authors":"Kyu-won Choi, A. Chatterjee","doi":"10.1145/871506.871527","DOIUrl":"https://doi.org/10.1145/871506.871527","url":null,"abstract":"In this paper, we propose an efficient approach to minimize total power (switching, short-circuit, and leakage power) without performance loss for ultra-low power CMOS circuits in nanometer technologies. We present a framework for combining supply/threshold voltage scaling, gate sizing, and interconnect scaling techniques for power optimization and propose an efficient heuristic algorithm which ensures that the total slack budget is maximal and the total power is minimal in the presence of back end (post-layout-based) UDSM effects. We have tested the proposed algorithms on a set of benchmark circuits and some building blocks of a synthesizable ARM core. The experimental results show that our polynomial-time solvable strategy delivers over an order of magnitude savings in total power without compromising performance.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126461654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Many emerging applications, e.g. in the embedded and DSP space, are often characterized by their loopy nature where a substantial part of the execution time is spent within a few program phases. Loop buffering techniques have been proposed for capturing and processing these loops in small buffers to reduce the processor's instruction fetch energy. However, these schemes are limited to straight-line or innermost loops and fail to adequately handle complex loops. In this paper, we propose a dynamic loop buffering mechanism that uses backwards branch control information to identify, capture and process complex loop structures. The DLB controller has been fully implemented in VHDL, synthesized and timed with the IBM Booledozer and Einstimer Synthesis tools, and analyzed for power with the Sequence PowerTheater tool. Our experiments show that the DLB approach, on average, results in a factor of 3 reduction in energy consumption compared to a traditional instruction memory design at an area overhead of about 9%.
{"title":"Reducing instruction fetch energy with backwards branch control information and buffering","authors":"J. Rivers, S. Asaad, J. Wellman, J. Moreno","doi":"10.1145/871506.871586","DOIUrl":"https://doi.org/10.1145/871506.871586","url":null,"abstract":"Many emerging applications, e.g. in the embedded and DSP space, are often characterized by their loopy nature where a substantial part of the execution time is spent within a few program phases. Loop buffering techniques have been proposed for capturing and processing these loops in small buffers to reduce the processor's instruction fetch energy. However, these schemes are limited to straight-line or innermost loops and fail to adequately handle complex loops. In this paper, we propose a dynamic loop buffering mechanism that uses backwards branch control information to identify, capture and process complex loop structures. The DLB controller has been fully implemented in VHDL, synthesized and timed with the IBM Booledozer and Einstimer Synthesis tools, and analyzed for power with the Sequence PowerTheater tool. Our experiments show that the DLB approach, on average, results in a factor of 3 reduction in energy consumption compared to a traditional instruction memory design at an area overhead of about 9%.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125263947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-08-25DOI: 10.1109/LPE.2003.1231826
Yen-Jen Chang, Chia-Lin Yang, F. Lai
Low power caches have become a critical component of both hand-held devices and high-performance processors. Based on the observation that an overwhelming majority of the data written to the cache are '0', in this paper we propose a power-aware SRAM cell with one single-bitline write port and one differential-bitlines read port, called SWDR cell, to minimize the cache power consumption in writing '0'. The SWDR cell uses a circuit-level technique, which is software independent and orthogonal to other low power techniques at architecture-level. Compared to the conventional SRAM cell, the experimental results show that without compromise of both performance and stability, the SWDR cell can result in 73%-92% reduction in average cache write power dissipated in bitlines.
{"title":"A power-aware SWDR cell for reducing cache write power","authors":"Yen-Jen Chang, Chia-Lin Yang, F. Lai","doi":"10.1109/LPE.2003.1231826","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231826","url":null,"abstract":"Low power caches have become a critical component of both hand-held devices and high-performance processors. Based on the observation that an overwhelming majority of the data written to the cache are '0', in this paper we propose a power-aware SRAM cell with one single-bitline write port and one differential-bitlines read port, called SWDR cell, to minimize the cache power consumption in writing '0'. The SWDR cell uses a circuit-level technique, which is software independent and orthogonal to other low power techniques at architecture-level. Compared to the conventional SRAM cell, the experimental results show that without compromise of both performance and stability, the SWDR cell can result in 73%-92% reduction in average cache write power dissipated in bitlines.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121839801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/LPE.2003.1231824
C.H. Kim, Jae-Joon Kim, S. Mukhopadhyay, K. Roy
This paper presents a forward body-biasing (FBB) scheme for active leakage power reduction in cache memories. We utilize super high V/sub T/ (threshold voltage) devices to suppress the leakage power in unselected portions of a cache while fast operation is achieved by dynamically forward body-biasing the selected SRAM cells. In order to generate a super high V/sub T/ device, the 2D halo doping profile was optimized by considering different nanometer regime leakage mechanisms. The transition latency and energy overhead associated with FBB could be minimized by (i) waking up the SRAM cells ahead of the access and (ii) exploiting the cache access pattern. The combined device-circuit-architecture level techniques offer 64% total leakage reduction and 7.3% improvement in bitline delay compared to a previous state-of-the-art low-leakage SRAM technique.
{"title":"A forward body-biased-low-leakage SRAM cache: device and architecture considerations","authors":"C.H. Kim, Jae-Joon Kim, S. Mukhopadhyay, K. Roy","doi":"10.1109/LPE.2003.1231824","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231824","url":null,"abstract":"This paper presents a forward body-biasing (FBB) scheme for active leakage power reduction in cache memories. We utilize super high V/sub T/ (threshold voltage) devices to suppress the leakage power in unselected portions of a cache while fast operation is achieved by dynamically forward body-biasing the selected SRAM cells. In order to generate a super high V/sub T/ device, the 2D halo doping profile was optimized by considering different nanometer regime leakage mechanisms. The transition latency and energy overhead associated with FBB could be minimized by (i) waking up the SRAM cells ahead of the access and (ii) exploiting the cache access pattern. The combined device-circuit-architecture level techniques offer 64% total leakage reduction and 7.3% improvement in bitline delay compared to a previous state-of-the-art low-leakage SRAM technique.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133803795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/LPE.2003.1231951
P. Heydari, Ying Zhang
This paper presents the design of a high efficiency, low THD, 5.7 GHz fully differential power amplifier for wireless communications in a standard 0.18 /spl mu/m CMOS technology. The power amplifier employs a fully differential class-E topology to achieve high power efficiency by exploiting its soft-switching property. In order to achieve high operating frequency, an injection-locked oscillator is utilized, which makes the output voltage of the power amplifier tuned at the input signal frequency. A complementary CMOS cross-coupled pair topology is employed to realize the LC-tank oscillator because it has lower phase-noise, thereby giving lower THD than the single NMOS cross-coupled pair topology. The proposed power amplifier can deliver 25 dBm output power to a 50 /spl Omega/ load at 5.7 GHz with 42.6% power-added efficiency (PAE) from a 1.8 V supply voltage.
{"title":"A novel high frequency, high-efficiency, differential class-E power amplifier in 0.18 /spl mu/m CMOS","authors":"P. Heydari, Ying Zhang","doi":"10.1109/LPE.2003.1231951","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231951","url":null,"abstract":"This paper presents the design of a high efficiency, low THD, 5.7 GHz fully differential power amplifier for wireless communications in a standard 0.18 /spl mu/m CMOS technology. The power amplifier employs a fully differential class-E topology to achieve high power efficiency by exploiting its soft-switching property. In order to achieve high operating frequency, an injection-locked oscillator is utilized, which makes the output voltage of the power amplifier tuned at the input signal frequency. A complementary CMOS cross-coupled pair topology is employed to realize the LC-tank oscillator because it has lower phase-noise, thereby giving lower THD than the single NMOS cross-coupled pair topology. The proposed power amplifier can deliver 25 dBm output power to a 50 /spl Omega/ load at 5.7 GHz with 42.6% power-added efficiency (PAE) from a 1.8 V supply voltage.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124311902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/LPE.2003.1231913
M. M. Ahmadi, R. Lotfi, M. Sharif-Bakhtiar
A new architecture for constant-g/sub m/, rail-to-rail(R-R) input stages is presented that has less than 5% deviation in g/sub m/ over the entire range of the input common-mode voltage. Furthermore, a new structure for folded cascode amplifier based on the use of a floating current source is presented. Employing these techniques a low-power operational transconductance amplifier (OTA) with 100 MHz unity-gain bandwidth, 106 dB gain, 60/spl deg/ phase margin, 2.65 V swing, and 6.4 nV//spl radic/Hz input-referred noise with R-R input common-mode range is realized in a 0.8 /spl mu/m CMOS technology. This amplifier dissipates 10 mW from a 3V power supply.
{"title":"A new architecture for rail-to-rail input constant-g/sub m/ CMOS operational transconductance amplifiers","authors":"M. M. Ahmadi, R. Lotfi, M. Sharif-Bakhtiar","doi":"10.1109/LPE.2003.1231913","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231913","url":null,"abstract":"A new architecture for constant-g/sub m/, rail-to-rail(R-R) input stages is presented that has less than 5% deviation in g/sub m/ over the entire range of the input common-mode voltage. Furthermore, a new structure for folded cascode amplifier based on the use of a floating current source is presented. Employing these techniques a low-power operational transconductance amplifier (OTA) with 100 MHz unity-gain bandwidth, 106 dB gain, 60/spl deg/ phase margin, 2.65 V swing, and 6.4 nV//spl radic/Hz input-referred noise with R-R input common-mode range is realized in a 0.8 /spl mu/m CMOS technology. This amplifier dissipates 10 mW from a 3V power supply.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128247932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/LPE.2003.1231944
Jonghae Kim, J. Plouchart, N. Zamdmer, M. Sherony, Yue Tan, Meeyoung Yoon, R. Trzcinski, Mosbah Talbi, J. Safran, A. Ray, L. Wagner
This paper describes the design and technology optimization of power-efficient monolithic VCOs with wide tuning range. Four 5-GHz LC-tank VCOs were fabricated in a 0.12-/spl mu/m SOI CMOS technology that was not enhanced for RF applications. High and regular resistivity substrates were used, as were single-layer and multiple-layer copper inductors. Using a new figure-of-merit (FOM/sub T/) that encompasses power dissipation, phase noise and tuning range, our best VCO has an FOM/sub T/ of -189 dBc/Hz. The measured frequency tuning range is 22 % and the phase noise is 126 dBc/Hz at 1 MHz offset for 4.5-GHz. Oscillation was achieved at 5.4-GHz at a minimum power consumption of 500 /spl mu/W.
{"title":"A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology. On high resistivity substrate","authors":"Jonghae Kim, J. Plouchart, N. Zamdmer, M. Sherony, Yue Tan, Meeyoung Yoon, R. Trzcinski, Mosbah Talbi, J. Safran, A. Ray, L. Wagner","doi":"10.1109/LPE.2003.1231944","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231944","url":null,"abstract":"This paper describes the design and technology optimization of power-efficient monolithic VCOs with wide tuning range. Four 5-GHz LC-tank VCOs were fabricated in a 0.12-/spl mu/m SOI CMOS technology that was not enhanced for RF applications. High and regular resistivity substrates were used, as were single-layer and multiple-layer copper inductors. Using a new figure-of-merit (FOM/sub T/) that encompasses power dissipation, phase noise and tuning range, our best VCO has an FOM/sub T/ of -189 dBc/Hz. The measured frequency tuning range is 22 % and the phase noise is 126 dBc/Hz at 1 MHz offset for 4.5-GHz. Oscillation was achieved at 5.4-GHz at a minimum power consumption of 500 /spl mu/W.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130532013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/LPE.2003.1231870
W. Weber
In this presentation, applications are discussed that describe achievements along the road towards 'ambient intelligence'. Appliances and devices disappear into the environment of the individual; instead services come into focus. Key to this development are systems solutions that lead to a significant improvement of the human-machine interface. Along this line, we present important technologies and key system components. They range from technologies for packaging and gathering of ambient energy, to system demonstrators such as low-cost electronic systems, ubiquitous sensor networks and electronics in smart textiles. The prime importance of the electric power supply and of low-power consumption, especially in the peripheral devices, is emphasized.
{"title":"Ambient intelligence - industrial research on a visionary concept","authors":"W. Weber","doi":"10.1109/LPE.2003.1231870","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231870","url":null,"abstract":"In this presentation, applications are discussed that describe achievements along the road towards 'ambient intelligence'. Appliances and devices disappear into the environment of the individual; instead services come into focus. Key to this development are systems solutions that lead to a significant improvement of the human-machine interface. Along this line, we present important technologies and key system components. They range from technologies for packaging and gathering of ambient energy, to system demonstrators such as low-cost electronic systems, ubiquitous sensor networks and electronics in smart textiles. The prime importance of the electric power supply and of low-power consumption, especially in the peripheral devices, is emphasized.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132238870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/LPE.2003.1231856
S. Mukhopadhyay, K. Roy
In this paper we have developed analytical models to estimate the mean and the standard deviation in the gate, the subthreshold, the reverse biased source/drain junction band-to-band tunneling (BTBT) and the total leakage in scaled CMOS devices considering variation in process parameters like device geometry, doping profile, flat-band voltage and supply voltage. We have verified the model using Monte Carlo simulation using an NMOS device of 50 nm effective length and analyzed the results to enumerate the effect of different process parameters on the individual components and the total leakage.
{"title":"Modeling and estimation of total leakage current in nano-scaled-CMOS devices considering the effect of parameter variation","authors":"S. Mukhopadhyay, K. Roy","doi":"10.1109/LPE.2003.1231856","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231856","url":null,"abstract":"In this paper we have developed analytical models to estimate the mean and the standard deviation in the gate, the subthreshold, the reverse biased source/drain junction band-to-band tunneling (BTBT) and the total leakage in scaled CMOS devices considering variation in process parameters like device geometry, doping profile, flat-band voltage and supply voltage. We have verified the model using Monte Carlo simulation using an NMOS device of 50 nm effective length and analyzed the results to enumerate the effect of different process parameters on the individual components and the total leakage.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128961850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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