Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807723
N. Prokopenko, N. I. Chernov, V. Yugai, N. Butyrlagin
In the article the task of construction of the multifunctional current logical element (MLE), which realizes the analogues of logical functions of the Boolean main functionally complete system (AND, OR, NOT), and also the comparison operation x1>x2 is solved for the first time. The quantum of the current I0 is an equivalent of the standard logical signal here. The suggested MLE also provides the normalization of the signal levels - the generation of the output current, which is equal to I0, without regard to the spread (up to 0.5I0) of numerical values of the input current logical variables. The concrete logical function, performed by MLE, is determined by the level of the reference DC current I1 (I1=0.5I0, I1=I0, I1=1.5I0), which is applied to the low-ohmic current input of MLE.
{"title":"The multifunctional current logical element for digital computing devices, operating on the principles of linear (not boolean) algebra","authors":"N. Prokopenko, N. I. Chernov, V. Yugai, N. Butyrlagin","doi":"10.1109/EWDTS.2016.7807723","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807723","url":null,"abstract":"In the article the task of construction of the multifunctional current logical element (MLE), which realizes the analogues of logical functions of the Boolean main functionally complete system (AND, OR, NOT), and also the comparison operation x<sub>1</sub>>x<sub>2</sub> is solved for the first time. The quantum of the current I<sub>0</sub> is an equivalent of the standard logical signal here. The suggested MLE also provides the normalization of the signal levels - the generation of the output current, which is equal to I0, without regard to the spread (up to 0.5I<sub>0</sub>) of numerical values of the input current logical variables. The concrete logical function, performed by MLE, is determined by the level of the reference DC current I<sub>1</sub> (I<sub>1</sub>=0.5I<sub>0</sub>, I<sub>1</sub>=I<sub>0</sub>, I<sub>1</sub>=1.5I<sub>0</sub>), which is applied to the low-ohmic current input of MLE.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125707613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807655
G. Kuchuk, V. Kharchenko, Andriy Kovalenko, E. Ruchkov
Traffic control in modern computer networks, including those within critical infrastructures (e.g. Nuclear Power Plants), implies various optimization problems solving by switching/routing devices in real time. Some of such problems include, for example, choosing of optimal route, distribution of data packets during multiway routing, redistribution of both service and user data, efficient changing of virtual configuration in network segment containing a bottleneck, which, in turn, appeared due to fault or failure of some physical links. In a majority of cases, input data in such problems have a discrete character (for example, traffic samples, statistical estimations, etc.); hence, it is inevitable to use algorithms of discrete optimization. Combinatorial algorithms for finding the solution in discrete optimization problem, applied to switching/routing nodes of critical infrastructures' networks, are considered. Conditions for selection of algorithm type, depending on nature of the problem, are determined. Implicit enumeration algorithms on lacing and tree, as well as algorithms of dynamic programming method are analyzed in details.
{"title":"Approaches to selection of combinatorial algorithm for optimization in network traffic control of safety-critical systems","authors":"G. Kuchuk, V. Kharchenko, Andriy Kovalenko, E. Ruchkov","doi":"10.1109/EWDTS.2016.7807655","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807655","url":null,"abstract":"Traffic control in modern computer networks, including those within critical infrastructures (e.g. Nuclear Power Plants), implies various optimization problems solving by switching/routing devices in real time. Some of such problems include, for example, choosing of optimal route, distribution of data packets during multiway routing, redistribution of both service and user data, efficient changing of virtual configuration in network segment containing a bottleneck, which, in turn, appeared due to fault or failure of some physical links. In a majority of cases, input data in such problems have a discrete character (for example, traffic samples, statistical estimations, etc.); hence, it is inevitable to use algorithms of discrete optimization. Combinatorial algorithms for finding the solution in discrete optimization problem, applied to switching/routing nodes of critical infrastructures' networks, are considered. Conditions for selection of algorithm type, depending on nature of the problem, are determined. Implicit enumeration algorithms on lacing and tree, as well as algorithms of dynamic programming method are analyzed in details.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"87 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125972290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807707
V. M. Artyushenko, V. I. Volovach, B. Kucherov
We obtained the expressions for estimating the accuracy of information parameters measurement of the signal on correlated, in general, non-Gaussian additive noise under continuous processing. It is demonstrated that taking into account the correlation properties and non-Gaussian nature of the additive noise we can significantly improve the measurement accuracy of the information parameters. It is shown that compared to discrete processing continuous processing, ceteris paribus, allows us to obtain a more accurate estimate of the measured parameters.
{"title":"Influence of correlated additive non-Gaussian noise on accuracy of signal parameters measurement during continuous processing","authors":"V. M. Artyushenko, V. I. Volovach, B. Kucherov","doi":"10.1109/EWDTS.2016.7807707","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807707","url":null,"abstract":"We obtained the expressions for estimating the accuracy of information parameters measurement of the signal on correlated, in general, non-Gaussian additive noise under continuous processing. It is demonstrated that taking into account the correlation properties and non-Gaussian nature of the additive noise we can significantly improve the measurement accuracy of the information parameters. It is shown that compared to discrete processing continuous processing, ceteris paribus, allows us to obtain a more accurate estimate of the measured parameters.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121705283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807675
Binod Kumar, B. Nehru, B. Pandey, Virendra Singh, Jaynarayan T. Tudu
Power dissipation is a major issue with testing of designs having full scan architectures. The proposed scan technique minimizes toggle activity while scanning in test patterns. The method uses bit inversion technique to avoid toggles in scan flip-flops. The setup is dynamically configurable to one among the logic reversal structure and traditional scan while shift-in/shift-out of test patterns. Experimental results indicate that the average toggle activity is minimized substantially compared to California Scan architecture. It has features of full diagnosability of single stuck-at faults along the scan chain path.
{"title":"A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture","authors":"Binod Kumar, B. Nehru, B. Pandey, Virendra Singh, Jaynarayan T. Tudu","doi":"10.1109/EWDTS.2016.7807675","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807675","url":null,"abstract":"Power dissipation is a major issue with testing of designs having full scan architectures. The proposed scan technique minimizes toggle activity while scanning in test patterns. The method uses bit inversion technique to avoid toggles in scan flip-flops. The setup is dynamically configurable to one among the logic reversal structure and traditional scan while shift-in/shift-out of test patterns. Experimental results indicate that the average toggle activity is minimized substantially compared to California Scan architecture. It has features of full diagnosability of single stuck-at faults along the scan chain path.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134421372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807684
C. Kołaciński, J. Wasowski, A. Szymanski, A. Jarosz, E. Kurjata-Pfitzner, T. Borejko, Krzysztof Siwiec, W. Pleskacz
This paper presents the design and implementation of the integrated circuit aimed at pulse oximetry measurements and intended to be a part of the biomedical SoC. The basics of the noninvasive method for oxygen saturation monitoring are briefly described and then the overview of the designed chip is presented and discussed. Next, several important simulation results are shown, proving proper operation of the designed structure.
{"title":"Dedicated chip for pulse oximetry measurements","authors":"C. Kołaciński, J. Wasowski, A. Szymanski, A. Jarosz, E. Kurjata-Pfitzner, T. Borejko, Krzysztof Siwiec, W. Pleskacz","doi":"10.1109/EWDTS.2016.7807684","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807684","url":null,"abstract":"This paper presents the design and implementation of the integrated circuit aimed at pulse oximetry measurements and intended to be a part of the biomedical SoC. The basics of the noninvasive method for oxygen saturation monitoring are briefly described and then the overview of the designed chip is presented and discussed. Next, several important simulation results are shown, proving proper operation of the designed structure.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131800655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807747
N. Levchenko, A. Okunev, A. Stempkovsky, D. Zmejev
The paper presents the main differences of the new computing model and the system that implements this model from traditional dataflow systems. The parallel dataflow computing system architecture and I/O processor are briefly described. I/O processor is one of the main management elements of computing process in the system. Functionality of the token-generating unit and various input-output modes are also described. The data obtained with some experiments, which were carried out at the modelling programme for a number of problems, are given.
{"title":"I/O processor as the device for computing process management in the PDCS “Buran”","authors":"N. Levchenko, A. Okunev, A. Stempkovsky, D. Zmejev","doi":"10.1109/EWDTS.2016.7807747","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807747","url":null,"abstract":"The paper presents the main differences of the new computing model and the system that implements this model from traditional dataflow systems. The parallel dataflow computing system architecture and I/O processor are briefly described. I/O processor is one of the main management elements of computing process in the system. Functionality of the token-generating unit and various input-output modes are also described. The data obtained with some experiments, which were carried out at the modelling programme for a number of problems, are given.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127404918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807751
Dmitry Komolov, Tanya Belikova, Volodymyr Krivonos, R. Tarnopolov
In this article deals with estimating and analysis capacity of the closed video channel in the case of applying the method for processing video data based on standardized MPEG technology, the method for closing the video based on the series circuit (compression followed by encryption), the method to hide all the video after the DCT blocks of the base of the video frame, the method based on the selection of significant structural units of the base video frame.
{"title":"Estimate of the capacity of the closed video channel for the method based on the selection of relevant structural units","authors":"Dmitry Komolov, Tanya Belikova, Volodymyr Krivonos, R. Tarnopolov","doi":"10.1109/EWDTS.2016.7807751","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807751","url":null,"abstract":"In this article deals with estimating and analysis capacity of the closed video channel in the case of applying the method for processing video data based on standardized MPEG technology, the method for closing the video based on the series circuit (compression followed by encryption), the method to hide all the video after the DCT blocks of the base of the video frame, the method based on the selection of significant structural units of the base video frame.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115614918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807678
Vazgen Melikyan, Tigran Hakhverdyan, Sergey Manukyan, A. Gevorgyan, D. Babayan
This paper presents a method of power optimization, implemented on Open RISC processor, aimed at reducing dynamic and static power consumption. Multi-voltage design method is one of the effective power reduction methods, implemented by dividing circuit into separate power domains based on their power/performance requirements. Multi-voltage will combination with multi-threshold and power gating techniques to significantly decrease both dynamic and leakage power of processor. Each domain then is supplied by separate power and ground rail.
{"title":"Low power OpenRISC processor with power gating, multi-VTH and multi-voltage techniques","authors":"Vazgen Melikyan, Tigran Hakhverdyan, Sergey Manukyan, A. Gevorgyan, D. Babayan","doi":"10.1109/EWDTS.2016.7807678","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807678","url":null,"abstract":"This paper presents a method of power optimization, implemented on Open RISC processor, aimed at reducing dynamic and static power consumption. Multi-voltage design method is one of the effective power reduction methods, implemented by dividing circuit into separate power domains based on their power/performance requirements. Multi-voltage will combination with multi-threshold and power gating techniques to significantly decrease both dynamic and leakage power of processor. Each domain then is supplied by separate power and ground rail.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115826461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recent research has shown that heterogeneous multicore architectures have the potential to further improve single thread performance. In such architectures different phases of the application are executed on different cores to improve performance and energy efficiency. However, restricting the cores to a single ISA limits the achievable performance gain. Different phases of applications also have shown affinity towards different ISAs due to their characteristics, functionality etc. Heterogeneous ISA architectures thus attempt to execute these different phases on their respective affine cores to fully harness ISA diversity. However, in such architectures, estimating the best migration point from one ISA to another, is an open research problem. This paper proposes a performance model for execution time estimation of heterogeneous ISAs which naturally extends to dynamic scheduling. The model is centred around execution time and a few on-line parameters. Regression techniques have been used to model the performance. Experimental evaluation shows that the proposed model has 78% accuracy in estimating migration from ARM ISA to X86 ISA.
{"title":"Performance modelling of heterogeneous ISA multicore architectures","authors":"N. Boran, Rameshwar Prasad Meghwal, Kuldeep Sharma, Binod Kumar, Virendra Singh","doi":"10.1109/EWDTS.2016.7807641","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807641","url":null,"abstract":"Recent research has shown that heterogeneous multicore architectures have the potential to further improve single thread performance. In such architectures different phases of the application are executed on different cores to improve performance and energy efficiency. However, restricting the cores to a single ISA limits the achievable performance gain. Different phases of applications also have shown affinity towards different ISAs due to their characteristics, functionality etc. Heterogeneous ISA architectures thus attempt to execute these different phases on their respective affine cores to fully harness ISA diversity. However, in such architectures, estimating the best migration point from one ISA to another, is an open research problem. This paper proposes a performance model for execution time estimation of heterogeneous ISAs which naturally extends to dynamic scheduling. The model is centred around execution time and a few on-line parameters. Regression techniques have been used to model the performance. Experimental evaluation shows that the proposed model has 78% accuracy in estimating migration from ARM ISA to X86 ISA.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116868383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807709
M. Shakurskiy, V. Shakurskiy, V. I. Volovach
In this paper digital steganographic system based on contraction mapping is considered. The proposed steganographic algorithm uses two channels to achieve informational redundancy, which allow decoding by using an algorithm invariant to container signal. This peculiarity is excellent in case of information hiding in chaotic signal. This paper is devoted to the illustration of algorithm performance with the stream audio container.
{"title":"Computer model of steganographic system based on contraction mapping with stream audio container","authors":"M. Shakurskiy, V. Shakurskiy, V. I. Volovach","doi":"10.1109/EWDTS.2016.7807709","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807709","url":null,"abstract":"In this paper digital steganographic system based on contraction mapping is considered. The proposed steganographic algorithm uses two channels to achieve informational redundancy, which allow decoding by using an algorithm invariant to container signal. This peculiarity is excellent in case of information hiding in chaotic signal. This paper is devoted to the illustration of algorithm performance with the stream audio container.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117023215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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