Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807726
M. Gromov
In this paper we consider two properties of timed automata, which help to reduce their complexity. We understand complexity as the number of time variables associated with a given timed automaton. The first property concerns redundant time variables and the second - timed automata composition.
{"title":"On simplification of timed automata","authors":"M. Gromov","doi":"10.1109/EWDTS.2016.7807726","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807726","url":null,"abstract":"In this paper we consider two properties of timed automata, which help to reduce their complexity. We understand complexity as the number of time variables associated with a given timed automaton. The first property concerns redundant time variables and the second - timed automata composition.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124995717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807681
D. Prozorov, A. Metelyov, A. Chistyakov, S. V. Romanov
This paper presents the study of the Hierarchical Distance-Vector Geo-Routing (HDVG) protocol for Mobile Ad-Hoc Networks (MANETs) using NS-3 simulator. The criteria for selection of simulation environment are described. The distributed computing technique for NS-3 simulator is proposed. Simulation results show that HDVG, in general case, outperforms well-known routing protocols OLSR, AODV and GPRS.
{"title":"Simulation of a hierarchical routing protocol for MANET","authors":"D. Prozorov, A. Metelyov, A. Chistyakov, S. V. Romanov","doi":"10.1109/EWDTS.2016.7807681","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807681","url":null,"abstract":"This paper presents the study of the Hierarchical Distance-Vector Geo-Routing (HDVG) protocol for Mobile Ad-Hoc Networks (MANETs) using NS-3 simulator. The criteria for selection of simulation environment are described. The distributed computing technique for NS-3 simulator is proposed. Simulation results show that HDVG, in general case, outperforms well-known routing protocols OLSR, AODV and GPRS.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126705638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807625
V. Marchuk, S. Makov, S. Stradanchenko, Alexandr Minaev
This paper deals with assessment of desired signal extraction accuracy using the estimation reproduction method in the conditions of a priori indeterminacy by residuals. Another words we compare estimations of differential probability density, correlation functions and statistical characteristics (mathematical expectation and variance) of the additive noise component and the residual between measured signal and its estimation.
{"title":"Studying accuracy of the new desired signal extraction method by residuals in a priory indeterminacy conditions","authors":"V. Marchuk, S. Makov, S. Stradanchenko, Alexandr Minaev","doi":"10.1109/EWDTS.2016.7807625","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807625","url":null,"abstract":"This paper deals with assessment of desired signal extraction accuracy using the estimation reproduction method in the conditions of a priori indeterminacy by residuals. Another words we compare estimations of differential probability density, correlation functions and statistical characteristics (mathematical expectation and variance) of the additive noise component and the residual between measured signal and its estimation.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126539486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807705
V. M. Artyushenko, V. I. Volovach, V. N. Budilov
Statistical characteristics of the density distribution of the instantaneous frequency of deep fading signals were defined. The threshold method for measuring of motion speed of the extended object within range radio measuring instrument movement device reviewed and analyzed. It is shown that applying of the Doppler signal in the amplitude selection channel can significantly reduce the phase noise, thereby increasing the accuracy of speed measuring of the extended object. An estimation of the potentially achievable object speed measurement accuracy is obtained.
{"title":"The determination of measurement error the instantaneous frequency of the deep fading signals","authors":"V. M. Artyushenko, V. I. Volovach, V. N. Budilov","doi":"10.1109/EWDTS.2016.7807705","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807705","url":null,"abstract":"Statistical characteristics of the density distribution of the instantaneous frequency of deep fading signals were defined. The threshold method for measuring of motion speed of the extended object within range radio measuring instrument movement device reviewed and analyzed. It is shown that applying of the Doppler signal in the amplitude selection channel can significantly reduce the phase noise, thereby increasing the accuracy of speed measuring of the extended object. An estimation of the potentially achievable object speed measurement accuracy is obtained.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123073949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807664
V. Obrizan, Tetiana Soklakova
This paper presents a multivesion parallel synthesis of digital structures based on SystemC specification. The purpose of which is a substantial reduction in design time computing architectures and increasing quality of digital products through multiversion synthesis structure of the digital products based on a predetermined specification in SystemC environments (C ++) and automatic selection of functional components by parallel synthesis and verification of system-level architectural decisions in accordance with proposed metric.
{"title":"Multiversion parallel synthesis of digital structures based on SystemC specification","authors":"V. Obrizan, Tetiana Soklakova","doi":"10.1109/EWDTS.2016.7807664","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807664","url":null,"abstract":"This paper presents a multivesion parallel synthesis of digital structures based on SystemC specification. The purpose of which is a substantial reduction in design time computing architectures and increasing quality of digital products through multiversion synthesis structure of the digital products based on a predetermined specification in SystemC environments (C ++) and automatic selection of functional components by parallel synthesis and verification of system-level architectural decisions in accordance with proposed metric.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"175 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114105817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807727
N. Prokopenko, A. Bugakova, I. Pakhomov
The article considers a new architecture of the BiJFet differential difference operational amplifier (DDA) on the base of single-ended differential stages, providing small values of systematic component of the offset voltage (Vos) in conditions of radiation and low-temperature degradation of current gains of the bipolar transistor base (β). The main equations are obtained, which allow formulating the requirements to the functional nodes of DDA - current mirrors and an output buffer amplifier, at which the effect cancellation P of the applied transistors is provided. The results of the computer simulation of BiJFet-DDA in the range of temperature -140° ÷ +100° and neutron flux up to 5.1013 n/cm2 are given. They show that its magnitude Vos is not bigger than unities of /V.
{"title":"The radiation-hardened differential difference operational amplifiers for operation in the low-temperature analog interfaces of sensors","authors":"N. Prokopenko, A. Bugakova, I. Pakhomov","doi":"10.1109/EWDTS.2016.7807727","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807727","url":null,"abstract":"The article considers a new architecture of the BiJFet differential difference operational amplifier (DDA) on the base of single-ended differential stages, providing small values of systematic component of the offset voltage (Vos) in conditions of radiation and low-temperature degradation of current gains of the bipolar transistor base (β). The main equations are obtained, which allow formulating the requirements to the functional nodes of DDA - current mirrors and an output buffer amplifier, at which the effect cancellation P of the applied transistors is provided. The results of the computer simulation of BiJFet-DDA in the range of temperature -140° ÷ +100° and neutron flux up to 5.1013 n/cm2 are given. They show that its magnitude Vos is not bigger than unities of /V.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114196033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807704
V. M. Artyushenko, V. I. Volovach, M. V. Shakursky
The issues of quasi-optimal signal processing in conditions of simultaneous effect of additive and multiplicative non-Gaussian noise are considered. It is shown that with given a priori information about probability density function of the multiplicative noise, the accuracy of the measurement of the information parameter of the signal, in the case of its slow fluctuations can be significantly worse than in the case of rapid fluctuations of multiplicative noise.
{"title":"The demodulation signal under the influence of additive and multiplicative non-Gaussian noise","authors":"V. M. Artyushenko, V. I. Volovach, M. V. Shakursky","doi":"10.1109/EWDTS.2016.7807704","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807704","url":null,"abstract":"The issues of quasi-optimal signal processing in conditions of simultaneous effect of additive and multiplicative non-Gaussian noise are considered. It is shown that with given a priori information about probability density function of the multiplicative noise, the accuracy of the measurement of the information parameter of the signal, in the case of its slow fluctuations can be significantly worse than in the case of rapid fluctuations of multiplicative noise.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116047156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807632
Hamed Najafi Haghi, M. Chupilko, A. Kamkin, Z. Navabi
Electronic System Level (ESL) design flow tries to handle the complexity of today's System-on-Chip design and verification. Due to this complexity, design and verification methodologies start from an abstraction level higher than Register Transfer Level (RTL). In ESL, verification becomes a major bottleneck in the design flow, and finding a good verification methodology at this abstraction level is important. In this paper, we focus on communication parts of ESL designs rather than the computation parts. Here, we propose a new environment for ESL designs called RTL+, which is an abstraction level higher than RTL and yet lower than TLM-2 implementation of ESL. For RTL+ models verification, we propose using a simulation-based toolkit named C++TESK.
{"title":"ESL design with RTL-verified predesigned abstract communication channels","authors":"Hamed Najafi Haghi, M. Chupilko, A. Kamkin, Z. Navabi","doi":"10.1109/EWDTS.2016.7807632","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807632","url":null,"abstract":"Electronic System Level (ESL) design flow tries to handle the complexity of today's System-on-Chip design and verification. Due to this complexity, design and verification methodologies start from an abstraction level higher than Register Transfer Level (RTL). In ESL, verification becomes a major bottleneck in the design flow, and finding a good verification methodology at this abstraction level is important. In this paper, we focus on communication parts of ESL designs rather than the computation parts. Here, we propose a new environment for ESL designs called RTL+, which is an abstraction level higher than RTL and yet lower than TLM-2 implementation of ESL. For RTL+ models verification, we propose using a simulation-based toolkit named C++TESK.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116499580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807624
V. Marchuk, S. Makov, Alexandr Minaev, V. Voronin, Dmitry Chernyshov
In this article is proposed a new method of bias compensation during processing of continuous desired signals with additive noise component. The noise in this article has asymmetrical distribution law. We propose to use our method of bias removing in automated measurement processing systems.
{"title":"Removing of systematic measurement errors caused by asymmetric distribution law of the noise component","authors":"V. Marchuk, S. Makov, Alexandr Minaev, V. Voronin, Dmitry Chernyshov","doi":"10.1109/EWDTS.2016.7807624","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807624","url":null,"abstract":"In this article is proposed a new method of bias compensation during processing of continuous desired signals with additive noise component. The noise in this article has asymmetrical distribution law. We propose to use our method of bias removing in automated measurement processing systems.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"2005 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127652386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807700
Binod Kumar, Ankit Jindal, Virendra Singh
Enhancing observability is a key challenge in post-silicon validation. On-chip trace buffers store real time data which can be used for analyzing and debugging. Appropriate selection of these signals is crucial for storing useful debug data. This paper proposes a methodology for identifying trace signals so as to maximize detection of erroneous behavior of the failing chip which helps in improving quality of information available for debugging. Different quantitative measures are proposed to assess utility of debug data. Experimental results on benchmark circuits indicate that the methodology is useful for selecting trace signals which maximize debug data effectiveness.
{"title":"A trace signal selection algorithm for improved post-silicon debug","authors":"Binod Kumar, Ankit Jindal, Virendra Singh","doi":"10.1109/EWDTS.2016.7807700","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807700","url":null,"abstract":"Enhancing observability is a key challenge in post-silicon validation. On-chip trace buffers store real time data which can be used for analyzing and debugging. Appropriate selection of these signals is crucial for storing useful debug data. This paper proposes a methodology for identifying trace signals so as to maximize detection of erroneous behavior of the failing chip which helps in improving quality of information available for debugging. Different quantitative measures are proposed to assess utility of debug data. Experimental results on benchmark circuits indicate that the methodology is useful for selecting trace signals which maximize debug data effectiveness.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127715833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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