Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226070
N. Sutisna, L. Lanante, Y. Nagao, M. Kurosaki, H. Ochi
Recently, wireless technology experiences a fast growth to meet user demand and push toward the boundary limit of system performance. The simulation and verification framework play important role for accelerating investigation of technology proof of concept, field-trial, and large-scale commercial prototyping. In this paper, we present system-level simulation of heterogeneous model and unified HW/SW framework, particularly for next generation wireless system. The proposed framework includes a unified HW/SW co-evaluation methodology, the flexible HW/SW architecture, and fast HW/SW co-evaluation. The co-evaluation is carried out by employing hardware-in-the loop scheme that covers various abstraction level of simulation, from algorithm-level into physical-level simulation, with respect to system level simulation. The proposed co-verification framework allows a comprehensive system evaluation for a wireless system, involving various system parameters, hardware impairments, different channel conditions and cross-layer evaluations with fast run-time evaluations. Additionally, we also show an application example of multi-user wireless communication system and its experimental evaluations.
{"title":"A unified HW/SW system-level simulation framework for next generation wireless system","authors":"N. Sutisna, L. Lanante, Y. Nagao, M. Kurosaki, H. Ochi","doi":"10.1109/SOCC.2017.8226070","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226070","url":null,"abstract":"Recently, wireless technology experiences a fast growth to meet user demand and push toward the boundary limit of system performance. The simulation and verification framework play important role for accelerating investigation of technology proof of concept, field-trial, and large-scale commercial prototyping. In this paper, we present system-level simulation of heterogeneous model and unified HW/SW framework, particularly for next generation wireless system. The proposed framework includes a unified HW/SW co-evaluation methodology, the flexible HW/SW architecture, and fast HW/SW co-evaluation. The co-evaluation is carried out by employing hardware-in-the loop scheme that covers various abstraction level of simulation, from algorithm-level into physical-level simulation, with respect to system level simulation. The proposed co-verification framework allows a comprehensive system evaluation for a wireless system, involving various system parameters, hardware impairments, different channel conditions and cross-layer evaluations with fast run-time evaluations. Additionally, we also show an application example of multi-user wireless communication system and its experimental evaluations.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126457207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226082
György Rácz, P. Arató
Multiprocessing can be considered the most characteristic common property of complex digital systems. Due to the more and more complex tasks to be solved for fulfilling often conflicting requirements (cost, speed, energy and communication efficiency, pipelining, parallelism, the number of component processors, etc.), the so called heterogeneous multiprocessor architectures (HMPA) have become unavoidable. The component processors of such systems may be not only general purpose CPUs or cores, but also DSPs, GPUs, FPGAs and other custom hardware components as well. The hierarchy of the component processors and the data transfer organization between them are strongly determined by the task to be solved and by the priority order of the requirements to be fulfilled. For each component processor of HMPAs, a subtask must be defined based on the requirements and their priority orders. The definition of the subtasks, i.e. the decomposition of the task influences strongly the cost and performance of the whole system. Therefore, comparing and evaluating the effects of different task decompositions performed by applying systematic algorithms may help the designer to approach the optimal decisions in the system level synthesis phase. For this purpose, the paper presents a novel method based on combining the decomposition and the modified high level synthesis algorithms. The application of the method is illustrated on redesigning and evaluating in some versions of a high performance embedded multiprocessing system.
{"title":"A decomposition-based system level synthesis method for heterogeneous multiprocessor architectures","authors":"György Rácz, P. Arató","doi":"10.1109/SOCC.2017.8226082","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226082","url":null,"abstract":"Multiprocessing can be considered the most characteristic common property of complex digital systems. Due to the more and more complex tasks to be solved for fulfilling often conflicting requirements (cost, speed, energy and communication efficiency, pipelining, parallelism, the number of component processors, etc.), the so called heterogeneous multiprocessor architectures (HMPA) have become unavoidable. The component processors of such systems may be not only general purpose CPUs or cores, but also DSPs, GPUs, FPGAs and other custom hardware components as well. The hierarchy of the component processors and the data transfer organization between them are strongly determined by the task to be solved and by the priority order of the requirements to be fulfilled. For each component processor of HMPAs, a subtask must be defined based on the requirements and their priority orders. The definition of the subtasks, i.e. the decomposition of the task influences strongly the cost and performance of the whole system. Therefore, comparing and evaluating the effects of different task decompositions performed by applying systematic algorithms may help the designer to approach the optimal decisions in the system level synthesis phase. For this purpose, the paper presents a novel method based on combining the decomposition and the modified high level synthesis algorithms. The application of the method is illustrated on redesigning and evaluating in some versions of a high performance embedded multiprocessing system.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"505 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125500658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226033
T. Le, R. Ning, Dan Zhao, Hongyi Wu, M. Bayoumi
Current hybrid network-on-chip designs in manycore systems are agnostic to the application requirements and thus are provided for general cases. This results in high cost in the manycore systems design, wasted energy and performance. We observe that the cost of network-on-chip designs can be reduced by optimizing the application-specific traffic onto the system. This paper presents mincostflow-based heuristic algorithm (LINCA) that minimizes the quantification of hybrid routers corresponding to the application-specific traffic for manycore systems. LINCA guarantees the performance of hybrid networks on chip. Its results are validated against the manycore system architecture. Our evaluations show that LINCA can reduce significant cost of using hybrid routers in the manycore systems. It reduces cost by 84 percent on average across a variety of applications, compared with all of hybrid routers being deployed in the network without using optimization model.
{"title":"Optimizing the heterogeneous network on-chip design in manycore architectures","authors":"T. Le, R. Ning, Dan Zhao, Hongyi Wu, M. Bayoumi","doi":"10.1109/SOCC.2017.8226033","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226033","url":null,"abstract":"Current hybrid network-on-chip designs in manycore systems are agnostic to the application requirements and thus are provided for general cases. This results in high cost in the manycore systems design, wasted energy and performance. We observe that the cost of network-on-chip designs can be reduced by optimizing the application-specific traffic onto the system. This paper presents mincostflow-based heuristic algorithm (LINCA) that minimizes the quantification of hybrid routers corresponding to the application-specific traffic for manycore systems. LINCA guarantees the performance of hybrid networks on chip. Its results are validated against the manycore system architecture. Our evaluations show that LINCA can reduce significant cost of using hybrid routers in the manycore systems. It reduces cost by 84 percent on average across a variety of applications, compared with all of hybrid routers being deployed in the network without using optimization model.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"23 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131725885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226004
M. K. Adimulam, K. K. Movva, M. Srinivas
This paper presents a low power programmable 12-bit Two Step successive approximation register (SAR) — Flash analog-to-digital converter architecture for communication and bio-potential signal processing applications. The proposed ADC consists of two identical 6-bit SAR-Flash analog-to-digital converter (ADC) stages combined with a pipelined inter-stage gain amplifier to improve performance, reduce area, and power consumption. The 6-bit SAR-Flash ADC stage consists of low power and high performance 3-bit SAR ADC and 3-bit flash ADC. The proposed ADC architecture results are compared with recent conventional SAR ADCs and hybrid ADCs at different sampling frequencies. The ADC is designed in 90nm standard CMOS process occupies 0.1225 mm2 area. The performance parameters of the proposed ADC design are found to be differential nonlinearity (DNL) of ±0.28 LSB, integral non-linearity (INL) of ±0.52 LSB, signal-to-noise-and-distortion ratio (SNDR) of 67.4 dB, spurious-free dynamic range (SFDR) of 79.6 dB, and effective number of bits (ENOB) of 10.9 bits with input frequency of 15 MHz @ 200 MS/s sampling frequency at 1.0 V supply voltage. The power consumption of the ADC at lower sampling frequency at 500 KS/s is 1.47 pW and at 200 MS/s it is 1.35 mW.
{"title":"A low power, programmable 12-bit two step SAR-flash ADC for signal processing applications","authors":"M. K. Adimulam, K. K. Movva, M. Srinivas","doi":"10.1109/SOCC.2017.8226004","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226004","url":null,"abstract":"This paper presents a low power programmable 12-bit Two Step successive approximation register (SAR) — Flash analog-to-digital converter architecture for communication and bio-potential signal processing applications. The proposed ADC consists of two identical 6-bit SAR-Flash analog-to-digital converter (ADC) stages combined with a pipelined inter-stage gain amplifier to improve performance, reduce area, and power consumption. The 6-bit SAR-Flash ADC stage consists of low power and high performance 3-bit SAR ADC and 3-bit flash ADC. The proposed ADC architecture results are compared with recent conventional SAR ADCs and hybrid ADCs at different sampling frequencies. The ADC is designed in 90nm standard CMOS process occupies 0.1225 mm2 area. The performance parameters of the proposed ADC design are found to be differential nonlinearity (DNL) of ±0.28 LSB, integral non-linearity (INL) of ±0.52 LSB, signal-to-noise-and-distortion ratio (SNDR) of 67.4 dB, spurious-free dynamic range (SFDR) of 79.6 dB, and effective number of bits (ENOB) of 10.9 bits with input frequency of 15 MHz @ 200 MS/s sampling frequency at 1.0 V supply voltage. The power consumption of the ADC at lower sampling frequency at 500 KS/s is 1.47 pW and at 200 MS/s it is 1.35 mW.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129686903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8225986
R. Wille, Bing Li
In the recent years, microfluidic technology has paved the way for so-called Labs-on-Chips (LoCs) — a convenient and cost-effective way to conduct biochemical, biological, or medical experiments. Instead of conducting tests manually in a fully equipped lab using up lab equipment and human resources, LoCs allow us to conduct biochemical and medical experiments on a small chip. This requires much smaller sample/reagent volumes and allows for a significantly higher throughput.
{"title":"Design automation for Labs-on-Chip: A new “playground” for SoC designers","authors":"R. Wille, Bing Li","doi":"10.1109/SOCC.2017.8225986","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8225986","url":null,"abstract":"In the recent years, microfluidic technology has paved the way for so-called Labs-on-Chips (LoCs) — a convenient and cost-effective way to conduct biochemical, biological, or medical experiments. Instead of conducting tests manually in a fully equipped lab using up lab equipment and human resources, LoCs allow us to conduct biochemical and medical experiments on a small chip. This requires much smaller sample/reagent volumes and allows for a significantly higher throughput.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134211694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226042
Ching-Yuan Yang, Jen-Yan Huang, Jun-Hong Weng
A monolithic CMOS DC-DC converter with integrated power switches and a novel variable-frequency boundary conduction mode for feedback control is presented in this paper. Implemented in a 0.18-um CMOS technology, the operating frequency is from 90 kHz to 500 kHz and the power efficiency can achieve 92.6%. The total area including I/O pads is 1.1mm × 1.15mm.
本文提出了一种集成功率开关的单片CMOS DC-DC变换器，并采用了一种新的变频边界传导方式进行反馈控制。采用0.18 um CMOS技术实现，工作频率为90 kHz ~ 500 kHz，功率效率可达92.6%。包括I/O焊盘在内的总面积为1.1mm × 1.15mm。
{"title":"Realization of buck converter with adaptive variable-frequency control","authors":"Ching-Yuan Yang, Jen-Yan Huang, Jun-Hong Weng","doi":"10.1109/SOCC.2017.8226042","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226042","url":null,"abstract":"A monolithic CMOS DC-DC converter with integrated power switches and a novel variable-frequency boundary conduction mode for feedback control is presented in this paper. Implemented in a 0.18-um CMOS technology, the operating frequency is from 90 kHz to 500 kHz and the power efficiency can achieve 92.6%. The total area including I/O pads is 1.1mm × 1.15mm.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116163658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226043
M. Habibzadeh, Moeen Hassanalieragh, T. Soyata, Gaurav Sharma
Off-grid medium-power (1–10 W) systems require either battery-or supercapacitor-based ambient energy harvesting for sustaining their operation. Supercapacitor-based harvesters are advantageous in autonomous field systems due to their extended lifetime, easy power management, and low maintenance requirement; however, they can reach only up to 10% of the energy density of rechargeable batteries. To overcome this energy density challenge, hybrid power sources, such as solar or wind, can be advantageously utilized in harvesting systems. The complementary power supply characteristics of solar and wind can substantially reduce the required supercapacitor buffer size compared with solar-only or wind-only systems. In the literature, no supercapacitor-based hybrid harvesting system design exists for 1–10 W range. In this paper, we develop and experimentally validate three different categories of supercapacitor-based harvesting systems that are capable of simultaneously harvesting solar/wind (hybrid) power sources.
{"title":"Supercapacitor-based embedded hybrid solar/wind harvesting system architectures","authors":"M. Habibzadeh, Moeen Hassanalieragh, T. Soyata, Gaurav Sharma","doi":"10.1109/SOCC.2017.8226043","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226043","url":null,"abstract":"Off-grid medium-power (1–10 W) systems require either battery-or supercapacitor-based ambient energy harvesting for sustaining their operation. Supercapacitor-based harvesters are advantageous in autonomous field systems due to their extended lifetime, easy power management, and low maintenance requirement; however, they can reach only up to 10% of the energy density of rechargeable batteries. To overcome this energy density challenge, hybrid power sources, such as solar or wind, can be advantageously utilized in harvesting systems. The complementary power supply characteristics of solar and wind can substantially reduce the required supercapacitor buffer size compared with solar-only or wind-only systems. In the literature, no supercapacitor-based hybrid harvesting system design exists for 1–10 W range. In this paper, we develop and experimentally validate three different categories of supercapacitor-based harvesting systems that are capable of simultaneously harvesting solar/wind (hybrid) power sources.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133100520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226036
Sri Navaneeth Easwaran, Samir Camdzic, R. Weigel
Power Semiconductor devices used for high voltage, high current applications dissipate lot of power thereby rapidly increasing their junction temperature to levels beyond which no SPICE (Simulation Program with Integrated Circuit Emphasis) models exist. In this paper, the design of an integrated four channel squib driver SOC (System on Chip) with four High Side (HS) drivers and four Low Side (LS) drivers is presented. 98mJ energy limited current regulating High Side (HS) driver needs the temperature information from the electro-thermal simulators like FloTHERM during the design to ensure that the powerFET operates within the thermal SOA (Safe Operating Area) without area penalty. Despite SPICE model restrictions to 200°C, this paper explains how the current regulation loop architecture is chosen to operate at peak temperatures of 400°C. The Thermal simulation results aid in the optimization of the layout of the gate-driver. Apart from the robust design, additional design measures to prevent inadvertent turn ON of the FETs and reverse protection for safety are discussed. This circuit was successfully implemented in a 40V, 0.35pm, BiCMOS process on a 4 channel airbag squib driver IC.
{"title":"Thermal simulation aided 98mJ integrated high side and low side drivers design for safety SOCs","authors":"Sri Navaneeth Easwaran, Samir Camdzic, R. Weigel","doi":"10.1109/SOCC.2017.8226036","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226036","url":null,"abstract":"Power Semiconductor devices used for high voltage, high current applications dissipate lot of power thereby rapidly increasing their junction temperature to levels beyond which no SPICE (Simulation Program with Integrated Circuit Emphasis) models exist. In this paper, the design of an integrated four channel squib driver SOC (System on Chip) with four High Side (HS) drivers and four Low Side (LS) drivers is presented. 98mJ energy limited current regulating High Side (HS) driver needs the temperature information from the electro-thermal simulators like FloTHERM during the design to ensure that the powerFET operates within the thermal SOA (Safe Operating Area) without area penalty. Despite SPICE model restrictions to 200°C, this paper explains how the current regulation loop architecture is chosen to operate at peak temperatures of 400°C. The Thermal simulation results aid in the optimization of the layout of the gate-driver. Apart from the robust design, additional design measures to prevent inadvertent turn ON of the FETs and reverse protection for safety are discussed. This circuit was successfully implemented in a 40V, 0.35pm, BiCMOS process on a 4 channel airbag squib driver IC.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133101009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226017
I. Polian, F. Regazzoni, Martha Johanna Sepúlveda
Novel applications demand computational resources that are provided by multiprocessor systems-on-chip (MPSoCs). At the same time, they increasingly process sensitive data and incorporate security-relevant functions like encryption or authentication. This paper discusses the implications of the MPSoC technology on security. It provides an overview of hardware-oriented techniques to enhance security (such as on-chip cryptographic key generation and hardware-supported software attestation), but also lists hardware-related threats and potential security loopholes, which designers of MPSoCs and MPSoC-based systems should be aware of.
{"title":"Introduction to hardware-oriented security for MPSoCs","authors":"I. Polian, F. Regazzoni, Martha Johanna Sepúlveda","doi":"10.1109/SOCC.2017.8226017","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226017","url":null,"abstract":"Novel applications demand computational resources that are provided by multiprocessor systems-on-chip (MPSoCs). At the same time, they increasingly process sensitive data and incorporate security-relevant functions like encryption or authentication. This paper discusses the implications of the MPSoC technology on security. It provides an overview of hardware-oriented techniques to enhance security (such as on-chip cryptographic key generation and hardware-supported software attestation), but also lists hardware-related threats and potential security loopholes, which designers of MPSoCs and MPSoC-based systems should be aware of.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124913821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8225980
T. Leyrer
The digital revolution in manufacturing process demand a communication standard which meets the requirements of the manufacturing floor. Additional sensing technology for predictive maintenance add new quality of service requirements to the industrial network. Managing different communication requirements for motion control, programmable logic control and predictive maintenance is the key challenge of applying IEEE Time Sensitive Network (TSN) standard to the trends in industrial automation market.
{"title":"Time sensitive networks for industry 4.0","authors":"T. Leyrer","doi":"10.1109/SOCC.2017.8225980","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8225980","url":null,"abstract":"The digital revolution in manufacturing process demand a communication standard which meets the requirements of the manufacturing floor. Additional sensing technology for predictive maintenance add new quality of service requirements to the industrial network. Managing different communication requirements for motion control, programmable logic control and predictive maintenance is the key challenge of applying IEEE Time Sensitive Network (TSN) standard to the trends in industrial automation market.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125005094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：