Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226008
Muhammad Obaidullah, G. Khan
Network-on-Chip (NoC) has been proposed as an interconnection framework for connecting large number of cores for a System-on-Chip (SoC). Assuming a mesh-based NoC, we explore the assignment of cores to cross-points and produce a best NoC configuration with minimum average communication traffic, power consumption and chip area. We use pre-synthesized network components data to estimate power and chip area of the NoC. NoC configuration and mapping problem belongs to NP-hard complexity set, therefore we propose a hybrid scheme of swarm optimization that combines Tabu-search, force-directed swapping, sub-swarms, and Discrete Particle Swarm Optimization (DPSO). The main goal of the optimization is to configure the NoC such that the total NoC latency, power consumption, and area occupied are minimal. DPSO is used as the main optimization scheme and modified so that each particle move is also influenced by a force derived from the NoC traffic matrix. The methodology is tested for some multimedia application core graphs as well as large network of randomly generated cores. It is determined that on average our hybrid technique required less number of iterations and time to reach an optimal solution when compared with existing NoC synthesis algorithms.
{"title":"Hybrid multi-swarm optimization based NoC synthesis","authors":"Muhammad Obaidullah, G. Khan","doi":"10.1109/SOCC.2017.8226008","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226008","url":null,"abstract":"Network-on-Chip (NoC) has been proposed as an interconnection framework for connecting large number of cores for a System-on-Chip (SoC). Assuming a mesh-based NoC, we explore the assignment of cores to cross-points and produce a best NoC configuration with minimum average communication traffic, power consumption and chip area. We use pre-synthesized network components data to estimate power and chip area of the NoC. NoC configuration and mapping problem belongs to NP-hard complexity set, therefore we propose a hybrid scheme of swarm optimization that combines Tabu-search, force-directed swapping, sub-swarms, and Discrete Particle Swarm Optimization (DPSO). The main goal of the optimization is to configure the NoC such that the total NoC latency, power consumption, and area occupied are minimal. DPSO is used as the main optimization scheme and modified so that each particle move is also influenced by a force derived from the NoC traffic matrix. The methodology is tested for some multimedia application core graphs as well as large network of randomly generated cores. It is determined that on average our hybrid technique required less number of iterations and time to reach an optimal solution when compared with existing NoC synthesis algorithms.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123077202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226003
Javed S. Gaggatur, Gaurab Banerjee
An integrated capacitance sensor interface is proposed with three programmable gain stages to measure femto-farad capacitance. The capacitance sensor interface is a differential measurement set-up to measure the change in capacitance over a fixed nominal capacitance. The programmable gain stages are used to change the gain settings to operate for a wide-range capacitance measurement. The implemented continuous time ΣΔ ADC is a third-order cascade of integrators feedforward topology with a signal bandwidth of 10 kHz. The ADC has a measured peak dynamic range of 84.5 dB while consuming 1.6 mW. The measured figure of merit (FoM) is 3.107 pJ-mm2/conversion at a clock frequency of 6.4 MHz having an active area of 0.45 mm2. The ADC was applied in the femto-farad capacitance measurement using a 0.3 pF–1.2 pF variable capacitor typically encountered in MEMS-based sensor applications like pressure/humidity/flow sensing in System-in-Package (SiP) or Systems-on-Chip (SoC).
{"title":"A 13.5 bit 1.6 mW 3rd order CT ΣΔ ADC for integrated capacitance sensor interface","authors":"Javed S. Gaggatur, Gaurab Banerjee","doi":"10.1109/SOCC.2017.8226003","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226003","url":null,"abstract":"An integrated capacitance sensor interface is proposed with three programmable gain stages to measure femto-farad capacitance. The capacitance sensor interface is a differential measurement set-up to measure the change in capacitance over a fixed nominal capacitance. The programmable gain stages are used to change the gain settings to operate for a wide-range capacitance measurement. The implemented continuous time ΣΔ ADC is a third-order cascade of integrators feedforward topology with a signal bandwidth of 10 kHz. The ADC has a measured peak dynamic range of 84.5 dB while consuming 1.6 mW. The measured figure of merit (FoM) is 3.107 pJ-mm2/conversion at a clock frequency of 6.4 MHz having an active area of 0.45 mm2. The ADC was applied in the femto-farad capacitance measurement using a 0.3 pF–1.2 pF variable capacitor typically encountered in MEMS-based sensor applications like pressure/humidity/flow sensing in System-in-Package (SiP) or Systems-on-Chip (SoC).","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126621837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226031
Ahmed Y. Ginawi, R. Gauthier, T. Xia
Diode-triggered silicon-controlled rectifier (DT-SCR) devices protect sensitive circuit nodes, such as high-frequency analog circuits and thin-gate complementary metal-oxide semiconductor (CMOS) circuits with high-speed input [1]. Reducing the turn-on time and overshoot voltage enhances the use of a DTSCR device in high-speed applications. We analyze the two lateral bipolar devices found in CMOS based process SCRS to improve the overall DTSCR turn-on time during an electrostatic discharge (ESD) event. We use technology computer-aided design (TCAD) device-level simulations to accurately predict the turn-on time of these parasitic bipolar devices in a 32nm CMOS technology.
{"title":"Investigation of diode triggered silicon control rectifier turn-on time during ESD events","authors":"Ahmed Y. Ginawi, R. Gauthier, T. Xia","doi":"10.1109/SOCC.2017.8226031","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226031","url":null,"abstract":"Diode-triggered silicon-controlled rectifier (DT-SCR) devices protect sensitive circuit nodes, such as high-frequency analog circuits and thin-gate complementary metal-oxide semiconductor (CMOS) circuits with high-speed input [1]. Reducing the turn-on time and overshoot voltage enhances the use of a DTSCR device in high-speed applications. We analyze the two lateral bipolar devices found in CMOS based process SCRS to improve the overall DTSCR turn-on time during an electrostatic discharge (ESD) event. We use technology computer-aided design (TCAD) device-level simulations to accurately predict the turn-on time of these parasitic bipolar devices in a 32nm CMOS technology.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"9 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120985608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226024
Dongjoo Shin, Youchang Kim, H. Yoo
An on-chip/off-chip hybrid transposition table (TT) is proposed to implement artificial intelligence functions in mobile platforms. In order to meet the power consumption and throughput requirements for realizing the intelligence functions in real-time, the TT is playing a key role to prevent the duplicated evaluations in a tree search by storing search results. Three key features, 1) On-chip/off-chip hybrid TT architecture, 2) On-chip buffer cache, and 3) Progress-based entry replacement policy, are proposed to overcome the design challenges (hit rate, latency and off-chip bandwidth) for implementing the TT. The proposed hybrid TT is fabricated in a 65nm CMOS technology, and achieves 35% hit ratio and 220ns latency with only 1.41mW power consumption and 2.9MB/s off-chip memory bandwidth.
{"title":"A 1.41mW on-chip/off-chip hybrid transposition table for low-power robust deep tree search in artificial intelligence SoCs","authors":"Dongjoo Shin, Youchang Kim, H. Yoo","doi":"10.1109/SOCC.2017.8226024","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226024","url":null,"abstract":"An on-chip/off-chip hybrid transposition table (TT) is proposed to implement artificial intelligence functions in mobile platforms. In order to meet the power consumption and throughput requirements for realizing the intelligence functions in real-time, the TT is playing a key role to prevent the duplicated evaluations in a tree search by storing search results. Three key features, 1) On-chip/off-chip hybrid TT architecture, 2) On-chip buffer cache, and 3) Progress-based entry replacement policy, are proposed to overcome the design challenges (hit rate, latency and off-chip bandwidth) for implementing the TT. The proposed hybrid TT is fabricated in a 65nm CMOS technology, and achieves 35% hit ratio and 220ns latency with only 1.41mW power consumption and 2.9MB/s off-chip memory bandwidth.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121457590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8225992
Ron Martino
Electronic innovation is becoming increasingly important in the evolution of our society. Noble goals of extending lives with improved medical capabilities, eliminating auto fatalities, and creating a connected infrastructure around the “Internet of Things” all center on electronic innovation. These goals are being driven by both legislation and consumer demand, which is leading to accelerated system challenges. New system solutions are requiring the integration of disparate functional blocks, high levels of optimization for energy efficiency and scaling across a large dynamic range of performance. A central focus in this evolution is the enhancements to the human-machine-interface (HMI), enabling seamless interactions between humans and machines. Multimedia applications processors are playing a critical role in introducing solutions with multisensory capabilities such as natural language recognition, vision detection and augmentation of reality through enhanced display functionality. We will explore HMI trends in multiple applications and discuss how FD-SOI technology, novel applications processor architectures, integrated circuit module development and system-on-chip integration create safe and secure systems.
{"title":"Wednesday keynote II: Advanced technology for automotive cockpits, industrial human-machine-interface and IoT systems — Optimization of technology — Architecture — Design","authors":"Ron Martino","doi":"10.1109/SOCC.2017.8225992","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8225992","url":null,"abstract":"Electronic innovation is becoming increasingly important in the evolution of our society. Noble goals of extending lives with improved medical capabilities, eliminating auto fatalities, and creating a connected infrastructure around the “Internet of Things” all center on electronic innovation. These goals are being driven by both legislation and consumer demand, which is leading to accelerated system challenges. New system solutions are requiring the integration of disparate functional blocks, high levels of optimization for energy efficiency and scaling across a large dynamic range of performance. A central focus in this evolution is the enhancements to the human-machine-interface (HMI), enabling seamless interactions between humans and machines. Multimedia applications processors are playing a critical role in introducing solutions with multisensory capabilities such as natural language recognition, vision detection and augmentation of reality through enhanced display functionality. We will explore HMI trends in multiple applications and discuss how FD-SOI technology, novel applications processor architectures, integrated circuit module development and system-on-chip integration create safe and secure systems.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125206445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226046
Cheng Zhuo, Bei Yu, Di Gao
At sub-22nm regime, chip designs have to go through hundreds to thousands of steps and tasks before shipment. Many tasks are data and simulation intensive, thereby demanding significant amount of resources and time. Unlike conventional methodologies relying on experiences to manually handle data and extract models, recent advances in machine learning techniques enable the successful applications in various complex tasks to accelerate modern chip designs, ranging from pre-silicon verification to post-silicon validation and tuning. The goals are to reduce the amount of time and efforts to process and understand data through automatic and effective learning and enhancing from examples. In this paper we review and discuss several application cases of machine learning techniques, including pre-silicon hotspot detection through classification, post-silicon variation extraction and bug localization through inference, and post-silicon timing tuning through iterative learning and optimization, so as to leverage the potentials and inspire more future innovations.
{"title":"Accelerating chip design with machine learning: From pre-silicon to post-silicon","authors":"Cheng Zhuo, Bei Yu, Di Gao","doi":"10.1109/SOCC.2017.8226046","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226046","url":null,"abstract":"At sub-22nm regime, chip designs have to go through hundreds to thousands of steps and tasks before shipment. Many tasks are data and simulation intensive, thereby demanding significant amount of resources and time. Unlike conventional methodologies relying on experiences to manually handle data and extract models, recent advances in machine learning techniques enable the successful applications in various complex tasks to accelerate modern chip designs, ranging from pre-silicon verification to post-silicon validation and tuning. The goals are to reduce the amount of time and efforts to process and understand data through automatic and effective learning and enhancing from examples. In this paper we review and discuss several application cases of machine learning techniques, including pre-silicon hotspot detection through classification, post-silicon variation extraction and bug localization through inference, and post-silicon timing tuning through iterative learning and optimization, so as to leverage the potentials and inspire more future innovations.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127715939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226077
Md Shahriar Shamim, M. Ahmed, N. Mansoor, A. Ganguly
Multichip systems with memory stacks and various processing chips are at the heart of platform based designs such as servers and embedded systems. Full utilization of the benefits of these integrated multichip systems need a seamless, and scalable in-package interconnection framework. However, state-of-the-art inter-chip communication requires long wireline channels which increases energy consumption and latency while decreasing data bandwidth. Here, we propose the design of an energy-efficient, seamless wireless interconnection network for multichip systems. We demonstrate with cycle-accurate simulations that such a design reduces the energy consumption and latency while increasing the bandwidth in comparison to modern multichip integration systems.
{"title":"Energy-efficient wireless interconnection framework for multichip systems with in-package memory stacks","authors":"Md Shahriar Shamim, M. Ahmed, N. Mansoor, A. Ganguly","doi":"10.1109/SOCC.2017.8226077","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226077","url":null,"abstract":"Multichip systems with memory stacks and various processing chips are at the heart of platform based designs such as servers and embedded systems. Full utilization of the benefits of these integrated multichip systems need a seamless, and scalable in-package interconnection framework. However, state-of-the-art inter-chip communication requires long wireline channels which increases energy consumption and latency while decreasing data bandwidth. Here, we propose the design of an energy-efficient, seamless wireless interconnection network for multichip systems. We demonstrate with cycle-accurate simulations that such a design reduces the energy consumption and latency while increasing the bandwidth in comparison to modern multichip integration systems.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134090182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226040
J. Hausner
As mobile broadband (MBB) technologies evolve, devices need to support increasing bandwidth with multiple frequencies and dramatically exploding data rates. New air interfaces in 5G will show once again the gain in data rates as we have seen from 2G, to 3G to HSPA, to LTE and LTE advanced. These technologies in a single device provide the best possible services with great user experience to all people no matter where they are. Developing the next generation takes advantage of higher density in analog and digital silicon circuitry to enable low cost high performance solutions. Next to those MBB systems, massive and reliable machine-type communications — also known as the Internet of Things — will get developed under the umbrella of 5G technologies. This talk will elaborate on challenges of related radio and semiconductor technologies, and highlight architectural breakthroughs to enable next generation solutions for global connectivity.
{"title":"The path to global connectivity — Wireless communication enters the next generation","authors":"J. Hausner","doi":"10.1109/SOCC.2017.8226040","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226040","url":null,"abstract":"As mobile broadband (MBB) technologies evolve, devices need to support increasing bandwidth with multiple frequencies and dramatically exploding data rates. New air interfaces in 5G will show once again the gain in data rates as we have seen from 2G, to 3G to HSPA, to LTE and LTE advanced. These technologies in a single device provide the best possible services with great user experience to all people no matter where they are. Developing the next generation takes advantage of higher density in analog and digital silicon circuitry to enable low cost high performance solutions. Next to those MBB systems, massive and reliable machine-type communications — also known as the Internet of Things — will get developed under the umbrella of 5G technologies. This talk will elaborate on challenges of related radio and semiconductor technologies, and highlight architectural breakthroughs to enable next generation solutions for global connectivity.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114806538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226010
Praveen Kumar, Alexander Fell, Sachin Mathur
Achieving optimal floor-plans during the physical synthesis flow is an iterative and resource intensive process and its quality has a significant impact on subsequent synthesis stages in terms of runtime and quality of results. This problem intensifies due the abundance of macros in advance technology nodes which poses challenges in the physical design flow, especially in the floor-plan stage. It has resulted in an excessive number of channels among macros that need to be spaced carefully and optimized as they consume placement and routing resources. The work presented here is two-fold: First, a tool is introduced for automatic channel space adjustment. Second, the impact of channel space minimization on the quality of results along with runtimes are investigated. Experimental results for two complex partitions of a taped out design, Design-A and Design-B, each with 3M instances including 225 and 205 macros respectively, are presented. The results indicate an existence of an optimum channel spacing in which a 35% and 124% reduction in turn-around-time is observed with same or better quality of results, when compared to the taped out version of the same.
{"title":"Automated, inter-macro channel space adjustment and optimization for faster design closure","authors":"Praveen Kumar, Alexander Fell, Sachin Mathur","doi":"10.1109/SOCC.2017.8226010","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226010","url":null,"abstract":"Achieving optimal floor-plans during the physical synthesis flow is an iterative and resource intensive process and its quality has a significant impact on subsequent synthesis stages in terms of runtime and quality of results. This problem intensifies due the abundance of macros in advance technology nodes which poses challenges in the physical design flow, especially in the floor-plan stage. It has resulted in an excessive number of channels among macros that need to be spaced carefully and optimized as they consume placement and routing resources. The work presented here is two-fold: First, a tool is introduced for automatic channel space adjustment. Second, the impact of channel space minimization on the quality of results along with runtimes are investigated. Experimental results for two complex partitions of a taped out design, Design-A and Design-B, each with 3M instances including 225 and 205 macros respectively, are presented. The results indicate an existence of an optimum channel spacing in which a 35% and 124% reduction in turn-around-time is observed with same or better quality of results, when compared to the taped out version of the same.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122510896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226022
R. García-Ramírez, A. Chacón-Rodríguez, R. Rímolo-Donadío
The design of an electrical impedance spectroscopy acquisition and processing system using a 0.13 μm CMOS technology with a 1kHz to 10 GHz functional frequency range is presented. The system is based on a quadrature modulator in a lock-in architecture. The design of each one of the modules of the system is explained, and post-layout simulations are used to validate the main features of the design such as frequency response, gain, noise, linearity, and error characterization.
{"title":"A 0.13 CMOS integrated circuit for electrical impedance spectroscopy from 1 kHz to 10 GHz","authors":"R. García-Ramírez, A. Chacón-Rodríguez, R. Rímolo-Donadío","doi":"10.1109/SOCC.2017.8226022","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226022","url":null,"abstract":"The design of an electrical impedance spectroscopy acquisition and processing system using a 0.13 μm CMOS technology with a 1kHz to 10 GHz functional frequency range is presented. The system is based on a quadrature modulator in a lock-in architecture. The design of each one of the modules of the system is explained, and post-layout simulations are used to validate the main features of the design such as frequency response, gain, noise, linearity, and error characterization.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125347278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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