Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226053
Wei-Lun Ou, Yu-Kai Tsai, Po-Yen Tseng, Liang-Hung Lu
A 2.4-GHz dual-mode power amplifier with transistor resizing is proposed. The proposed technique keeps the conductance for optimum power-matching constant in both modes. By introducing transformers and capacitors, the 50-ohm load is matched to near-optimal impedances for size-scaling MOS transistors. Using a 0.18-pm CMOS process, the proposed PA demonstrates a PAE enhancement of 2.7×/2.3× respectively at 6.5-dB/9-dB transmitting power back-off.
提出了一种可调整晶体管尺寸的2.4 ghz双模功率放大器。该方法在两种模式下均保持电导恒定以达到最佳功率匹配。通过引入变压器和电容器，50欧姆负载匹配到接近最佳阻抗的尺寸MOS晶体管。采用0.18 pm CMOS工艺，在6.5 db /9 db发射功率下，所提出的PA的PAE分别提高了2.7倍/2.3倍。
{"title":"A 2.4-GHz dual-mode resizing power amplifier with a constant conductance output matching","authors":"Wei-Lun Ou, Yu-Kai Tsai, Po-Yen Tseng, Liang-Hung Lu","doi":"10.1109/SOCC.2017.8226053","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226053","url":null,"abstract":"A 2.4-GHz dual-mode power amplifier with transistor resizing is proposed. The proposed technique keeps the conductance for optimum power-matching constant in both modes. By introducing transformers and capacitors, the 50-ohm load is matched to near-optimal impedances for size-scaling MOS transistors. Using a 0.18-pm CMOS process, the proposed PA demonstrates a PAE enhancement of 2.7×/2.3× respectively at 6.5-dB/9-dB transmitting power back-off.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130114583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226076
A. Nannarelli
In this work, we present a radix-16 multi-format multiplier to multiply 64-bit unsigned integer operands, double-precision and single-precision operands. The multiplier is sectioned in two lanes such that two single-precision multiplications can be computed in parallel. Radix-16 is chosen for the reduced number of partial products and the resulting power savings. The experimental results show that high power efficiency is obtained by issuing two single-precision multiplications per cycle. Moreover, by converting the double-precision numbers which fit to single-precision, further energy can be saved.
{"title":"A multi-format floating-point multiplier for power-efficient operations","authors":"A. Nannarelli","doi":"10.1109/SOCC.2017.8226076","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226076","url":null,"abstract":"In this work, we present a radix-16 multi-format multiplier to multiply 64-bit unsigned integer operands, double-precision and single-precision operands. The multiplier is sectioned in two lanes such that two single-precision multiplications can be computed in parallel. Radix-16 is chosen for the reduced number of partial products and the resulting power savings. The experimental results show that high power efficiency is obtained by issuing two single-precision multiplications per cycle. Moreover, by converting the double-precision numbers which fit to single-precision, further energy can be saved.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"74 31","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134196947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8225996
V. Nautiyal, G. Singla, Lalita Gupta, S. Dwivedi, M. Kinkade
In recent times, graphic, audio and video definition has improved due to significant advancement in complex algorithms and video processing techniques. These techniques require heterogeneous and multi-core processors because of their complex computation abilities. Dual-port memories have become an essential component of CPUs because multi-core processors require significant data transfer. However, dual-port memories come at a cost of increased area and leakage. In this paper, an ultra-high-density dual-port SRAM (RADPUHD) architecture is proposed which addresses area and leakage challenges. It is designed and fabricated in 16nm technology. This paper presents use of a single-port bitcell to achieve functionality of dual-port SRAM thus improving area efficiency. The use of latches for Port B signals instead of full flip-flops further reduces area. The proposed design is a bolt-on wrapper around a 6T single-port SRAM. This design achieved a memory density of 8.1Mb/mm2 chip area and achieved 53% area savings and approximately 60% leakage savings when compared to an 8T dual-port SRAM that was also fabricated in 16nm. Silicon results show that the proposed circuit is functional down to a minimum operating voltage of 520mV.
{"title":"An ultra high density pseudo dual-port SRAM in 16nm FINFET process for graphics processors","authors":"V. Nautiyal, G. Singla, Lalita Gupta, S. Dwivedi, M. Kinkade","doi":"10.1109/SOCC.2017.8225996","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8225996","url":null,"abstract":"In recent times, graphic, audio and video definition has improved due to significant advancement in complex algorithms and video processing techniques. These techniques require heterogeneous and multi-core processors because of their complex computation abilities. Dual-port memories have become an essential component of CPUs because multi-core processors require significant data transfer. However, dual-port memories come at a cost of increased area and leakage. In this paper, an ultra-high-density dual-port SRAM (RADPUHD) architecture is proposed which addresses area and leakage challenges. It is designed and fabricated in 16nm technology. This paper presents use of a single-port bitcell to achieve functionality of dual-port SRAM thus improving area efficiency. The use of latches for Port B signals instead of full flip-flops further reduces area. The proposed design is a bolt-on wrapper around a 6T single-port SRAM. This design achieved a memory density of 8.1Mb/mm2 chip area and achieved 53% area savings and approximately 60% leakage savings when compared to an 8T dual-port SRAM that was also fabricated in 16nm. Silicon results show that the proposed circuit is functional down to a minimum operating voltage of 520mV.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"546 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123918708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226071
M. Bhanja, B. Ray
This paper presents a graph based synthesis procedure for reconfigurable linear analog function. A n-level weighted binary tree structure has been used to represent nth order linear network. Root of the binary tree has two children nodes with weights of first order lowpass filter (LPF) and first order highpass filter (HPF). Traversing through each possible path in the tree implements one filter type. The level 2 binary tree has been transformed to a hexagonal closed graph. This conversion has been done to map the proposed synthesis procedure into field programmable analog array (FPAA), which demonstrates the reusuability and programmability. First order LPF and HPF has been used as basic building blocks, whereas a hexagonal structure is denoted as a configurable analog block (CAB) of the FPAA. The hexagonal topology of the FPAA gives the versatile connectivity between two adjacent CABS of the FPAA. Performance has been verified through SPICE simulations.
{"title":"A graph based synthesis procedure for linear analog function","authors":"M. Bhanja, B. Ray","doi":"10.1109/SOCC.2017.8226071","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226071","url":null,"abstract":"This paper presents a graph based synthesis procedure for reconfigurable linear analog function. A n-level weighted binary tree structure has been used to represent nth order linear network. Root of the binary tree has two children nodes with weights of first order lowpass filter (LPF) and first order highpass filter (HPF). Traversing through each possible path in the tree implements one filter type. The level 2 binary tree has been transformed to a hexagonal closed graph. This conversion has been done to map the proposed synthesis procedure into field programmable analog array (FPAA), which demonstrates the reusuability and programmability. First order LPF and HPF has been used as basic building blocks, whereas a hexagonal structure is denoted as a configurable analog block (CAB) of the FPAA. The hexagonal topology of the FPAA gives the versatile connectivity between two adjacent CABS of the FPAA. Performance has been verified through SPICE simulations.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129159990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226069
H. Wei, C. King, Bhaskar Das, Mei-Chiao Peng, Chen-Chieh Wang, Hsun-Lun Huang, Juin-Ming Lu
Programmers depend on virtual platforms, such as Android-QEMU, to build and test their applications as well as system software for the ease of development efforts. It is easy to add tracing modules to the virtual platforms to dump the execution trace of the guest system, which can then be used to estimate and evaluate the performance of alternative system designs. However, tracing in virtual platforms are performed at the architecture level, which makes it difficult to generate traces for specific applications due to the lack of high-level software information. This problem becomes even more challenging for Android systems, which use component-based design strategies, where applications request services from other components. In this paper, we propose a novel Android-QEMU tracing system, which follows the invocations among the service components, generates component-service-aware traces only for specific applications. The evaluation results show that the proposed system improves 152% in simulation time and saves 33% of storage space in average compared to the static QEMU-Tracer.
{"title":"Application specific component-service-aware trace generation on Android-QEMU","authors":"H. Wei, C. King, Bhaskar Das, Mei-Chiao Peng, Chen-Chieh Wang, Hsun-Lun Huang, Juin-Ming Lu","doi":"10.1109/SOCC.2017.8226069","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226069","url":null,"abstract":"Programmers depend on virtual platforms, such as Android-QEMU, to build and test their applications as well as system software for the ease of development efforts. It is easy to add tracing modules to the virtual platforms to dump the execution trace of the guest system, which can then be used to estimate and evaluate the performance of alternative system designs. However, tracing in virtual platforms are performed at the architecture level, which makes it difficult to generate traces for specific applications due to the lack of high-level software information. This problem becomes even more challenging for Android systems, which use component-based design strategies, where applications request services from other components. In this paper, we propose a novel Android-QEMU tracing system, which follows the invocations among the service components, generates component-service-aware traces only for specific applications. The evaluation results show that the proposed system improves 152% in simulation time and saves 33% of storage space in average compared to the static QEMU-Tracer.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123357015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226020
Martha Johanna Sepúlveda, A. Zankl, Oliver Mischke
Public-key cryptography (PKC), widely used to protect communication in the Internet of Things (IoT), is the basis for establishing secured communication channels between multiple parties. The foreseeable breakthrough of quantum computers represents a risk for many PKC ecosystems. Almost all approaches in use today rely on the hardness of factoring large integers or computing (elliptic-curve) discrete logarithms. It is known that cryptography based on these problems can be broken in polynomial time by Shors algorithm, once a large enough quantum computer is built. In order to prepare for such an event, the integration of quantum-resistant cryptography on devices operating in the IoT is mandatory to achieve long-term security. Due to their limited resources, tight performance requirements and long-term life-cycles, this is especially challenging for Multi-Processor System-on-Chips (MPSoCs) operating in this context. At the same time, it must be provided that well-known implementation attacks, such as those targeting a cipher's execution time or its use of the processor cache, are inhibited, as they've successfully been used to attack cryptosystems in the pre-quantum era. Hence, this work presents an analysis of the security-critical polynomial multiplication routine within the NTRU algorithm and its susceptibility to timing and cache attacks. We also propose two different countermeasures to harden systems with or without caches against said attacks, and include the evaluation of the respective overheads. We demonstrate that security against timing and cache attacks can be achieved with reasonable overheads depending on the chosen parameters of NTRU.
{"title":"Cache attacks and countermeasures for NTRUEncrypt on MPSoCs: Post-quantum resistance for the IoT","authors":"Martha Johanna Sepúlveda, A. Zankl, Oliver Mischke","doi":"10.1109/SOCC.2017.8226020","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226020","url":null,"abstract":"Public-key cryptography (PKC), widely used to protect communication in the Internet of Things (IoT), is the basis for establishing secured communication channels between multiple parties. The foreseeable breakthrough of quantum computers represents a risk for many PKC ecosystems. Almost all approaches in use today rely on the hardness of factoring large integers or computing (elliptic-curve) discrete logarithms. It is known that cryptography based on these problems can be broken in polynomial time by Shors algorithm, once a large enough quantum computer is built. In order to prepare for such an event, the integration of quantum-resistant cryptography on devices operating in the IoT is mandatory to achieve long-term security. Due to their limited resources, tight performance requirements and long-term life-cycles, this is especially challenging for Multi-Processor System-on-Chips (MPSoCs) operating in this context. At the same time, it must be provided that well-known implementation attacks, such as those targeting a cipher's execution time or its use of the processor cache, are inhibited, as they've successfully been used to attack cryptosystems in the pre-quantum era. Hence, this work presents an analysis of the security-critical polynomial multiplication routine within the NTRU algorithm and its susceptibility to timing and cache attacks. We also propose two different countermeasures to harden systems with or without caches against said attacks, and include the evaluation of the respective overheads. We demonstrate that security against timing and cache attacks can be achieved with reasonable overheads depending on the chosen parameters of NTRU.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129153443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power density will stay a major challenge for the foreseeable future. Despite orders-of-magnitude-improved efficiency, power consumption per area is sharply rising, mainly due to the limits of voltage scaling. To investigate the physical implications of high power densities, we must distinguish between peak and average temperatures and temporal and spatial thermal gradients because they trigger circuit-aging mechanisms and eventually jeopardize the reliability of an on-chip system. The talk starts by presenting some basic interdependencies in the triangle of power density, circuit degradation and reliability and continues with some solutions to mitigate the problem via, among others, power density-aware resource management and efficient power budgeting.
{"title":"The triangle of power density, circuit degradation and reliability","authors":"J. Henkel, P. Montuschi","doi":"10.1109/MC.2017.214","DOIUrl":"https://doi.org/10.1109/MC.2017.214","url":null,"abstract":"Power density will stay a major challenge for the foreseeable future. Despite orders-of-magnitude-improved efficiency, power consumption per area is sharply rising, mainly due to the limits of voltage scaling. To investigate the physical implications of high power densities, we must distinguish between peak and average temperatures and temporal and spatial thermal gradients because they trigger circuit-aging mechanisms and eventually jeopardize the reliability of an on-chip system. The talk starts by presenting some basic interdependencies in the triangle of power density, circuit degradation and reliability and continues with some solutions to mitigate the problem via, among others, power density-aware resource management and efficient power budgeting.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131970645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-21DOI: 10.1109/SOCC.2017.8226044
Lucie Broyde, Kent W. Nixon, Xiang Chen, Hai Helen Li, Yiran Chen
Smartphones are becoming essential devices used for various types of applications in our daily life. To satisfy the ever-increasing performance requirement, the number of CPU cores in a phone keeps growing, which imposes a great impact on its power consumption. This work presents a series of analysis to understand how the current Android resource management policy adjusts CPU features. Our results indicate a significant improvement margin for CPU power efficiency in modern Android smartphones. We then propose MobiCore — a power-efficient CPU management scheme that can optimize the use of Dynamic and Frequency Voltage Scaling (DVFS) and the Dynamic Core Scaling (DCS) techniques with a sensitive control on CPU bandwidth. The measurements on the real systems prove that MobiCore can achieve substantial CPU power reduction compared to state-of-the-art architectures.
{"title":"MobiCore: An adaptive hybrid approach for power-efficient CPU management on Android devices","authors":"Lucie Broyde, Kent W. Nixon, Xiang Chen, Hai Helen Li, Yiran Chen","doi":"10.1109/SOCC.2017.8226044","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226044","url":null,"abstract":"Smartphones are becoming essential devices used for various types of applications in our daily life. To satisfy the ever-increasing performance requirement, the number of CPU cores in a phone keeps growing, which imposes a great impact on its power consumption. This work presents a series of analysis to understand how the current Android resource management policy adjusts CPU features. Our results indicate a significant improvement margin for CPU power efficiency in modern Android smartphones. We then propose MobiCore — a power-efficient CPU management scheme that can optimize the use of Dynamic and Frequency Voltage Scaling (DVFS) and the Dynamic Core Scaling (DCS) techniques with a sensitive control on CPU bandwidth. The measurements on the real systems prove that MobiCore can achieve substantial CPU power reduction compared to state-of-the-art architectures.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124205992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/SOCC.2017.8225994
Harsh Rawat, K. Bharath, Alexander Fell
With the advancement in technology nodes, the number of components operating in different clock domains in a System on Chip (SoC) increases. Asynchronous multi-port memory with dedicated write and read ports is used to allow data to cross clock domain boundaries. The dual-port memory architecture introduced in this paper, is based on the Single-Port SRAM (SP-SRAM) that can be generated in larger capacities with better performance statistics compared to the Dual-Port SRAM (DP-SRAM). The proposed design has been evaluated by comparing existing dual-port 1R-1W and 2RW designs in 28nm Ultra Thin Body and Box Fully Depleted Silicon on Insulator (UTBB-FDSOI) technology. A memory with a capacity of 2048 words with 64 bits, shows 15%, 35%, 28% and 4.5% improvement in read power, write power, read-write power consumption and performance respectively over conventional 1R-1W DP-SRAM with equal area. The synthesis with area optimizations applied instead, shows an area advantage of 50% over conventional 1R-1W DP-SRAM, but with a degradation in performance.
{"title":"Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology","authors":"Harsh Rawat, K. Bharath, Alexander Fell","doi":"10.1109/SOCC.2017.8225994","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8225994","url":null,"abstract":"With the advancement in technology nodes, the number of components operating in different clock domains in a System on Chip (SoC) increases. Asynchronous multi-port memory with dedicated write and read ports is used to allow data to cross clock domain boundaries. The dual-port memory architecture introduced in this paper, is based on the Single-Port SRAM (SP-SRAM) that can be generated in larger capacities with better performance statistics compared to the Dual-Port SRAM (DP-SRAM). The proposed design has been evaluated by comparing existing dual-port 1R-1W and 2RW designs in 28nm Ultra Thin Body and Box Fully Depleted Silicon on Insulator (UTBB-FDSOI) technology. A memory with a capacity of 2048 words with 64 bits, shows 15%, 35%, 28% and 4.5% improvement in read power, write power, read-write power consumption and performance respectively over conventional 1R-1W DP-SRAM with equal area. The synthesis with area optimizations applied instead, shows an area advantage of 50% over conventional 1R-1W DP-SRAM, but with a degradation in performance.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130013917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SOCC.2017.8226007
Hong-Yan Su, S. Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, H. Onodera
Pin accessibility influences the routability of a design at the stage of block/chip assembling. The estimation model for pin accessibility in previous researches counts the total number of intersections between each pin and M2 routing tracks. It does not consider the variation of pin accessibility as the spacing between a pin and its neighboring pins and metal wires changes. Besides, it cannot properly deal with the off-grid pin access neither. In this paper, we propose a general model for pin accessibility estimation. In the model, all directions to connect to the boundary of a pin are under estimation. Off-grid pin access is also available. Experimental results show that the reduction rate of minimum area to complete the routing of a circuit can be 7.0% on average. Due to the diminishment of required area for routing, the total number of vias for higher metal layer also decrease under the same area constraint.
{"title":"Pin accessibility evaluating model for improving routability of VLSI designs","authors":"Hong-Yan Su, S. Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, H. Onodera","doi":"10.1109/SOCC.2017.8226007","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226007","url":null,"abstract":"Pin accessibility influences the routability of a design at the stage of block/chip assembling. The estimation model for pin accessibility in previous researches counts the total number of intersections between each pin and M2 routing tracks. It does not consider the variation of pin accessibility as the spacing between a pin and its neighboring pins and metal wires changes. Besides, it cannot properly deal with the off-grid pin access neither. In this paper, we propose a general model for pin accessibility estimation. In the model, all directions to connect to the boundary of a pin are under estimation. Off-grid pin access is also available. Experimental results show that the reduction rate of minimum area to complete the routing of a circuit can be 7.0% on average. Due to the diminishment of required area for routing, the total number of vias for higher metal layer also decrease under the same area constraint.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121075225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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