Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226012
Takashi Imagawa, Koki Honda, H. Ochi
This paper proposes a placement algorithm using analytical placement (AP) and low-temperature simulated annealing (SA) for mixed-grained reconfigurable architecture (MGRA) with dedicated carry chains. The target MGRAs are assumed to have fine-grained blocks with dedicated carry chains to implement high-speed adders/subtracters and coarse-grained blocks to implement complicated arithmetic operations. Although this mixed-grained architecture is expected to enhance the performance of the implemented application circuit, placement becomes problematic because of the inherent placement constraints. For example, some logic blocks have many connections to others and constraints such as these cause simple pair-swap-based SA to converge to a local optimum. The proposed algorithm uses AP to determine an initial placement for SA. The AP explores an appropriate placement of coarse-grained blocks and adders/subtracters consisting of fine-grained blocks and dedicated carry chains. On the other hand, SA is mainly used to determine optimal placement of the remaining fine-grained blocks. The evaluations show that the proposed algorithm reduces the placement cost, critical path delay, and runtime by 18.4%, 6.0%, and 67.6% on average, respectively, over the versatile place and route (VPR) approach. The benchmark includes circuits consisting of only fine-grained logic. Hence, the proposed algorithm is expected to improve the placement quality for a wide range of application circuits.
{"title":"Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chain","authors":"Takashi Imagawa, Koki Honda, H. Ochi","doi":"10.1109/SOCC.2017.8226012","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226012","url":null,"abstract":"This paper proposes a placement algorithm using analytical placement (AP) and low-temperature simulated annealing (SA) for mixed-grained reconfigurable architecture (MGRA) with dedicated carry chains. The target MGRAs are assumed to have fine-grained blocks with dedicated carry chains to implement high-speed adders/subtracters and coarse-grained blocks to implement complicated arithmetic operations. Although this mixed-grained architecture is expected to enhance the performance of the implemented application circuit, placement becomes problematic because of the inherent placement constraints. For example, some logic blocks have many connections to others and constraints such as these cause simple pair-swap-based SA to converge to a local optimum. The proposed algorithm uses AP to determine an initial placement for SA. The AP explores an appropriate placement of coarse-grained blocks and adders/subtracters consisting of fine-grained blocks and dedicated carry chains. On the other hand, SA is mainly used to determine optimal placement of the remaining fine-grained blocks. The evaluations show that the proposed algorithm reduces the placement cost, critical path delay, and runtime by 18.4%, 6.0%, and 67.6% on average, respectively, over the versatile place and route (VPR) approach. The benchmark includes circuits consisting of only fine-grained logic. Hence, the proposed algorithm is expected to improve the placement quality for a wide range of application circuits.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130058524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226009
J. B. Filho, J. Wang
In the design flow of Multi-Processed Systems-on-Chip (MPSoCs), the evaluation of communication structures play a very important role, since it may reveal relevant information on performance, energy consumption and cost. Simulation under a number of stimulus given by a traffic generator is a relevant solution for MPSoCs performance analysis. Traditional traffic generators based on Poisson and classic Markovian models are not able to reproduce certain characteristics of original application traces, such as bursts and self-similarity. After the detection of Long Range Dependence (LRD) in on-chip traffic, monofractal models started being used for traffic generation. These models, however, were mainly used under RTL/CA simulations and present statistical limitations, opening opportunities for tests with multifractal models and higher abstraction level descriptions. In this work, it is shown that the Multifractal Wavelet Model (MWM) presents a better accuracy in the modeling of on-chip traffic when compared with auto-regressive (monofractal) models and that the usage of traffic generators modeled under TLM can achieve simulation speed-ups in the order of 12x.
{"title":"Multifractal on-chip traffic generation under TLM","authors":"J. B. Filho, J. Wang","doi":"10.1109/SOCC.2017.8226009","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226009","url":null,"abstract":"In the design flow of Multi-Processed Systems-on-Chip (MPSoCs), the evaluation of communication structures play a very important role, since it may reveal relevant information on performance, energy consumption and cost. Simulation under a number of stimulus given by a traffic generator is a relevant solution for MPSoCs performance analysis. Traditional traffic generators based on Poisson and classic Markovian models are not able to reproduce certain characteristics of original application traces, such as bursts and self-similarity. After the detection of Long Range Dependence (LRD) in on-chip traffic, monofractal models started being used for traffic generation. These models, however, were mainly used under RTL/CA simulations and present statistical limitations, opening opportunities for tests with multifractal models and higher abstraction level descriptions. In this work, it is shown that the Multifractal Wavelet Model (MWM) presents a better accuracy in the modeling of on-chip traffic when compared with auto-regressive (monofractal) models and that the usage of traffic generators modeled under TLM can achieve simulation speed-ups in the order of 12x.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128952383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226062
N. Wehn
It is well known that DRAM memory performance cannot keep pace with the performance of today's multicore compute systems. In addition to the memory bandwidth problem, there is another major challenge, namely, the power/energy challenge. DRAMs are largely contributing to the overall power consumption. Thus, there is a need for power and bandwidth optimization of the DRAM memory subsystems. Moreover, new memory architectures are emerging like HBM, HMC and Wide I/O DRAMs to cope with the increasing bandwidth requirements. In this talk, we will give an overview on these new architectures and present various optimization techniques to optimize bandwidth and energy consumption in DRAM based memory systems.
{"title":"The memory challenge in computing systems: A survey","authors":"N. Wehn","doi":"10.1109/SOCC.2017.8226062","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226062","url":null,"abstract":"It is well known that DRAM memory performance cannot keep pace with the performance of today's multicore compute systems. In addition to the memory bandwidth problem, there is another major challenge, namely, the power/energy challenge. DRAMs are largely contributing to the overall power consumption. Thus, there is a need for power and bandwidth optimization of the DRAM memory subsystems. Moreover, new memory architectures are emerging like HBM, HMC and Wide I/O DRAMs to cope with the increasing bandwidth requirements. In this talk, we will give an overview on these new architectures and present various optimization techniques to optimize bandwidth and energy consumption in DRAM based memory systems.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121180286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226072
Jeremy Schlachter, M. Fagan, K. Palem, C. Enz
Energy-efficiency is a critical concern for many computing systems. With Moore's law showing its limits, new hardware design and programming techniques emerge to pursue energy scaling. Among these, approximate computing is certainly the most popular in current works. It has been shown that reducing precision using software techniques can show significant energy savings on commercially available processors. In this paper, an energy model based on Energy Per Instruction (EPI) has been built in order to understand which mechanisms enable those savings. EPIs of various instructions have been measured and data movement has been identified as being the major consumer. The energy model has been evaluated on a computationally intensive Newton method for solving nonlinear equations using double-precision and single-precision floating-point data types. For all the cases, the model predicts the consumption with less than 10 % error. The energy breakdown reveals that arithmetic operations consume less than 6 % of the total energy and that savings are mainly achieved by reducing the amount of data transferred between registers, cache and main memory. With these conclusions, implementing approximate arithmetic circuits in this type of architecture would have a very limited impact on the consumption. It is however shown that specialized hardware implemented on an FPGA interconnected with a processing system can lead to an additional 20 % energy savings on the Newton method using the same single-precision data type.
{"title":"A study on the energy-precision tradeoffs on commercially available processors and SoCs with an EPI based energy model","authors":"Jeremy Schlachter, M. Fagan, K. Palem, C. Enz","doi":"10.1109/SOCC.2017.8226072","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226072","url":null,"abstract":"Energy-efficiency is a critical concern for many computing systems. With Moore's law showing its limits, new hardware design and programming techniques emerge to pursue energy scaling. Among these, approximate computing is certainly the most popular in current works. It has been shown that reducing precision using software techniques can show significant energy savings on commercially available processors. In this paper, an energy model based on Energy Per Instruction (EPI) has been built in order to understand which mechanisms enable those savings. EPIs of various instructions have been measured and data movement has been identified as being the major consumer. The energy model has been evaluated on a computationally intensive Newton method for solving nonlinear equations using double-precision and single-precision floating-point data types. For all the cases, the model predicts the consumption with less than 10 % error. The energy breakdown reveals that arithmetic operations consume less than 6 % of the total energy and that savings are mainly achieved by reducing the amount of data transferred between registers, cache and main memory. With these conclusions, implementing approximate arithmetic circuits in this type of architecture would have a very limited impact on the consumption. It is however shown that specialized hardware implemented on an FPGA interconnected with a processing system can lead to an additional 20 % energy savings on the Newton method using the same single-precision data type.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122632065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226064
Sebastian Tobuschat, R. Ernst
Future mixed-criticality systems must handle a growing variety of traffic requirements, ranging from safety-critical real-time traffic to bursty latency-sensitive best-effort traffic. Additionally, safety standards (e.g. ISO 26262) require sufficient independence among different criticality levels for mixed-criticality systems. Networks-on-Chip (NoCs), as a scalable and modular interconnect, are used as a promising solution for such systems. Hence, a NoC must provide performance isolation for safety-critical traffic and low latency for best-effort traffic at the same time. This paper presents a run-time configurable NoC design enabling throughput guarantees for selected traffic streams with reduced adverse impact on the performance of best-effort traffic. In contrast to existing approaches, we prioritize best-effort over guaranteed throughput traffic and only switch priorities when required, providing sufficient performance isolation among different criticality levels. We show that the overhead implementing our approach is affordable. And through an experimental evaluation, we show that the approach reduces the adverse effects through strict prioritization on best-effort applications.
{"title":"Providing throughput guarantees in mixed-criticality networks-on-chip","authors":"Sebastian Tobuschat, R. Ernst","doi":"10.1109/SOCC.2017.8226064","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226064","url":null,"abstract":"Future mixed-criticality systems must handle a growing variety of traffic requirements, ranging from safety-critical real-time traffic to bursty latency-sensitive best-effort traffic. Additionally, safety standards (e.g. ISO 26262) require sufficient independence among different criticality levels for mixed-criticality systems. Networks-on-Chip (NoCs), as a scalable and modular interconnect, are used as a promising solution for such systems. Hence, a NoC must provide performance isolation for safety-critical traffic and low latency for best-effort traffic at the same time. This paper presents a run-time configurable NoC design enabling throughput guarantees for selected traffic streams with reduced adverse impact on the performance of best-effort traffic. In contrast to existing approaches, we prioritize best-effort over guaranteed throughput traffic and only switch priorities when required, providing sufficient performance isolation among different criticality levels. We show that the overhead implementing our approach is affordable. And through an experimental evaluation, we show that the approach reduces the adverse effects through strict prioritization on best-effort applications.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130669422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226034
Thawra Kadeed, Eberle A. Rambo, R. Ernst
As fault-tolerant Networks-on-Chip (NoCs) become prevalent in reliable systems, their overhead must be accurately evaluated. In this paper, we evaluate the overhead of a soft error resilient real-time NoC router for ASICs in terms of area and power. We employ a power analysis framework and load profiles that provide accurate power figures. Furthermore, we analyze the power behavior in normal operation as well as under errors. Experiments show that the employed error detection and retransmission schemes in our NoC contribute low power overhead when compared to previously proposed scheme.
{"title":"Power and area evaluation of a fault-tolerant network-on-chip","authors":"Thawra Kadeed, Eberle A. Rambo, R. Ernst","doi":"10.1109/SOCC.2017.8226034","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226034","url":null,"abstract":"As fault-tolerant Networks-on-Chip (NoCs) become prevalent in reliable systems, their overhead must be accurately evaluated. In this paper, we evaluate the overhead of a soft error resilient real-time NoC router for ASICs in terms of area and power. We employ a power analysis framework and load profiles that provide accurate power figures. Furthermore, we analyze the power behavior in normal operation as well as under errors. Experiments show that the employed error detection and retransmission schemes in our NoC contribute low power overhead when compared to previously proposed scheme.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114143240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226047
Haoyu Yang, Yajun Lin, Bei Yu, Evangeline F. Y. Young
As VLSI technology nodes continue, the gap between lithography system manufacturing ability and transistor feature size induces serious problems, thus lithography hotspot detection is of importance in physical verification flow. Existing hotspot detection approaches can be categorized into pattern matching-based and machine learning-based. With extreme scaling of transistor feature size and the growing complexity of layout patterns, the traditional methods may suffer from performance degradation. For example, pattern matching-based methods have lower hotspot detection rates for unseen patterns, while machine learning-based methods may lose information in manual feature extraction for ultra-large-scale integrated circuit masks. To overcome the drawbacks derived from existing methods, in this paper, we survey very recent deep learning techniques and argue that the pooling layers in ordinary deep learning architecture are not necessary. We further propose a novel pooling-free neural network architecture, whose effectiveness is verified by industrial benchmark suites.
{"title":"Lithography hotspot detection: From shallow to deep learning","authors":"Haoyu Yang, Yajun Lin, Bei Yu, Evangeline F. Y. Young","doi":"10.1109/SOCC.2017.8226047","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226047","url":null,"abstract":"As VLSI technology nodes continue, the gap between lithography system manufacturing ability and transistor feature size induces serious problems, thus lithography hotspot detection is of importance in physical verification flow. Existing hotspot detection approaches can be categorized into pattern matching-based and machine learning-based. With extreme scaling of transistor feature size and the growing complexity of layout patterns, the traditional methods may suffer from performance degradation. For example, pattern matching-based methods have lower hotspot detection rates for unseen patterns, while machine learning-based methods may lose information in manual feature extraction for ultra-large-scale integrated circuit masks. To overcome the drawbacks derived from existing methods, in this paper, we survey very recent deep learning techniques and argue that the pooling layers in ordinary deep learning architecture are not necessary. We further propose a novel pooling-free neural network architecture, whose effectiveness is verified by industrial benchmark suites.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114473456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226030
Y. Lan, V. Muthukumar
Low-level design parameters such as router micro-architecture (RMA), flow controls (resource allocation), routing techniques and traffic patterns have a major significance on cost and performance of Network on Chip (NOC) design. This work proposes an efficient virtual channel (VC) buffer management structure and a dynamic VC allocation mechanism for the router to minimize latency, and area (buffer allocation) overhead. The proposed VC architecture and allocation algorithm can be adapted to various switching techniques used in NoC implementations with buffers and is independent of the topology. The architecture was developed and simulated for various traffic patterns. The performance was evaluated for different load scenarios and comparison to existing VC allocation algorithms are discussed in this paper. Our implementation achieves better performance (throughput and area overhead) compared to baseline and Adaptive Backpressure (ABP) VC allocation algorithm.
{"title":"Efficient virtual channel allocator for NoC router micro-architecture","authors":"Y. Lan, V. Muthukumar","doi":"10.1109/SOCC.2017.8226030","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226030","url":null,"abstract":"Low-level design parameters such as router micro-architecture (RMA), flow controls (resource allocation), routing techniques and traffic patterns have a major significance on cost and performance of Network on Chip (NOC) design. This work proposes an efficient virtual channel (VC) buffer management structure and a dynamic VC allocation mechanism for the router to minimize latency, and area (buffer allocation) overhead. The proposed VC architecture and allocation algorithm can be adapted to various switching techniques used in NoC implementations with buffers and is independent of the topology. The architecture was developed and simulated for various traffic patterns. The performance was evaluated for different load scenarios and comparison to existing VC allocation algorithms are discussed in this paper. Our implementation achieves better performance (throughput and area overhead) compared to baseline and Adaptive Backpressure (ABP) VC allocation algorithm.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124635074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8225984
Subhadeep Ghosh, Scott Martin, Shane Stelmach
The semiconductor industry is strategically focusing on automotive and industrial markets. Significant investment is targeted to address these markets. The automotive industry in particular is already in focus for last several years. At the same time, with its seemingly endless possibilities in the “internet of things” (IOT) world, industrial markets are gaining attention as building automation, factory automation, and grid infrastructure rapidly advance.
{"title":"Reliability for IoT and automotive markets","authors":"Subhadeep Ghosh, Scott Martin, Shane Stelmach","doi":"10.1109/SOCC.2017.8225984","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8225984","url":null,"abstract":"The semiconductor industry is strategically focusing on automotive and industrial markets. Significant investment is targeted to address these markets. The automotive industry in particular is already in focus for last several years. At the same time, with its seemingly endless possibilities in the “internet of things” (IOT) world, industrial markets are gaining attention as building automation, factory automation, and grid infrastructure rapidly advance.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117189090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8225995
Renyuan Zhang, M. Kaneko
A random access analog memory is designed without static power in this work. The analog memory appears the benefit on the great reduction of interconnections but suffers from the static power consumption and inaccuracy. As a hybrid, the hexadecimal signal processing is targeted in this paper. For storing hexadecimal values even implementing hexadecimal sequential logic, a master-slave structure is proposed with eighteen transistors, which is 28% of four pieces of binary master-slave flipflop. The hexadecimal voltage values are stored on the floating gate; and the read-out operations are executed by a comparator to protect the stored voltage. This comparator is powered only during the read-out operation. In this manner, the static power is eliminated. By using the proposed timing control mode, the master and slave stages are organized for hexadecimal sequential logic. As a demonstration, a sixteen-counter is designed on the basis of proposed analog memory without combinational logic circuits, in which the number of devices is reduced in contrast of binary approaches. From the circuit simulation results, the designed circuits maintain the hexadecimal values and execute hexadecimal functions correctly.
{"title":"A random access analog memory with master-slave structure for implementing hexadecimal logic","authors":"Renyuan Zhang, M. Kaneko","doi":"10.1109/SOCC.2017.8225995","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8225995","url":null,"abstract":"A random access analog memory is designed without static power in this work. The analog memory appears the benefit on the great reduction of interconnections but suffers from the static power consumption and inaccuracy. As a hybrid, the hexadecimal signal processing is targeted in this paper. For storing hexadecimal values even implementing hexadecimal sequential logic, a master-slave structure is proposed with eighteen transistors, which is 28% of four pieces of binary master-slave flipflop. The hexadecimal voltage values are stored on the floating gate; and the read-out operations are executed by a comparator to protect the stored voltage. This comparator is powered only during the read-out operation. In this manner, the static power is eliminated. By using the proposed timing control mode, the master and slave stages are organized for hexadecimal sequential logic. As a demonstration, a sixteen-counter is designed on the basis of proposed analog memory without combinational logic circuits, in which the number of devices is reduced in contrast of binary approaches. From the circuit simulation results, the designed circuits maintain the hexadecimal values and execute hexadecimal functions correctly.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134346213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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