Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226037
Todd Hiers, Chunhua Hu, B. Karguth, Chuck Fuoco
Interface-based design methodologies and tools using machine-readable metadata have been in use for many years; however, a lot of manual effort is still needed to gather module information, especially when the SoC and modules are being co-designed. It is a time-consuming and error prone challenge made more difficult by increasing SoC complexity. Various efforts to address these issues with document-based “executable specifications” met with only modest success. By committing fully to an architecture-specific web-based executable specification tool, the metadata available in the ecosystem could be leveraged to greatly improve the specification-to-design process. This paper presents a case study on a unified, integrated environment for subsystem creation, SoC integration, and SoC specification teams by building and using an architecture-aware tool to comprehend the SoC constructs. A modern web-based framework instead of a standalone tool gave built-in collaboration capabilities and an easy way to visually represent and manipulate data. Various architectural rules about these connections can be enforced. Connection fabrics (e.g. NoC) and other project-specific infrastructure can be configured and synthesized on demand and brought in to the design easily due to the common environment. Netlists and other connectivity data can be fed into automated RTL generation processes directly, or used as reference for design teams tasked with implementation. Reports and automated software generation satisfy the needs of the design verification and software teams. Overall team productivity is greatly enhanced — infrastructure is produced much more quickly with fewer engineers needed. The shorter revision cycle also speeds and simplifies functional and performance testing feedback loops.
{"title":"Virtual white board: Leveraging investments in interface based design and executable specification","authors":"Todd Hiers, Chunhua Hu, B. Karguth, Chuck Fuoco","doi":"10.1109/SOCC.2017.8226037","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226037","url":null,"abstract":"Interface-based design methodologies and tools using machine-readable metadata have been in use for many years; however, a lot of manual effort is still needed to gather module information, especially when the SoC and modules are being co-designed. It is a time-consuming and error prone challenge made more difficult by increasing SoC complexity. Various efforts to address these issues with document-based “executable specifications” met with only modest success. By committing fully to an architecture-specific web-based executable specification tool, the metadata available in the ecosystem could be leveraged to greatly improve the specification-to-design process. This paper presents a case study on a unified, integrated environment for subsystem creation, SoC integration, and SoC specification teams by building and using an architecture-aware tool to comprehend the SoC constructs. A modern web-based framework instead of a standalone tool gave built-in collaboration capabilities and an easy way to visually represent and manipulate data. Various architectural rules about these connections can be enforced. Connection fabrics (e.g. NoC) and other project-specific infrastructure can be configured and synthesized on demand and brought in to the design easily due to the common environment. Netlists and other connectivity data can be fed into automated RTL generation processes directly, or used as reference for design teams tasked with implementation. Reports and automated software generation satisfy the needs of the design verification and software teams. Overall team productivity is greatly enhanced — infrastructure is produced much more quickly with fewer engineers needed. The shorter revision cycle also speeds and simplifies functional and performance testing feedback loops.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132728997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226014
Takumi Fujimori, Minoru Watanabe
Recently, field programmable gate arrays (FPGAs) are anticipated for use in high-radiation environments such as the Fukushima Daiichi nuclear power plant. According to recent news, regions with 650 Sv/h radiation have been found at the Fukushima Daiichi nuclear power plant. Under such extremely high radiation environments, high-speed scrubbing operations must be used to maintain correct circuit information on the configuration memory of programmable gate arrays. Up to now, optical high-speed scrubbing based on an optically reconfigurable gate array has been proposed. This paper presents a demonstration of the radiation tolerance of the optical high-speed scrubbing based on an optically reconfigurable gate array VLSI by using lasers that emulate strong radiation environments. It has been confirmed that 70-ns period high-speed scrubbing operations on the optically reconfigurable gate array are never disturbed by the emulated radiation.
{"title":"Radiation tolerance demonstration of high-speed scrubbing on an optically reconfigurable gate array","authors":"Takumi Fujimori, Minoru Watanabe","doi":"10.1109/SOCC.2017.8226014","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226014","url":null,"abstract":"Recently, field programmable gate arrays (FPGAs) are anticipated for use in high-radiation environments such as the Fukushima Daiichi nuclear power plant. According to recent news, regions with 650 Sv/h radiation have been found at the Fukushima Daiichi nuclear power plant. Under such extremely high radiation environments, high-speed scrubbing operations must be used to maintain correct circuit information on the configuration memory of programmable gate arrays. Up to now, optical high-speed scrubbing based on an optically reconfigurable gate array has been proposed. This paper presents a demonstration of the radiation tolerance of the optical high-speed scrubbing based on an optically reconfigurable gate array VLSI by using lasers that emulate strong radiation environments. It has been confirmed that 70-ns period high-speed scrubbing operations on the optically reconfigurable gate array are never disturbed by the emulated radiation.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132920322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8225987
A. Marshall, N. Sharma
As it has become physically more difficult and more expensive to extend the performance characteristics of planar CMOS technology, there have been many efforts to create new technologies. Some of these are CMOS extensions, such as Finfet devices. Others are the so-called beyond CMOS devices, which include charge-based logic such as Tunnel FET based systems, others are non-charge based, which include nano-magnetic structures, spintronics devices, advanced charge-based devices and a variety of quantum structures.
{"title":"The importance of benchmarking for charge-based and beyond CMOS devices","authors":"A. Marshall, N. Sharma","doi":"10.1109/SOCC.2017.8225987","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8225987","url":null,"abstract":"As it has become physically more difficult and more expensive to extend the performance characteristics of planar CMOS technology, there have been many efforts to create new technologies. Some of these are CMOS extensions, such as Finfet devices. Others are the so-called beyond CMOS devices, which include charge-based logic such as Tunnel FET based systems, others are non-charge based, which include nano-magnetic structures, spintronics devices, advanced charge-based devices and a variety of quantum structures.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131816842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226052
Jan Plíva, M. Khafaji, László Szilágyi, R. Henker, F. Ellinger
This paper presents the design and the opto-electrical measurements of a power-efficient receiver analog front-end (AFE) for optical communication with standby mode and rapid recovery time below 10 ns. The circuit was designed and fabricated in advanced 14 nm FinFET CMOS with a small area of 0.0159mm2. The AFE consumes 22.6mW power, thus achieving a power efficiency of 0.82 pJ/bit. Furthermore, a power saving standby mode is supported which is a feature not commonly available in state-of-the-art designs. During the powersaving mode, the limiting amplifier (LA) is shut down resulting in power consumption reduction of 50 % down to 11.4 mW. A recovery time from standby mode amounting to 8.2 ns was measured, thus making the front-end suitable for future standard burst mode operation. For measurements, a multi-chip assembly with a photo diode in 850 nm band was fabricated and the performance was measured using an optical probe. A bit error rate (BER) of 10−12 was achieved for a data rate of 28 Gb/s with an optical sensitivity of −3.5 dBm optical modulation amplitude (OMA).
{"title":"Opto-electrical analog front-end with rapid power-on and 0.82 pJ/bit for 28 Gb/s in 14 nm FinFET CMOS","authors":"Jan Plíva, M. Khafaji, László Szilágyi, R. Henker, F. Ellinger","doi":"10.1109/SOCC.2017.8226052","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226052","url":null,"abstract":"This paper presents the design and the opto-electrical measurements of a power-efficient receiver analog front-end (AFE) for optical communication with standby mode and rapid recovery time below 10 ns. The circuit was designed and fabricated in advanced 14 nm FinFET CMOS with a small area of 0.0159mm2. The AFE consumes 22.6mW power, thus achieving a power efficiency of 0.82 pJ/bit. Furthermore, a power saving standby mode is supported which is a feature not commonly available in state-of-the-art designs. During the powersaving mode, the limiting amplifier (LA) is shut down resulting in power consumption reduction of 50 % down to 11.4 mW. A recovery time from standby mode amounting to 8.2 ns was measured, thus making the front-end suitable for future standard burst mode operation. For measurements, a multi-chip assembly with a photo diode in 850 nm band was fabricated and the performance was measured using an optical probe. A bit error rate (BER) of 10−12 was achieved for a data rate of 28 Gb/s with an optical sensitivity of −3.5 dBm optical modulation amplitude (OMA).","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133204027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226054
A. Bondok, A. M. El-Mohandes, A. Shalaby, M. Sayed
Dealing with critical health issues requires the existence of an intelligent health care system capable of monitoring the patients wherever they are, which increases the demand for a wireless health care system. One possible realization of such a system is the wireless body area network standard defined by IEEE 802.15.6. Based on IEEE 802.15.6, this paper proposes a low complexity implementation of the ultra-wideband physical layer transceiver. A full practical transceiver is introduced with Pulse Shaping, Pulse Deshaping, Time Hopping, Packet Detection and Frame Synchronization included. Chirp pulse is used to shape the data bits in order to minimize the out-of-band radiations. New hardware efficient strategy is used for packet detection. The functionality of the transceiver is tested through computer simulations. All of the design modules were written in Matlab then prototyped using verilog hardware description language. The transceiver is then synthesized targeting 65 nm CMOS technology. The transceiver consumes 443.83 μW in 65 nm technology and conforms to all of standard requirements.
{"title":"A low complexity UWB PHY baseband transceiver for IEEE 802.15.6 WBAN","authors":"A. Bondok, A. M. El-Mohandes, A. Shalaby, M. Sayed","doi":"10.1109/SOCC.2017.8226054","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226054","url":null,"abstract":"Dealing with critical health issues requires the existence of an intelligent health care system capable of monitoring the patients wherever they are, which increases the demand for a wireless health care system. One possible realization of such a system is the wireless body area network standard defined by IEEE 802.15.6. Based on IEEE 802.15.6, this paper proposes a low complexity implementation of the ultra-wideband physical layer transceiver. A full practical transceiver is introduced with Pulse Shaping, Pulse Deshaping, Time Hopping, Packet Detection and Frame Synchronization included. Chirp pulse is used to shape the data bits in order to minimize the out-of-band radiations. New hardware efficient strategy is used for packet detection. The functionality of the transceiver is tested through computer simulations. All of the design modules were written in Matlab then prototyped using verilog hardware description language. The transceiver is then synthesized targeting 65 nm CMOS technology. The transceiver consumes 443.83 μW in 65 nm technology and conforms to all of standard requirements.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116108115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226058
Hantao Huang, Leibin Ni, Hao Yu
An energy efficient machine learning requires an effective construction of neural network during training. This paper introduces a tensorized formulation of neural network during training such that weight matrix can be significantly compressed. The tensorized neural network can be further naturally mapped to a 3D CMOS-RRAM based accelerator with significant bandwidth boosting from vertical I/O connections. As such, high throughput and low power can be achieved simultaneously. Simulation results using the benchmark MNIST show that the proposed accelerator has 1.294x speed-up, 2.393x energy-efficiency and 7.59 x area saving compared to 3D CMOS-ASIC implementation. Moreover, our proposed accelerator can achieve 370.64 GOPS throughput and 1055.95 GOPS/W energy efficiency, which is equivalent to 7.661 TOPS/W for uncompressed neural network. In addition, 142x model compression can be achieved by tensorization with acceptable accuracy loss.
{"title":"LTNN: An energy-efficient machine learning accelerator on 3D CMOS-RRAM for layer-wise tensorized neural network","authors":"Hantao Huang, Leibin Ni, Hao Yu","doi":"10.1109/SOCC.2017.8226058","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226058","url":null,"abstract":"An energy efficient machine learning requires an effective construction of neural network during training. This paper introduces a tensorized formulation of neural network during training such that weight matrix can be significantly compressed. The tensorized neural network can be further naturally mapped to a 3D CMOS-RRAM based accelerator with significant bandwidth boosting from vertical I/O connections. As such, high throughput and low power can be achieved simultaneously. Simulation results using the benchmark MNIST show that the proposed accelerator has 1.294x speed-up, 2.393x energy-efficiency and 7.59 x area saving compared to 3D CMOS-ASIC implementation. Moreover, our proposed accelerator can achieve 370.64 GOPS throughput and 1055.95 GOPS/W energy efficiency, which is equivalent to 7.661 TOPS/W for uncompressed neural network. In addition, 142x model compression can be achieved by tensorization with acceptable accuracy loss.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130465168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8225985
A. Frisch
In a press release on March 6th 2017, IBM has commited itself to develop a commercial quantum system called IBM Q. For the first time this enables IBM to directly target potential customers in this field e.g. HPC groups or industrial R&D departments. Early access to a Quantum Computer on the cloud is enabled via the IBM Quantum Experience. The IBM Quantum Computer has been presented at this years CeBIT in Hannover. The great advantage of a universal Quantum Computer is based on quantum mechanical effects, which are not known in classical every-day life, e.g. superposition, entanglement, and teleportation. Using these effects in smart ways certain algorithms can be boosted beyond classical limits. But controlling and measuring qubits in large scales turns out to be a great challenge. In my talk I will point out the fundamental differences between a classical computer and a quantum computer. I will show in detail how the IBM Quantum Computer works and what potential pitfalls are there for scaling quantum systems. In a live demo we will program simple quantum algorithms and execute them on the IBM quantum computer in real-time.
{"title":"IBM Q — Introduction into quantum computing with live demo","authors":"A. Frisch","doi":"10.1109/SOCC.2017.8225985","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8225985","url":null,"abstract":"In a press release on March 6th 2017, IBM has commited itself to develop a commercial quantum system called IBM Q. For the first time this enables IBM to directly target potential customers in this field e.g. HPC groups or industrial R&D departments. Early access to a Quantum Computer on the cloud is enabled via the IBM Quantum Experience. The IBM Quantum Computer has been presented at this years CeBIT in Hannover. The great advantage of a universal Quantum Computer is based on quantum mechanical effects, which are not known in classical every-day life, e.g. superposition, entanglement, and teleportation. Using these effects in smart ways certain algorithms can be boosted beyond classical limits. But controlling and measuring qubits in large scales turns out to be a great challenge. In my talk I will point out the fundamental differences between a classical computer and a quantum computer. I will show in detail how the IBM Quantum Computer works and what potential pitfalls are there for scaling quantum systems. In a live demo we will program simple quantum algorithms and execute them on the IBM quantum computer in real-time.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115634240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8226025
Jeong H. Choi, K. Yoon
This paper presents a CMOS third order ΔΣ modulator with inverter-based integrators for low power audio signal processing application. In order to minimize the power consumption of the proposed modulator, the inverters embedded into integrators and an analog adder operating in the subthreshold region were implemented on an 180nm CMOS technology with digital and analog power supply of 1.8V and 0.8V, respectively. The measurement results demonstrated ENOB of 13.1bit, DR of 86.1dB, total power dissipation of 92uW, and FOM(walden) of 260 fJ/step at sampling frequency of 2.56 MHz and input signal frequency of 2.5kHz.
{"title":"A CMOS third order ΔΣ modulator with inverter-based integrators","authors":"Jeong H. Choi, K. Yoon","doi":"10.1109/SOCC.2017.8226025","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8226025","url":null,"abstract":"This paper presents a CMOS third order ΔΣ modulator with inverter-based integrators for low power audio signal processing application. In order to minimize the power consumption of the proposed modulator, the inverters embedded into integrators and an analog adder operating in the subthreshold region were implemented on an 180nm CMOS technology with digital and analog power supply of 1.8V and 0.8V, respectively. The measurement results demonstrated ENOB of 13.1bit, DR of 86.1dB, total power dissipation of 92uW, and FOM(walden) of 260 fJ/step at sampling frequency of 2.56 MHz and input signal frequency of 2.5kHz.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129461272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8225983
Herbert Preuthen, Jurgen Dirks
22FDX™ is new technology from GLOBALFOUNDRIES based on Fully-Depleted-Silicon-on-Insulator (FDSOI). Its transistor architecture consists of a thin layer of semiconductor material on top of a body-oxide. On the top side, a planar leading-edge MOS-transistor is formed. From the bottom, the wells have electrostatic influence through the body-oxide, which is large enough to shift the transistor threshold voltages between high-performance- and low-leakage operation. The tutorial will give an introduction to the technology and show the digital design reference flow from GLOBALFOUNDRIES, which has been developed for 22FDX. Particular emphasis will be given on how to use FDSOI for low-power designs using the back-gate bias. Also, design examples will be exposed and results will be discussed.
{"title":"FDSOI design experience and recommendations","authors":"Herbert Preuthen, Jurgen Dirks","doi":"10.1109/SOCC.2017.8225983","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8225983","url":null,"abstract":"22FDX™ is new technology from GLOBALFOUNDRIES based on Fully-Depleted-Silicon-on-Insulator (FDSOI). Its transistor architecture consists of a thin layer of semiconductor material on top of a body-oxide. On the top side, a planar leading-edge MOS-transistor is formed. From the bottom, the wells have electrostatic influence through the body-oxide, which is large enough to shift the transistor threshold voltages between high-performance- and low-leakage operation. The tutorial will give an introduction to the technology and show the digital design reference flow from GLOBALFOUNDRIES, which has been developed for 22FDX. Particular emphasis will be given on how to use FDSOI for low-power designs using the back-gate bias. Also, design examples will be exposed and results will be discussed.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117100242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/SOCC.2017.8225982
M. Pronath
Designing circuits for enhanced IoT (“Internet of Things”) applications is one of the current growth driver for the electronics industry. Optimizing such circuits for lowest power consumption while maximize functionality and performance is key for successful implementation of such circuits in the IoT systems. IoT devices are diverse in nature but are typically constrained by limited power availability, limited area budget and the need for modularity of design. The burden of ultra-low-power budget unfortunately doesn't necessarily mean that other performance requirements are relaxed. The tutorial is therefore geared towards designers of IoT devices including sensors, MEMS, mobile devices, medical sensors, wireless communication devices, near field communication devices, energy harvesting designs, mobile devices, and wireless communication devices. It will focus on how automated circuit sizing and tuning methodologies can be used to enhance existing design expertise to reduce power consumption while trade-off with other circuit performances. Additionally it will be shown how features like circuit sensitivity analysis can be used for confirming design hypotheses. Using such a verification and optimization environment can help systematically and fully explore design's operating, design and statistical design space.
{"title":"Low power circuit optimization for IoT","authors":"M. Pronath","doi":"10.1109/SOCC.2017.8225982","DOIUrl":"https://doi.org/10.1109/SOCC.2017.8225982","url":null,"abstract":"Designing circuits for enhanced IoT (“Internet of Things”) applications is one of the current growth driver for the electronics industry. Optimizing such circuits for lowest power consumption while maximize functionality and performance is key for successful implementation of such circuits in the IoT systems. IoT devices are diverse in nature but are typically constrained by limited power availability, limited area budget and the need for modularity of design. The burden of ultra-low-power budget unfortunately doesn't necessarily mean that other performance requirements are relaxed. The tutorial is therefore geared towards designers of IoT devices including sensors, MEMS, mobile devices, medical sensors, wireless communication devices, near field communication devices, energy harvesting designs, mobile devices, and wireless communication devices. It will focus on how automated circuit sizing and tuning methodologies can be used to enhance existing design expertise to reduce power consumption while trade-off with other circuit performances. Additionally it will be shown how features like circuit sensitivity analysis can be used for confirming design hypotheses. Using such a verification and optimization environment can help systematically and fully explore design's operating, design and statistical design space.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114809363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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