The paper studies the field failure of a radio frequency differential amplifier in the 5G Active Antenna Unit base station; gallium arsenide(GaAs) die substrate crack was found through failure analysis on the returned units. Packaging process investigation found ejector marks on the blue film were abnormal when executing die bonding. Some amplifiers with slight cracks have passed the functional test, and base station manufacturers’ production test has not effectively intercepted the defect units. Eventually, defect units outflow and fail during field operation. Through the statistics of failure time and reliability data analysis, the results show that the failure is a typical log-normal distribution with a correlation coefficient of 0.87, and the failure rate decreases with time, indicating that the case belongs to an early failure, which once again proves the theory that the early failure is the outflow of defective products. It is estimated that the cumulative failure ratio in 1 year is 0.58% which was confirmed by actual field performance. This study can be a reference for die crack failure analysis and its reliability risk prediction.
{"title":"GaAs RF Amplifier Field Failure Analysis and Reliability Prediction in 5G AAU System","authors":"Lin Shi, Chong Wang, Xiaolong Cai, Zhengya Cao, Xiao-hua Ma, Xiangyang Duan","doi":"10.1109/IPFA55383.2022.9915740","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915740","url":null,"abstract":"The paper studies the field failure of a radio frequency differential amplifier in the 5G Active Antenna Unit base station; gallium arsenide(GaAs) die substrate crack was found through failure analysis on the returned units. Packaging process investigation found ejector marks on the blue film were abnormal when executing die bonding. Some amplifiers with slight cracks have passed the functional test, and base station manufacturers’ production test has not effectively intercepted the defect units. Eventually, defect units outflow and fail during field operation. Through the statistics of failure time and reliability data analysis, the results show that the failure is a typical log-normal distribution with a correlation coefficient of 0.87, and the failure rate decreases with time, indicating that the case belongs to an early failure, which once again proves the theory that the early failure is the outflow of defective products. It is estimated that the cumulative failure ratio in 1 year is 0.58% which was confirmed by actual field performance. This study can be a reference for die crack failure analysis and its reliability risk prediction.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128715244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915776
Eyal Weiss
A large-scale evaluation of the quality of electronic components at the time of the electronic board assembly is presented. Counterfeit components are often recycled or old component, therefore, the quality of components and the soldering leads is a good indicator of the component’s authenticity. The quality of the components is evaluated based on their visual appearance by quantifying their visual defects and the corrosion evidence as they appear on the component and its soldering leads. The effect of body defects and corrosion in the soldering leads on the reliability of the component bond to the board is reviewed. A machine learning method to detect body defects and evidence of corrosion on soldering leads is presented. Over 11 million components images were inspected by the presented AI algorithm. It is shown that 290 components out of a million had body visual defects that cannot be seen by conventional AOI. In addition, over 1,100 out of million had visible corrosion evidence on their soldering leads. Corrosion on the soldering not only affects the production yield but is the most common cause for random statistical failures in the field resulting in products failure. The presented method allows inspection of all the components used in production thus reducing the risk of failures in the field caused by poor quality electronic components originating from counterfeit, and poor storage or handling conditions.
{"title":"AI Detection of Body Defects and Corrosion on Leads in Electronic Components, and a study of their Occurrence","authors":"Eyal Weiss","doi":"10.1109/IPFA55383.2022.9915776","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915776","url":null,"abstract":"A large-scale evaluation of the quality of electronic components at the time of the electronic board assembly is presented. Counterfeit components are often recycled or old component, therefore, the quality of components and the soldering leads is a good indicator of the component’s authenticity. The quality of the components is evaluated based on their visual appearance by quantifying their visual defects and the corrosion evidence as they appear on the component and its soldering leads. The effect of body defects and corrosion in the soldering leads on the reliability of the component bond to the board is reviewed. A machine learning method to detect body defects and evidence of corrosion on soldering leads is presented. Over 11 million components images were inspected by the presented AI algorithm. It is shown that 290 components out of a million had body visual defects that cannot be seen by conventional AOI. In addition, over 1,100 out of million had visible corrosion evidence on their soldering leads. Corrosion on the soldering not only affects the production yield but is the most common cause for random statistical failures in the field resulting in products failure. The presented method allows inspection of all the components used in production thus reducing the risk of failures in the field caused by poor quality electronic components originating from counterfeit, and poor storage or handling conditions.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128746547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915706
A. S. Nair, P. Hoffrogge, P. Czurratis, E. Kuehnicke, Mario Wolf
More effective Failure Analysis (FA) technologies are required to meet the upcoming challenges in complex semiconductor devices. Because of recent advances in AI (Artificial Intelligence), we can now concentrate our efforts on developing AI-based algorithms for high precision-automated signal interpretation for failure detection in Scanning Acoustic Microscopes (SAM). Typically, flaw detection in ultrasonic data relies heavily on human expertise, and the majority of automated classifications are based on image-based decision algorithms. For defect classification, the image-based ML approach necessitates a large dataset. On signals, the traditional machine learning approach requires manual feature extraction and selection of the best features. DL approaches are commonly used to automate feature learning and classification from raw signals. This paper proposes a method for creating datasets, preprocessing signals, and semi-supervised signal training for defect classification. For performance evaluation, different DL architectures such as 1D CNN, RNN, and hybrid networks were studied. The models were trained to categorize C4 bumps in flip chips into a defect and intact classes. Even with fewer learnable, 1D-CNN with wavelet applied A-Scan as input outperforms other models with an accuracy of up to 99 percent. The model was then validated by destructive analysis on an unknown sample.
{"title":"Automated Defect Classification In Semiconductor Devices Using Deep Learning Networks","authors":"A. S. Nair, P. Hoffrogge, P. Czurratis, E. Kuehnicke, Mario Wolf","doi":"10.1109/IPFA55383.2022.9915706","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915706","url":null,"abstract":"More effective Failure Analysis (FA) technologies are required to meet the upcoming challenges in complex semiconductor devices. Because of recent advances in AI (Artificial Intelligence), we can now concentrate our efforts on developing AI-based algorithms for high precision-automated signal interpretation for failure detection in Scanning Acoustic Microscopes (SAM). Typically, flaw detection in ultrasonic data relies heavily on human expertise, and the majority of automated classifications are based on image-based decision algorithms. For defect classification, the image-based ML approach necessitates a large dataset. On signals, the traditional machine learning approach requires manual feature extraction and selection of the best features. DL approaches are commonly used to automate feature learning and classification from raw signals. This paper proposes a method for creating datasets, preprocessing signals, and semi-supervised signal training for defect classification. For performance evaluation, different DL architectures such as 1D CNN, RNN, and hybrid networks were studied. The models were trained to categorize C4 bumps in flip chips into a defect and intact classes. Even with fewer learnable, 1D-CNN with wavelet applied A-Scan as input outperforms other models with an accuracy of up to 99 percent. The model was then validated by destructive analysis on an unknown sample.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114350436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915737
Selene Lobnig, C. Burmer, Konstantin Schekotihin
Failure analysis (FA) in semiconductors is an error-prone and knowledge-intensive activity. Therefore, timely support of engineers with information about past analyses, best practices, or technical data is crucial for successful FA operations. Unfortunately, in many cases application of modern Artificial Intelligence (AI) methods is limited since most of the data is stored in human-readable formats only, thus, making its automatic processing impossible. In this paper, we consider a problem of method detection from images made by different tools used in FA. We show that the proposed deep learning technique can successfully recognize methods from various images made in an FA lab with an accuracy of 91%. In addition, we investigate the transferability of our results to images of other labs. Obtained results show a slight drop in accuracy to 82%, which can be improved by fine-tuning a model on data from other labs.
{"title":"Detection of Failure Analysis Methods with Image Classification","authors":"Selene Lobnig, C. Burmer, Konstantin Schekotihin","doi":"10.1109/IPFA55383.2022.9915737","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915737","url":null,"abstract":"Failure analysis (FA) in semiconductors is an error-prone and knowledge-intensive activity. Therefore, timely support of engineers with information about past analyses, best practices, or technical data is crucial for successful FA operations. Unfortunately, in many cases application of modern Artificial Intelligence (AI) methods is limited since most of the data is stored in human-readable formats only, thus, making its automatic processing impossible. In this paper, we consider a problem of method detection from images made by different tools used in FA. We show that the proposed deep learning technique can successfully recognize methods from various images made in an FA lab with an accuracy of 91%. In addition, we investigate the transferability of our results to images of other labs. Obtained results show a slight drop in accuracy to 82%, which can be improved by fine-tuning a model on data from other labs.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127170910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915750
Ye Chen, Jie Zhu
In this paper we demonstrate the analytical method using energy-filtered TEM (EFTEM) in gate oxide breakdown defect analysis for semiconductor devices. We discuss the limitation of normal high-resolution TEM (HRTEM) imaging on gate oxide breakdown defect characterization and how EFTEM help on the contrast enhancement. We discuss three case studies utilizing EFTEM for the defect characterization. In each case study, EFTEM is used to observe gate oxide breakdown defect for both NMOS and PMOS failure for relatively thicker TEM samples to give more accurate analysis of the gate oxide breakdown mechanisms for the root-cause understanding.
{"title":"Use of Energy Filtered TEM to Observe Gate Oxide Breakdown Defects","authors":"Ye Chen, Jie Zhu","doi":"10.1109/IPFA55383.2022.9915750","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915750","url":null,"abstract":"In this paper we demonstrate the analytical method using energy-filtered TEM (EFTEM) in gate oxide breakdown defect analysis for semiconductor devices. We discuss the limitation of normal high-resolution TEM (HRTEM) imaging on gate oxide breakdown defect characterization and how EFTEM help on the contrast enhancement. We discuss three case studies utilizing EFTEM for the defect characterization. In each case study, EFTEM is used to observe gate oxide breakdown defect for both NMOS and PMOS failure for relatively thicker TEM samples to give more accurate analysis of the gate oxide breakdown mechanisms for the root-cause understanding.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125796957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915725
Saidaliah Sarip, John Carlo Francisco, Tejinder Gandhi, Che-Ping Chen, Jed Paolo Deligente, Jonathan Azares
Electrical Overstress (EOS) is a widely known problem in the semiconductor industry. Oftentimes, EOS damage occurs on a systemic manner at a certain location of the die. In this paper, multi-channel data-acquisition devices were returned for analysis to solve repetitive EOS symptoms of failure. We present two (2) case studies of the customer-returned devices that show anomalous passivation layer resulting in secondary EOS damages at Metal 2. This leads to an in-depth analysis of the EOS phenomena that we traced back at the wafer-level where process and electrical root cause were determined.
{"title":"Deep Dive into Systemic Secondary EOS Damage caused by a Process-Related Issue","authors":"Saidaliah Sarip, John Carlo Francisco, Tejinder Gandhi, Che-Ping Chen, Jed Paolo Deligente, Jonathan Azares","doi":"10.1109/IPFA55383.2022.9915725","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915725","url":null,"abstract":"Electrical Overstress (EOS) is a widely known problem in the semiconductor industry. Oftentimes, EOS damage occurs on a systemic manner at a certain location of the die. In this paper, multi-channel data-acquisition devices were returned for analysis to solve repetitive EOS symptoms of failure. We present two (2) case studies of the customer-returned devices that show anomalous passivation layer resulting in secondary EOS damages at Metal 2. This leads to an in-depth analysis of the EOS phenomena that we traced back at the wafer-level where process and electrical root cause were determined.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125821560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915721
K. H. Yip, P. Ang, K. Lee, Y. Yeo, Z. Mo
Focused ion beam (FIB) technique has been widely used in Si base semiconductor for cross sectioning sample preparation to a scale of nanometers accuracy. As FIB involve removing material with high ion energy, inevitably damage will be induced on the sample surface. This paper addresses the effect of FIB induced damage in silicon for junction staining and poly silicon profile delineation application. This damage will prevent junction stain chemical mixture to effectively stained out the P-type and N-type implantation. Additionally, it also caused damage on poly silicon and silicon substrate after buffered oxide etch (BOE) staining on FIB prepared cross sectioning samples. The effectiveness of argon sputter clean on FIB induced damage reduction has been studied with different duration. Successful junction stain result and wet chemical delineation of poly silicon profile on FIB prepared sample were achieved with optimized Argon sputter clean timing.
{"title":"Reduction of FIB induced damage in silicon with Argon sputter clean","authors":"K. H. Yip, P. Ang, K. Lee, Y. Yeo, Z. Mo","doi":"10.1109/IPFA55383.2022.9915721","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915721","url":null,"abstract":"Focused ion beam (FIB) technique has been widely used in Si base semiconductor for cross sectioning sample preparation to a scale of nanometers accuracy. As FIB involve removing material with high ion energy, inevitably damage will be induced on the sample surface. This paper addresses the effect of FIB induced damage in silicon for junction staining and poly silicon profile delineation application. This damage will prevent junction stain chemical mixture to effectively stained out the P-type and N-type implantation. Additionally, it also caused damage on poly silicon and silicon substrate after buffered oxide etch (BOE) staining on FIB prepared cross sectioning samples. The effectiveness of argon sputter clean on FIB induced damage reduction has been studied with different duration. Successful junction stain result and wet chemical delineation of poly silicon profile on FIB prepared sample were achieved with optimized Argon sputter clean timing.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126066672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915712
Miao Cai, S. Leang, Kok Wai Chew, P. Tan, A. P. Herlambang, Chunxiang Zhu, Yongxin Guo
Reverse body bias (RBB) stress impact on high-voltage (HV) n-Type extended-drain MOSFET (EDMOS) has been investigated in this paper. Two-step degradation behavior of sub-threshold voltage (Vth) has been observed. At RBB stress lower than -1.25V, there is minor impact of RBB stress on hot carrier induced Vth shift. However, when the stress reaches around -2.5V, the Vth degradation increases significantly and has strong correlation with the RBB stress. Technology computer-aided design (TCAD) simulation shows that the Body/Source junction is reverse biased under large RBB stress therefore band to band tunneling current is generated at the interface near source side. High electric field enhances hot-electron trapping towards gate oxide in the channel region, resulting in large Vth shift after stressing. An equivalent reliability model has been developed based on this phenomenon, and the improved model fits well with the silicon data.
{"title":"Analysis and Modeling for Reverse Body Bias Stress Impact on HCI Induced Degradation in n-Type EDMOS","authors":"Miao Cai, S. Leang, Kok Wai Chew, P. Tan, A. P. Herlambang, Chunxiang Zhu, Yongxin Guo","doi":"10.1109/IPFA55383.2022.9915712","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915712","url":null,"abstract":"Reverse body bias (RBB) stress impact on high-voltage (HV) n-Type extended-drain MOSFET (EDMOS) has been investigated in this paper. Two-step degradation behavior of sub-threshold voltage (Vth) has been observed. At RBB stress lower than -1.25V, there is minor impact of RBB stress on hot carrier induced Vth shift. However, when the stress reaches around -2.5V, the Vth degradation increases significantly and has strong correlation with the RBB stress. Technology computer-aided design (TCAD) simulation shows that the Body/Source junction is reverse biased under large RBB stress therefore band to band tunneling current is generated at the interface near source side. High electric field enhances hot-electron trapping towards gate oxide in the channel region, resulting in large Vth shift after stressing. An equivalent reliability model has been developed based on this phenomenon, and the improved model fits well with the silicon data.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124216354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915724
Bardon Cui
A System-In-Package (SIP) chip failed after 240 cycle temperature cycle test. Electrical test results suggested that the failure was due to an open circuit. . This SIP chip was built with a three layers structure. The upper and lower modules are interconnected through an interposer die. Based solely on the ATE results, the faulty cell could not be located. . Use of standard analysis techniques such as 3D X-ray imaging and Confocal Scanning Acoustic Microscopy (CSAM) was not enough to localize the defect. The fault location was isolated by laser decapsulation and probing, and the open circuit was confirmed to be in the interposer die. Use of parallel grinding was a key enabler to succeed in this analysis. From this, a new workflow was developed for fault isolation in SIP IC. The gradual reduction in candidate locations for the failure root cause was decisive in this analysis.
{"title":"Failure Analysis for SIP IC after TC reliability test","authors":"Bardon Cui","doi":"10.1109/IPFA55383.2022.9915724","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915724","url":null,"abstract":"A System-In-Package (SIP) chip failed after 240 cycle temperature cycle test. Electrical test results suggested that the failure was due to an open circuit. . This SIP chip was built with a three layers structure. The upper and lower modules are interconnected through an interposer die. Based solely on the ATE results, the faulty cell could not be located. . Use of standard analysis techniques such as 3D X-ray imaging and Confocal Scanning Acoustic Microscopy (CSAM) was not enough to localize the defect. The fault location was isolated by laser decapsulation and probing, and the open circuit was confirmed to be in the interposer die. Use of parallel grinding was a key enabler to succeed in this analysis. From this, a new workflow was developed for fault isolation in SIP IC. The gradual reduction in candidate locations for the failure root cause was decisive in this analysis.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"3 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124379594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915727
S. Moon, D. Nagalingam, Y. Ngow, A. Quah
Software based scan diagnosis is the de facto method for debugging logic scan failures. Physical analysis success rate is high on dies diagnosed with maximum score, one symptom, one suspect and shorter net. This poses a limitation on maximum utilization of scan diagnosis data for PFA. There have been several attempts to combine dynamic fault isolation techniques with scan diagnosis results to enhance the utilization and success rate. However, it is not a feasible approach for foundry due to limited product design and test knowledge and hardware requirements such as probe card and tester. Suitable for a foundry, an enhanced diagnosis-driven analysis scheme was proposed in [1] that classifies the failures as frontend-of-line (FEOL) and backend-of-line (BEOL) improving the die selection process for PFA. In this paper, static NIR PEM and defect prediction approach are applied on dies that are already classified as FEOL and BEOL failures yet considered unsuitable for PFA due to low score, multiple symptoms, and suspects. Successful case studies are highlighted to showcase the effectiveness of using static NIR PEM as the next level screening process to further maximize the scan diagnosis data utilization.
{"title":"Combining Enhanced Diagnostic-Driven Analysis Scheme and Static Near Infrared Photon Emission Microscopy for Effective Scan Failure Debug","authors":"S. Moon, D. Nagalingam, Y. Ngow, A. Quah","doi":"10.1109/IPFA55383.2022.9915727","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915727","url":null,"abstract":"Software based scan diagnosis is the de facto method for debugging logic scan failures. Physical analysis success rate is high on dies diagnosed with maximum score, one symptom, one suspect and shorter net. This poses a limitation on maximum utilization of scan diagnosis data for PFA. There have been several attempts to combine dynamic fault isolation techniques with scan diagnosis results to enhance the utilization and success rate. However, it is not a feasible approach for foundry due to limited product design and test knowledge and hardware requirements such as probe card and tester. Suitable for a foundry, an enhanced diagnosis-driven analysis scheme was proposed in [1] that classifies the failures as frontend-of-line (FEOL) and backend-of-line (BEOL) improving the die selection process for PFA. In this paper, static NIR PEM and defect prediction approach are applied on dies that are already classified as FEOL and BEOL failures yet considered unsuitable for PFA due to low score, multiple symptoms, and suspects. Successful case studies are highlighted to showcase the effectiveness of using static NIR PEM as the next level screening process to further maximize the scan diagnosis data utilization.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125641997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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