Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915747
Hoseok Song, Ki-Jong Lee, Yong H. Lee
A novel failure analysis (FA) method was developed for the identification of failure root cause in a display device. Conventionally, FA on display failure requires the components to be detached from the integrated display device, which involves potentially destructive steps. These may result in an alteration of the defect, preventing a precise localization and further analysis of the failure root cause of display failure. To overcome this issue, a specific FA workflow involving in-place analysis was developed. It enabled a successful localization and characterization of the defect via emission analysis from both sides of the device and cross-sectional analysis. With this new workflow, the manufacturing step responsible for the defect was well identified. This makes FA result of display failure clearer enough to give feedback to manufacturing line for process rectification.
{"title":"Novel Approach to Display Failure on OLED Display Device","authors":"Hoseok Song, Ki-Jong Lee, Yong H. Lee","doi":"10.1109/IPFA55383.2022.9915747","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915747","url":null,"abstract":"A novel failure analysis (FA) method was developed for the identification of failure root cause in a display device. Conventionally, FA on display failure requires the components to be detached from the integrated display device, which involves potentially destructive steps. These may result in an alteration of the defect, preventing a precise localization and further analysis of the failure root cause of display failure. To overcome this issue, a specific FA workflow involving in-place analysis was developed. It enabled a successful localization and characterization of the defect via emission analysis from both sides of the device and cross-sectional analysis. With this new workflow, the manufacturing step responsible for the defect was well identified. This makes FA result of display failure clearer enough to give feedback to manufacturing line for process rectification.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123422780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915765
I. Tee, Jie Zhu
Transmission electron microscope (TEM) failure analysis has been widely adopted in the field of semiconductor manufacturing because of its ability to provide high resolution measurement and elemental characterization in (sub) nanometer scale. Despite many advantages of the TEM technique, one challenge that the conventional sample preparation by Focused Ion Beam (FIB) is limitations on the TEM lamella size, structure, or pattern of the target. In this work, we demonstrate how TEM lamellas were prepared on a suspended structure with deep cavity. In the first case study, proper selection of coating materials with tilted angle deposition and use of in-situ lift-out technique are critical for successful sample preparation to study thin residue layer along large sidewall of a suspended structure. In the second case study, application of fine cleaving and sample reorientation enabled us to prepare an artifact-free sample to characterize post-etch residue at the bottom of a very deep cavity.
{"title":"TEM sample preparation for a suspended structure with deep cavity","authors":"I. Tee, Jie Zhu","doi":"10.1109/IPFA55383.2022.9915765","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915765","url":null,"abstract":"Transmission electron microscope (TEM) failure analysis has been widely adopted in the field of semiconductor manufacturing because of its ability to provide high resolution measurement and elemental characterization in (sub) nanometer scale. Despite many advantages of the TEM technique, one challenge that the conventional sample preparation by Focused Ion Beam (FIB) is limitations on the TEM lamella size, structure, or pattern of the target. In this work, we demonstrate how TEM lamellas were prepared on a suspended structure with deep cavity. In the first case study, proper selection of coating materials with tilted angle deposition and use of in-situ lift-out technique are critical for successful sample preparation to study thin residue layer along large sidewall of a suspended structure. In the second case study, application of fine cleaving and sample reorientation enabled us to prepare an artifact-free sample to characterize post-etch residue at the bottom of a very deep cavity.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127702321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915766
Teck Leong Wee, Handoko Linewih, Sally Chwa, P. K. Tan, A. Quah, P. T. Ng, Hnin Hnin Won, Thoungh Ma, Fransiscus Rivai
This paper demonstrates the use of Current Imaging, Atomic Force Probing (AFP) and Focus Exposure Matrix (FEM) analysis to identify the root cause of high leakage current issue in Static Random-Access Memory (SRAM) array in the product. Through current imaging and AFP probing, abnormal current image contrast was observed on the P-Channel Field Effect Transistor (PFET) of bad SRAM bit cells. Further physical failure analysis by delayering and Transmission Electron Microscopy (TEM) found no physical-related defect. This indicates that the high leak path is caused by front-end of line (FEOL) process-related issue. The AFP analysis results indicate a possible implant-related issue. Focus Exposure Matrix (FEM) analysis was carried out on an implant mask and the results correlate well to the SRAM leakage, which suggests counter-doping due to insufficient resist coverage that leads to a new product mask evaluation.
{"title":"Atomic Force Probing and Focus Exposure Matrix Analysis to Resolve High Leakage Current Failure on SRAM","authors":"Teck Leong Wee, Handoko Linewih, Sally Chwa, P. K. Tan, A. Quah, P. T. Ng, Hnin Hnin Won, Thoungh Ma, Fransiscus Rivai","doi":"10.1109/IPFA55383.2022.9915766","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915766","url":null,"abstract":"This paper demonstrates the use of Current Imaging, Atomic Force Probing (AFP) and Focus Exposure Matrix (FEM) analysis to identify the root cause of high leakage current issue in Static Random-Access Memory (SRAM) array in the product. Through current imaging and AFP probing, abnormal current image contrast was observed on the P-Channel Field Effect Transistor (PFET) of bad SRAM bit cells. Further physical failure analysis by delayering and Transmission Electron Microscopy (TEM) found no physical-related defect. This indicates that the high leak path is caused by front-end of line (FEOL) process-related issue. The AFP analysis results indicate a possible implant-related issue. Focus Exposure Matrix (FEM) analysis was carried out on an implant mask and the results correlate well to the SRAM leakage, which suggests counter-doping due to insufficient resist coverage that leads to a new product mask evaluation.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129550189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915720
Nathan Jessurun, Jacob Harrison, M. Tehranipoor, N. Asadizanjani
Automated optical inspection (AOI) is used to verify quality of printed circuit board (PCB) assembly and has been proposed for detecting counterfeit components and malicious "trojan" PCB modifications. Component pin localization and characterization is an important step in both of these processes. We present PinPoint: a computer vision algorithm which extracts pin information from surface-mount device (SMD) contours. PinPoint is robust against contour noise, component size, and package type. We evaluate PinPoint against a sample of SMD contours and show that it achieves remarkable performance. Our algorithm could serve as an efficient pin localization step in traditional assembly quality checks and can support future efforts to extract expensive-to-forge characteristics of SMD packages to improve optical assurance.
{"title":"PinPoint: An SMD Pin Localization Method","authors":"Nathan Jessurun, Jacob Harrison, M. Tehranipoor, N. Asadizanjani","doi":"10.1109/IPFA55383.2022.9915720","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915720","url":null,"abstract":"Automated optical inspection (AOI) is used to verify quality of printed circuit board (PCB) assembly and has been proposed for detecting counterfeit components and malicious \"trojan\" PCB modifications. Component pin localization and characterization is an important step in both of these processes. We present PinPoint: a computer vision algorithm which extracts pin information from surface-mount device (SMD) contours. PinPoint is robust against contour noise, component size, and package type. We evaluate PinPoint against a sample of SMD contours and show that it achieves remarkable performance. Our algorithm could serve as an efficient pin localization step in traditional assembly quality checks and can support future efforts to extract expensive-to-forge characteristics of SMD packages to improve optical assurance.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128969272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915749
Chengjie Xi, Aslam A. Khan, Nathan Jessurun, Nidish Vashisthan, M. Tehranipoor, N. Asadizanjani
Integrated Circuit (IC) hardware assurance is an increasingly concerning topic for semiconductor industries. Because ICs are the industries’ fundamental building blocks, they are consistently targeted for adversarial attacks. Physical inspection methods (i.e., Scanning Electron Microscopy (SEM), X-ray, and THz) are used to verify the IC hardware from the transistor to the device level. However, these inspection methods are difficult to apply to emerging packaging technologies and Heterogeneous Integration (HI) due to their inherent limitations and sample complexity. HI complex nature can provide some inherent features employable as countermeasures. For instance, the material and the structural fingerprints can be used to monitor, verify, and provide device assurance. This paper will introduce potential security vulnerabilities in HI hardware and review various physical inspection methods and their limitations surrounding comprehensive assurance. Both non-destructive and destructive methods will be discussed, ranging from material/structural analysis to transistor-level physical inspection. Insights to the MEMS & NEMS implantation into the package to secure the original design, will be also explored in this paper.
{"title":"Physical Assurance for Heterogeneous Integration: Challenges and Opportunities","authors":"Chengjie Xi, Aslam A. Khan, Nathan Jessurun, Nidish Vashisthan, M. Tehranipoor, N. Asadizanjani","doi":"10.1109/IPFA55383.2022.9915749","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915749","url":null,"abstract":"Integrated Circuit (IC) hardware assurance is an increasingly concerning topic for semiconductor industries. Because ICs are the industries’ fundamental building blocks, they are consistently targeted for adversarial attacks. Physical inspection methods (i.e., Scanning Electron Microscopy (SEM), X-ray, and THz) are used to verify the IC hardware from the transistor to the device level. However, these inspection methods are difficult to apply to emerging packaging technologies and Heterogeneous Integration (HI) due to their inherent limitations and sample complexity. HI complex nature can provide some inherent features employable as countermeasures. For instance, the material and the structural fingerprints can be used to monitor, verify, and provide device assurance. This paper will introduce potential security vulnerabilities in HI hardware and review various physical inspection methods and their limitations surrounding comprehensive assurance. Both non-destructive and destructive methods will be discussed, ranging from material/structural analysis to transistor-level physical inspection. Insights to the MEMS & NEMS implantation into the package to secure the original design, will be also explored in this paper.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121229045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915705
Wei-Cheng Chu, B. Tsai, H. Yoshida, Yi-Heng Chen, Yung-Lung Hsu
The Ibmax (Maximum Substrate Current) of general LDNMOS has two peaks, one is located at Ndrift (N drift region) under Gox, far from the pinch-off point, while the other is close to the pinch-off point [1]. Considering the actual application of the component, we chose the first peak for HCI (Hot Carrier Injection) stress, and found that the 32V symmetry STI-LDNMOS (Shallow Trench Isolation Lateral Diffusion) on different platforms (A and B) seem to have different reasons for burning. The experimental data shows that the component burnout of platform A is similar to the papers published by the authors [2], that is, HCI stress will degrade the diode characteristics of drain to bulk, making the maximum electric field closer to the drain terminal and the kirk effect of IbVg worse. What's interesting is that during the HCI stress of the components on platform B, the measured IdVd, IbVd and IbVg do not have the signs of burning like those of platform A. In order to clarify the reason for its burning, we performed a series of experiments, and finally proved that it may originate from BJT (Bipolar Junction Transistor) being turned on, not HCI induced TDDB (Time Dependent Dielectric Breakdown). Finally, in order to save costs, we chose to change the process conditions of LDNH2 (Ndrift is near the channel) for reducing the implant energy and increasing the concentration to solve the burn-out problem and pass the criteria.
{"title":"Case Study For STI-LDNMOS Burned During HCI Stress to Passing Reliability Specifications","authors":"Wei-Cheng Chu, B. Tsai, H. Yoshida, Yi-Heng Chen, Yung-Lung Hsu","doi":"10.1109/IPFA55383.2022.9915705","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915705","url":null,"abstract":"The Ibmax (Maximum Substrate Current) of general LDNMOS has two peaks, one is located at Ndrift (N drift region) under Gox, far from the pinch-off point, while the other is close to the pinch-off point [1]. Considering the actual application of the component, we chose the first peak for HCI (Hot Carrier Injection) stress, and found that the 32V symmetry STI-LDNMOS (Shallow Trench Isolation Lateral Diffusion) on different platforms (A and B) seem to have different reasons for burning. The experimental data shows that the component burnout of platform A is similar to the papers published by the authors [2], that is, HCI stress will degrade the diode characteristics of drain to bulk, making the maximum electric field closer to the drain terminal and the kirk effect of IbVg worse. What's interesting is that during the HCI stress of the components on platform B, the measured IdVd, IbVd and IbVg do not have the signs of burning like those of platform A. In order to clarify the reason for its burning, we performed a series of experiments, and finally proved that it may originate from BJT (Bipolar Junction Transistor) being turned on, not HCI induced TDDB (Time Dependent Dielectric Breakdown). Finally, in order to save costs, we chose to change the process conditions of LDNH2 (Ndrift is near the channel) for reducing the implant energy and increasing the concentration to solve the burn-out problem and pass the criteria.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122522479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915732
F. Palumbo, M. Klebanov, G. Monreal, S. Chetlur
It is well established that the bias temperature instability (BTI) mechanism alters the Vth distribution with reliability implications to balanced analog circuits. This paper presents a deep understanding of the mechanisms involved in the permanent components of BTI effects that dominate the long-term reliability projections. By use of CV measurements, the energetic distribution of traps in the bandgap was studied where hydrogen reactions are linked to the positive charge buildup.
{"title":"Physical origin of the permanent components of the positive charge buildup resulting from NBTI/PBTI stress in nMOS/pMOS transistors","authors":"F. Palumbo, M. Klebanov, G. Monreal, S. Chetlur","doi":"10.1109/IPFA55383.2022.9915732","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915732","url":null,"abstract":"It is well established that the bias temperature instability (BTI) mechanism alters the Vth distribution with reliability implications to balanced analog circuits. This paper presents a deep understanding of the mechanisms involved in the permanent components of BTI effects that dominate the long-term reliability projections. By use of CV measurements, the energetic distribution of traps in the bandgap was studied where hydrogen reactions are linked to the positive charge buildup.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123220697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915773
Xin Yang, Yongkang Xue, Z. Dong, Chaolun Wang, Zhigang Ji, Chihang Tsai, Yongren Wu, Weisong Yu, Runsheng Wang, Xing Wu
Reliability issues of semiconductors devices are always related with defects accumulation. Repeatedly switching processes of a semiconductor device could induce the defects accumulation which results in performance degradation. Bulk fin field-effect transistor (FinFET) devices, with a miniaturized three-dimensional structure, have a more complex reliability mechanism that requires detailed research. In this experiment, failure analysis was studied on the same batch of the FinFET devices which suffered performance degradation aging tests at different stress time. During this process, the magnitude of each applied electrical current was not exceeded the operating current. In this work, microstructural and chemical elements differences were characterized by transmission electron microscopy. It is founded that the interconnection part next to the core fin structure was destructed under the electrical over stress (EOS). These phenomena were not observed in the normal FinFET. It can be concluded that the effective contact area of the interconnection part decreased, resulting in the increased internal electrical field. Tungsten (W), as the metal 0 (M0) layer, migrated under defects accumulation. This work paves a guideline for the reliability improvements of FinFET.
{"title":"Interconnection Reliability on FinFET Devices","authors":"Xin Yang, Yongkang Xue, Z. Dong, Chaolun Wang, Zhigang Ji, Chihang Tsai, Yongren Wu, Weisong Yu, Runsheng Wang, Xing Wu","doi":"10.1109/IPFA55383.2022.9915773","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915773","url":null,"abstract":"Reliability issues of semiconductors devices are always related with defects accumulation. Repeatedly switching processes of a semiconductor device could induce the defects accumulation which results in performance degradation. Bulk fin field-effect transistor (FinFET) devices, with a miniaturized three-dimensional structure, have a more complex reliability mechanism that requires detailed research. In this experiment, failure analysis was studied on the same batch of the FinFET devices which suffered performance degradation aging tests at different stress time. During this process, the magnitude of each applied electrical current was not exceeded the operating current. In this work, microstructural and chemical elements differences were characterized by transmission electron microscopy. It is founded that the interconnection part next to the core fin structure was destructed under the electrical over stress (EOS). These phenomena were not observed in the normal FinFET. It can be concluded that the effective contact area of the interconnection part decreased, resulting in the increased internal electrical field. Tungsten (W), as the metal 0 (M0) layer, migrated under defects accumulation. This work paves a guideline for the reliability improvements of FinFET.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115254012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915731
Prantik Mahajan, Vishal Ganesan, N. Subramani, Ruchil Jain, S. Mitra, R. Gauthier
Best-in-class (BIC) High-Voltage (HV) Electrostatic Discharge (ESD) solutions for 8-12V power pad protection in first-of-its-kind GlobalFoundries® 28nm low-cost BCDLite process are evaluated. A comparative analysis between different types of devices, namely gate-grounded NMOS (GGNMOS), NPN, PNP and Diode, showing DC & 100ns Transmission Line Pulse (TLP) performance from Technology Computer-Aided Design (TCAD) simulations and silicon measurement results with performance metrics in terms of core device ESD protection effectiveness w.r.t Safe Operating Area (SOA) boundary and key Figures of Merit (FOMs) is elucidated.
{"title":"High-Voltage Electrostatic Discharge Protection Device development in 28nm BCDLite Technology","authors":"Prantik Mahajan, Vishal Ganesan, N. Subramani, Ruchil Jain, S. Mitra, R. Gauthier","doi":"10.1109/IPFA55383.2022.9915731","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915731","url":null,"abstract":"Best-in-class (BIC) High-Voltage (HV) Electrostatic Discharge (ESD) solutions for 8-12V power pad protection in first-of-its-kind GlobalFoundries® 28nm low-cost BCDLite process are evaluated. A comparative analysis between different types of devices, namely gate-grounded NMOS (GGNMOS), NPN, PNP and Diode, showing DC & 100ns Transmission Line Pulse (TLP) performance from Technology Computer-Aided Design (TCAD) simulations and silicon measurement results with performance metrics in terms of core device ESD protection effectiveness w.r.t Safe Operating Area (SOA) boundary and key Figures of Merit (FOMs) is elucidated.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130972478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915754
Shang Jiantong, Yang Gang, Song Yong, Yu Hongjun, Chen Chuncheng
This paper explores the influence factors of warpage of the light guide plate (LGP) by conducting the reliability experiments. The results show that the warpage of the LGP is mainly caused by uneven stress release under the thermal shock test (TST) condition, while the warpage of the LGP under the high temperature & humidity test (THS) condition is mainly caused by the interactive compression of LGP and the mold frame. The study provides a theoretical basis for the design of LGP in backlight module and can effectively reduce the incidence of warpage and deformation in the LGP.
{"title":"Research on the factors affecting warpage of the light guide plate in the process of reliability","authors":"Shang Jiantong, Yang Gang, Song Yong, Yu Hongjun, Chen Chuncheng","doi":"10.1109/IPFA55383.2022.9915754","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915754","url":null,"abstract":"This paper explores the influence factors of warpage of the light guide plate (LGP) by conducting the reliability experiments. The results show that the warpage of the LGP is mainly caused by uneven stress release under the thermal shock test (TST) condition, while the warpage of the LGP under the high temperature & humidity test (THS) condition is mainly caused by the interactive compression of LGP and the mold frame. The study provides a theoretical basis for the design of LGP in backlight module and can effectively reduce the incidence of warpage and deformation in the LGP.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131209879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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