Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915782
Shih-Hui Lin
It has been reported, that EM lifetime of Ti/Al-Cu structure is shorter than that of Ti/TiN/Al-Cu structure. Our study shows that the lifetime of Ti/ALPS Al-Cu structure is better than Ti/TiN/ALPS Al-Cu. In this paper, we will discuss the effect of the Glue layer -Ti/TiN & Ti, and the effect of the AlCu processes-Hot Al and ALPS/Hot Al to explain the main reasons. After the study, we found Ti /ALPS/Hot Al-Cu has the best EM lifetime and we believe it’s due to (1) The ALPS process has less Cu precipitation at the interface between Al and Ti/TiN, which makes Cu more concentrated in the AlCu layer (2) The Glue layer of Ti forms TiAl3, and these intermetallic compounds changes the AlCu ratio. The Al atomic ratio decreases, while the Cu atomic ratio increases .The formation of Ti3Al intermetallic compounds increased the Cu concentration in the grain boundary of AlCu metal line and affected the EM result.
{"title":"A Study on AlCu with ALPS Al and Glue layer on Electromigration","authors":"Shih-Hui Lin","doi":"10.1109/IPFA55383.2022.9915782","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915782","url":null,"abstract":"It has been reported, that EM lifetime of Ti/Al-Cu structure is shorter than that of Ti/TiN/Al-Cu structure. Our study shows that the lifetime of Ti/ALPS Al-Cu structure is better than Ti/TiN/ALPS Al-Cu. In this paper, we will discuss the effect of the Glue layer -Ti/TiN & Ti, and the effect of the AlCu processes-Hot Al and ALPS/Hot Al to explain the main reasons. After the study, we found Ti /ALPS/Hot Al-Cu has the best EM lifetime and we believe it’s due to (1) The ALPS process has less Cu precipitation at the interface between Al and Ti/TiN, which makes Cu more concentrated in the AlCu layer (2) The Glue layer of Ti forms TiAl3, and these intermetallic compounds changes the AlCu ratio. The Al atomic ratio decreases, while the Cu atomic ratio increases .The formation of Ti3Al intermetallic compounds increased the Cu concentration in the grain boundary of AlCu metal line and affected the EM result.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123355731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915713
Mukhil Azhagan Mallaiyan Sathiaseelan, Manoj Yasaswi Vutukuru, Shajib Ghosh, Olivia P. Paradis, M. Tehranipoor, N. Asadizanjani, David Crandall
In this manuscript, we present a new solution to logo detection on printed circuit boards (PCB). With the growing incidence of PCB counterfeits and Trojans, having a quick, automated PCB assurance tool is the need of the hour. Logo detection and verification is an important step in PCB assurance and counterfeit detection. In addition, text recognition in PCBs is made difficult due to logo interference, which can also be solved with our proposed solution. We describe our Deep Neural Network (DNN)-based algorithm along with a description of the dataset used. Finally, we present images as well as qualitative results using common object detection metrics to demonstrate the performance of our proposed approach.
{"title":"Logo Detection and Localization for IC Authentication, Marking Recognition, and Counterfeit Detection","authors":"Mukhil Azhagan Mallaiyan Sathiaseelan, Manoj Yasaswi Vutukuru, Shajib Ghosh, Olivia P. Paradis, M. Tehranipoor, N. Asadizanjani, David Crandall","doi":"10.1109/IPFA55383.2022.9915713","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915713","url":null,"abstract":"In this manuscript, we present a new solution to logo detection on printed circuit boards (PCB). With the growing incidence of PCB counterfeits and Trojans, having a quick, automated PCB assurance tool is the need of the hour. Logo detection and verification is an important step in PCB assurance and counterfeit detection. In addition, text recognition in PCBs is made difficult due to logo interference, which can also be solved with our proposed solution. We describe our Deep Neural Network (DNN)-based algorithm along with a description of the dataset used. Finally, we present images as well as qualitative results using common object detection metrics to demonstrate the performance of our proposed approach.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114770083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915775
Jian-Hsing Lee, Chih-Hsuan Lin, K. Nidhi, Chao-Yang Chen, Yeh-Ning Jou, M. Ker
The failure mechanism of latch-up in two different power domains for the high voltage (HV) output driver under the positive trigger current latch-up test is investigated. From the T-CAD, why the guard-rings (GRs) in two different power domains are damaged is found. It is caused by the conductivity modulation effect as the region between two power domains is triggered into the latch-up state. So, this region becomes an intrinsic region (resistor) to induce power short to power, resulting in the GR damage.
{"title":"The Failure Mechanism of the Guard-Rings in Two Different Power Domains during the Latch-Up Test","authors":"Jian-Hsing Lee, Chih-Hsuan Lin, K. Nidhi, Chao-Yang Chen, Yeh-Ning Jou, M. Ker","doi":"10.1109/IPFA55383.2022.9915775","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915775","url":null,"abstract":"The failure mechanism of latch-up in two different power domains for the high voltage (HV) output driver under the positive trigger current latch-up test is investigated. From the T-CAD, why the guard-rings (GRs) in two different power domains are damaged is found. It is caused by the conductivity modulation effect as the region between two power domains is triggered into the latch-up state. So, this region becomes an intrinsic region (resistor) to induce power short to power, resulting in the GR damage.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116372844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915771
Allah Rakhio Junejo, Hyunseung Ryu, Wooseung Noh, N. Raghavan, Sang-Hun Kim, Jaehyeok Doh
This study focuses on the multi-physics simulation-based prognosis of titanium dioxide nanoparticles (TiO2, NPs) doped in dye-sensitized solar cells (DSSCs), considering optical and electrical properties. The fabrication of TiO2, NPs using the Sol-Gel method (400 oC) is the optimal calcination temperature to achieve an anatase phase. Various physical-chemical properties tests for TiO2, NPs are conducted to understand optical and electrical characterizations utilizing X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), and scanning electron microscopy (SEM) and Ultraviolet-Visible (UV-vis) absorption spectrophotometry. Optical properties such as absorption, bandgap, deflection, and photoluminescence emission are also observed. Based on the best case of high-power energy conversion (PEC) amongst semiconductor material characterizations, multi-physics simulation (optical and electrical properties) for three-dimensional (3D) TiO2, NPs is carried out to acquire time-dependent current data, which is relative to degradation for DSSC. A data-driven prognosis of solar cells is then conducted by using degradation data. According to dye molecule layers, the remaining useful life (RUL) is stochastically predicted. The main contribution is to suggest the framework of multi-physics simulation-based prognosis for power energy applications.
{"title":"Multi-Physics Simulation-Based Prognosis of Titanium Dioxide Nanoparticles-Embedded Solar Cell","authors":"Allah Rakhio Junejo, Hyunseung Ryu, Wooseung Noh, N. Raghavan, Sang-Hun Kim, Jaehyeok Doh","doi":"10.1109/IPFA55383.2022.9915771","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915771","url":null,"abstract":"This study focuses on the multi-physics simulation-based prognosis of titanium dioxide nanoparticles (TiO2, NPs) doped in dye-sensitized solar cells (DSSCs), considering optical and electrical properties. The fabrication of TiO2, NPs using the Sol-Gel method (400 oC) is the optimal calcination temperature to achieve an anatase phase. Various physical-chemical properties tests for TiO2, NPs are conducted to understand optical and electrical characterizations utilizing X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), and scanning electron microscopy (SEM) and Ultraviolet-Visible (UV-vis) absorption spectrophotometry. Optical properties such as absorption, bandgap, deflection, and photoluminescence emission are also observed. Based on the best case of high-power energy conversion (PEC) amongst semiconductor material characterizations, multi-physics simulation (optical and electrical properties) for three-dimensional (3D) TiO2, NPs is carried out to acquire time-dependent current data, which is relative to degradation for DSSC. A data-driven prognosis of solar cells is then conducted by using degradation data. According to dye molecule layers, the remaining useful life (RUL) is stochastically predicted. The main contribution is to suggest the framework of multi-physics simulation-based prognosis for power energy applications.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126067757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915722
Xinyu Ren, M. Ren, Yining Wu, Chao Xu, Hongwei Zhou, Zehong Li, Bo Zhang
Shielded-gate Trench (SGT) MOSFET is widely used in the low-voltage field because of its low specific on resistance and gate-to-drain charge. Like most power MOSFETs, thermal instability reduces the safety operation area (SOA) of the SGT MOSFET. Failure of SGT MOSFET due to thermal instability is observed and the mechanism is studied in this paper. According to simulation, increasing the channel length is an effective means to improve thermal stability of SGT MOSFET. Therefore, the improved SGT MOSFETs, T-shaped gate SGT and L-shaped gate SGT, are proposed. The simulation results show that the improved structures can reduce the current corresponding to zero temperature coefficient by 50%.
{"title":"Thermal instability failure analysis of Shielded-gate Trench MOSFET in linear mode","authors":"Xinyu Ren, M. Ren, Yining Wu, Chao Xu, Hongwei Zhou, Zehong Li, Bo Zhang","doi":"10.1109/IPFA55383.2022.9915722","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915722","url":null,"abstract":"Shielded-gate Trench (SGT) MOSFET is widely used in the low-voltage field because of its low specific on resistance and gate-to-drain charge. Like most power MOSFETs, thermal instability reduces the safety operation area (SOA) of the SGT MOSFET. Failure of SGT MOSFET due to thermal instability is observed and the mechanism is studied in this paper. According to simulation, increasing the channel length is an effective means to improve thermal stability of SGT MOSFET. Therefore, the improved SGT MOSFETs, T-shaped gate SGT and L-shaped gate SGT, are proposed. The simulation results show that the improved structures can reduce the current corresponding to zero temperature coefficient by 50%.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131245071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915741
L. Yeoh, Kok-Cheng Chong, Susan X. Li
EBIC (Electron Beam Induced Current) is a microscopic technique offered by nano-probing system to characterize the electrical property of active circuits in a semiconductor device. EBIC is also a powerful local fault isolation technique which is capable to narrow down the potential physical defect site. In this paper, we will show three case studies of applying EBIC technique coupled with various failure analysis equipment to discover particle defects buried in metal and poly structures in Flash memory devices.
{"title":"EBIC Application in Finding Particle Defects","authors":"L. Yeoh, Kok-Cheng Chong, Susan X. Li","doi":"10.1109/IPFA55383.2022.9915741","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915741","url":null,"abstract":"EBIC (Electron Beam Induced Current) is a microscopic technique offered by nano-probing system to characterize the electrical property of active circuits in a semiconductor device. EBIC is also a powerful local fault isolation technique which is capable to narrow down the potential physical defect site. In this paper, we will show three case studies of applying EBIC technique coupled with various failure analysis equipment to discover particle defects buried in metal and poly structures in Flash memory devices.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128890756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915716
Pengfei Lian, Zebin Kong, Sheng Hu, Rong Zhao, Qing Ji, Jianshe Lou, Kunshu Wang, L. Tang
This paper focus on failure analysis of a full wave phase sensitive demodulator induced by surface defect. A phase sensitive demodulator fails, inducing a big AC signal after the post-amplifier. According to the failure analysis, the failure reason of the phase sensitive demodulator is the surface defect in the interface of the Si and the SiO2. The surface defect decreases the current of the operational amplifier of the phase sensitive demodulator, making the signal suppression of the low frequency noise worse. The failure reappearance is performed by adding a parallel resistance between the power supply and the base of the triode of the operational amplifier. Moreover, three improvement measurements that include electrical test, cleaning and process are proposed, solving the failure phenomenon of the full wave phase sensitive demodulator.
{"title":"Failure Analysis of a Full Wave Phase Sensitive Demodulator Induced by Surface Defect","authors":"Pengfei Lian, Zebin Kong, Sheng Hu, Rong Zhao, Qing Ji, Jianshe Lou, Kunshu Wang, L. Tang","doi":"10.1109/IPFA55383.2022.9915716","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915716","url":null,"abstract":"This paper focus on failure analysis of a full wave phase sensitive demodulator induced by surface defect. A phase sensitive demodulator fails, inducing a big AC signal after the post-amplifier. According to the failure analysis, the failure reason of the phase sensitive demodulator is the surface defect in the interface of the Si and the SiO2. The surface defect decreases the current of the operational amplifier of the phase sensitive demodulator, making the signal suppression of the low frequency noise worse. The failure reappearance is performed by adding a parallel resistance between the power supply and the base of the triode of the operational amplifier. Moreover, three improvement measurements that include electrical test, cleaning and process are proposed, solving the failure phenomenon of the full wave phase sensitive demodulator.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130633530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915717
Kok Heng Lau, C. N. Liew, L.L. Goh, Siew Ming Lim, Jack Yi Jie Ng
Effective test coverage served as a gate keeper for device failure screening, this is to ensure none of the failing part escaped to customer side. Samples that failed electrically be means in class test and reliability stress test will need failure analysis for defect root causing. This is crucial for continuous product quality improvement. Physical defect localization to enable defect finding highly depends on optical fault isolation (FI) for defect localization and physical failure analysis (PFA) techniques ranging from sample delayering, secondary electron microscope (SEM) imaging and transmission electron microscopy (TEM) to reveal the physical defect. In certain cases where the failure is suspected to be internal regulated power line induced the section on area for SEM will be much too large. Extensive nano probing is required to isolate the failing region. This along with FIB edit and pico probe will be able to provide electrical failure correlation and to create a hypothesis. In this work, a complete failure analysis fault isolation (FAFI) method using the afore mentioned techniques to lock down the physical defect caused by power rail short reported in power-up-power-down (PUSPDS) test is presented.
{"title":"Internal Power Net Defect Localization Via Holistic Fault Isolation With FIB Edit Pico Probe","authors":"Kok Heng Lau, C. N. Liew, L.L. Goh, Siew Ming Lim, Jack Yi Jie Ng","doi":"10.1109/IPFA55383.2022.9915717","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915717","url":null,"abstract":"Effective test coverage served as a gate keeper for device failure screening, this is to ensure none of the failing part escaped to customer side. Samples that failed electrically be means in class test and reliability stress test will need failure analysis for defect root causing. This is crucial for continuous product quality improvement. Physical defect localization to enable defect finding highly depends on optical fault isolation (FI) for defect localization and physical failure analysis (PFA) techniques ranging from sample delayering, secondary electron microscope (SEM) imaging and transmission electron microscopy (TEM) to reveal the physical defect. In certain cases where the failure is suspected to be internal regulated power line induced the section on area for SEM will be much too large. Extensive nano probing is required to isolate the failing region. This along with FIB edit and pico probe will be able to provide electrical failure correlation and to create a hypothesis. In this work, a complete failure analysis fault isolation (FAFI) method using the afore mentioned techniques to lock down the physical defect caused by power rail short reported in power-up-power-down (PUSPDS) test is presented.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130216723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915748
I. Matacena, L. Maresca, M. Riccio, A. Irace, G. Breglio, A. Castellazzi, S. Daliento
In this paper the effects of SiC/SiO2 interface traps on SiC MOSFETs Gate Capacitance are investigated when a positive bias is applied at the Drain terminal. The Gate capacitance arising from this configuration shows an unexpected sharp peak, exceeding the oxide capacitance, for a Gate voltage close to the threshold voltage. The properties of such peak are studied through numerical analysis. Results affirm that the peak is related to the displacement current, and its origin lies in the channel region. The so-measured Gate capacitance can allow the extraction of important interface properties, such as traps concentration at the SiC/SiO2 interface. Also the effects of temperature on this peak are investigated through experimental and numerical analysis
{"title":"SiC/SiO2 interface traps effect on SiC MOSFETs Gate capacitance with biased Drain","authors":"I. Matacena, L. Maresca, M. Riccio, A. Irace, G. Breglio, A. Castellazzi, S. Daliento","doi":"10.1109/IPFA55383.2022.9915748","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915748","url":null,"abstract":"In this paper the effects of SiC/SiO2 interface traps on SiC MOSFETs Gate Capacitance are investigated when a positive bias is applied at the Drain terminal. The Gate capacitance arising from this configuration shows an unexpected sharp peak, exceeding the oxide capacitance, for a Gate voltage close to the threshold voltage. The properties of such peak are studied through numerical analysis. Results affirm that the peak is related to the displacement current, and its origin lies in the channel region. The so-measured Gate capacitance can allow the extraction of important interface properties, such as traps concentration at the SiC/SiO2 interface. Also the effects of temperature on this peak are investigated through experimental and numerical analysis","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123346581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915783
C. Boit, J. Jatzkowski, F. Altmann, M. DiBattista, S. Silverman, G. Zwicker, N. Herfurth, E. Amini, J.-P. Seifert
The backside approach of contactless fault isolation (CFI) was comfortable as long as it could be carried out with Near Infra-Red (NIR) optical techniques. But even with a solid immersion lens (SIL), the resolution was limited to ~180nm, corresponding to ca. 40nm node integrated circuit (IC) technologies. However, with failure analysis (FA) experience and circuit simulation, it was still successful down to 14 nm FinFET technology. There are several attempts to keep optical CFI competitive because the FA community has enormous experience to read and interpret the obtained signals. Two major strategies are out to save optical CFI for smaller nanoscale IC technologies: (1) shorter wavelength increases resolution by practically max. 2X, but then optical absorption is increasing by orders of magnitude so bulk silicon has to get very thin, and (2) sticking to NIR resolution and work with the signal mix coming from ca. 10 FETs inside the optical spot, requiring an increasing level of circuit and device knowledge involving big data and Artificial Intelligence/Machine Learning (AI/ML).Here, another way out will be presented: (3) fault isolation techniques with real nanoscale resolution like e-beam probing, backside nanoprobing and even near-field optical microscopy are possible if only the back surface of the IC is very close to the active device. This Ultra-Thin Silicon Back Surface (UTSBS) has already been explored to a certain extent. This work shows an overview about the results that are available and the still open field of opportunities. These techniques also support CFI in 3D systems. The sample preparation is very challenging as it has to get down very close to the device of interest but gives more degrees of freedom as only local planarity in a trench is required. No space for a SIL has to be created and the imaging or probing techniques have a long working distance.So, the ultra-thinning may be only necessary in local area, offering a number of preparation solutions consisting of mainly FIB trenching and laser etching. They can as well be composed of these techniques. It will also be presented how beneficial chemical mechanical polishing (CMP) can be.
{"title":"The IC Ultra-Thin Back Surface - A Field of Real Nanoscale Fault Isolation Opportunities Requiring a Skillful Sample Preparation","authors":"C. Boit, J. Jatzkowski, F. Altmann, M. DiBattista, S. Silverman, G. Zwicker, N. Herfurth, E. Amini, J.-P. Seifert","doi":"10.1109/IPFA55383.2022.9915783","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915783","url":null,"abstract":"The backside approach of contactless fault isolation (CFI) was comfortable as long as it could be carried out with Near Infra-Red (NIR) optical techniques. But even with a solid immersion lens (SIL), the resolution was limited to ~180nm, corresponding to ca. 40nm node integrated circuit (IC) technologies. However, with failure analysis (FA) experience and circuit simulation, it was still successful down to 14 nm FinFET technology. There are several attempts to keep optical CFI competitive because the FA community has enormous experience to read and interpret the obtained signals. Two major strategies are out to save optical CFI for smaller nanoscale IC technologies: (1) shorter wavelength increases resolution by practically max. 2X, but then optical absorption is increasing by orders of magnitude so bulk silicon has to get very thin, and (2) sticking to NIR resolution and work with the signal mix coming from ca. 10 FETs inside the optical spot, requiring an increasing level of circuit and device knowledge involving big data and Artificial Intelligence/Machine Learning (AI/ML).Here, another way out will be presented: (3) fault isolation techniques with real nanoscale resolution like e-beam probing, backside nanoprobing and even near-field optical microscopy are possible if only the back surface of the IC is very close to the active device. This Ultra-Thin Silicon Back Surface (UTSBS) has already been explored to a certain extent. This work shows an overview about the results that are available and the still open field of opportunities. These techniques also support CFI in 3D systems. The sample preparation is very challenging as it has to get down very close to the device of interest but gives more degrees of freedom as only local planarity in a trench is required. No space for a SIL has to be created and the imaging or probing techniques have a long working distance.So, the ultra-thinning may be only necessary in local area, offering a number of preparation solutions consisting of mainly FIB trenching and laser etching. They can as well be composed of these techniques. It will also be presented how beneficial chemical mechanical polishing (CMP) can be.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123397357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：